CN111146193B - 半导体装置组合件和其制造方法 - Google Patents

半导体装置组合件和其制造方法 Download PDF

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CN111146193B
CN111146193B CN201911067483.6A CN201911067483A CN111146193B CN 111146193 B CN111146193 B CN 111146193B CN 201911067483 A CN201911067483 A CN 201911067483A CN 111146193 B CN111146193 B CN 111146193B
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semiconductor device
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CN111146193A (zh
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C·H·育
O·R·费伊
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Micron Technology Inc
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Abstract

本申请案涉及半导体装置组合件和其制造方法。一种半导体装置组合件，其包含直接连接到衬底的第一侧的第一半导体装置和第二半导体装置及连接到所述衬底的第二侧的多个互连件。所述衬底经配置以使得所述第一半导体装置和所述第二半导体装置能够通过所述衬底彼此通信。所述衬底可以是硅衬底，其包含互补型金属氧化物半导体CMOS电路。所述第一半导体装置可以是处理单元，且所述第二半导体装置可以是存储器装置，其可以是高带宽存储器装置。一种制造半导体装置组合件的方法包含将CMOS处理应用于硅衬底、在所述衬底的第一侧上形成后段工艺BEOL层、将存储器装置和处理单元直接附接到所述BEOL层，及在所述衬底的所述第二侧上形成重布层。

Description

半导体装置组合件和其制造方法
技术领域
本文中所描述的实施例涉及具有直接连接到衬底的处理单元和存储器装置的半导体装置组合件和制造半导体装置组合件的方法，所述衬底可以是使得半导体装置组合件能够连接到例如图形卡的另一装置的硅衬底。所述衬底可包含互补型金属氧化物半导体(CMOS)电路。所述处理单元可以是图形处理单元(GPU)或中央处理单元(CPU)，并且所述存储器装置可以是高带宽存储器装置。
背景技术
高带宽存储器通常是包含动态随机存取存储器(DRAM)的堆叠的高性能随机存取存储器(RAM)接口，所述DRAM的堆叠具有穿过DRAM堆叠的硅穿孔(TSV)。高带宽存储器通常封装于具体配置中以使得高带宽存储器能够由例如但不限于图形卡的另一装置使用。
图6展示现有半导体装置组合件400的侧视示意图，所述现有半导体装置组合件包含由爱达荷州博伊西市(Boise，Idaho)的Micron Technology公司提供的多个混合存储器立方体(HMC)430。HMC包含彼此堆叠的多个存储器裸片，通常四(4)个到八(8)个，且使用TSV来互连存储器单元。HMC包含作为单独裸片集成的存储器控制器。HMC的底侧上的微凸块可用于将HMC连接到另一装置，例如但不限于图形卡。
半导体装置组合件400包含衬底或印刷电路板(PCB)410，所述印刷电路板具有第一侧或顶侧411和与第一侧411相对的第二侧或底侧412。硅中介层420连接到衬底410的第一侧411。中介层420具有第一侧或顶侧421和与第一侧421相对的第二侧或底侧422。衬底410的第二侧412上的多个互连件401可用于将半导体装置组合件400连接到另一装置，如所属领域的一般技术人员将了解。半导体装置组合件400可在半导体装置组合件400的每一组件之间包含多个互连元件(未展示)，如所属领域的一般技术人员将了解。
GPU或CPU 440直接连接到中介层420的第一侧421。半导体装置组合件400包含至少一个HMC 430。举例来说，四个HMC 430可连接到半导体装置组合件400。然而，HMC 430不直接连接到中介层420的第一侧421。确切地说，每一HMC 430连接到接口裸片450。接着，包括HMC 430和接口裸片450的所述组合件连接到中介层420。半导体装置组合件400在每一HMC 430与中介层420之间需要接口裸片450，从而增加了半导体装置组合件400的成本和/或复杂性。
可能存在额外缺陷和缺点。
发明内容
在一个方面中，本申请案提供一种半导体装置组合件，其包括：衬底，其具有第一侧和第二侧，所述衬底具有多个互补型金属氧化物半导体电路；第一半导体装置，其直接连接到所述衬底的所述第一侧；第二半导体装置，其直接连接到所述衬底的所述第一侧，其中所述衬底经配置以使得所述第一半导体装置和所述第二半导体装置能够通过所述衬底彼此通信；重布层，其定位于所述衬底的所述第二侧上；及多个互连件，其连接到所述重布层，其中所述重布层实现所述多个互连件与至少所述第一半导体装置之间的连接。
在另一方面中，本申请案提供一种半导体装置组合件，其包括：硅衬底，其具有第一侧和第二侧，所述硅衬底具有互补型金属氧化物半导体电路并且所述第一侧包含后段工艺(BEOL)层；图形处理单元(GPU)或中央处理单元(CPU)，其直接连接到所述硅衬底的所述BEOL层；及多个存储器装置，其直接连接到所述硅衬底的所述BEOL层，其中所述GPU或CPU及所述多个存储器装置彼此通过所述硅衬底通信。
在另一方面中，本申请案提供一种制造半导体装置组合件的方法，其包括：将互补型金属氧化物半导体处理应用于硅衬底；在所述硅衬底的第一侧上形成后段工艺(BEOL)层；将第一半导体装置直接附接到所述BEOL层；将第二半导体装置直接附接到所述BEOL层；在所述硅衬底的第二侧上形成重布层；及将多个焊球附接到所述重布层。
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图1是半导体装置组合件的实施例的侧视示意图。
图2是半导体装置组合件的实施例的俯视示意图。
图3是半导体装置组合件的实施例的横截面示意图。
图4是制造半导体装置组合件的方法的实施例的流程图。
图5是制造半导体装置组合件的方法的实施例的流程图。
图6是现有半导体装置组合件的侧视示意图。
图7是制造半导体装置组合件的现有方法的流程图。
虽然本公开易有各种修改和替代形式，但具体实施例已经在图式中作为实例展示且将在本文中详细描述。然而，应理解，本公开不意欲限于所公开的特定形式。实际上，意图是涵盖属于如由所附权利要求书限定的本公开的范围内的所有修改、等效物和替代方案。
具体实施方式
在本公开中，论述了许多具体细节以提供对本公开的实施例的透彻且启发性描述。所属领域的一般技术人员将认识到，可在并无具体细节中的一或多个的情况下实践本公开。可能不展示和/或可能不详细描述常常与半导体装置和半导体装置封装相关联的熟知结构和/或操作，以避免混淆本公开的其它方面。一般来说，应理解，除了本文中所公开的那些具体实施例之外的各种其它装置、系统和/或方法也可在本公开的范围内。
术语“半导体装置组合件”可指一或多个半导体装置、半导体装置封装和/或衬底的组合件，所述衬底可包含中介层、支撑件和/或其它合适的衬底。半导体装置组合件可制造为但不限于离散封装件形式、条带或矩阵形式和/或晶片面板形式。术语“半导体装置”大体上是指包含半导体材料的固态装置。半导体装置可包含例如来自晶片或衬底的半导体衬底、晶片、面板或单个裸片。半导体装置在本文中可是指一种半导体裸片，但半导体装置不限于半导体裸片。
如本文中所使用，术语“竖直”、“横向”、“上部”和“下部”可指图中所展示的特征在半导体装置和/或半导体装置组合件中的相对方向或位置。举例来说，“上部”或“最上部”可指比另一特征更接近页面顶部定位的特征。然而，这些术语应被广泛地解释为包含具有例如颠倒或倾斜定向等其它定向的半导体装置和/或半导体装置组合件，其中顶部/底部、上方/下方、高于/低于、向上/向下和左边/右边可取决于定向而互换。
本公开的各个实施例涉及半导体装置、半导体装置组合件、半导体封装、半导体装置封装，以及制造和/或操作半导体装置的方法。
本公开的实施例是一种包括衬底的半导体装置组合件，所述衬底具有第一侧和第二侧，所述衬底具有多个互补型金属氧化物半导体(CMOS)电路。半导体装置组合件包含直接连接到衬底的第一侧的第一半导体装置和直接连接到衬底的第一侧的第二半导体装置。所述衬底经配置以使得第一半导体装置和第二半导体装置能够通过衬底彼此通信。半导体装置组合件包含定位于衬底的第二侧上的重布层和连接到所述重布层的多个互连件，其中所述重布层实现多个互连件与至少第一半导体装置之间的连接。第一半导体装置可以是处理单元，例如图形处理器，且第二半导体装置可以是存储器装置，例如高带宽存储器装置。
本公开的实施例是一种包括硅衬底的半导体装置组合件，所述硅衬底具有第一侧和第二侧，所述硅衬底具有CMOS电路且第一侧包含后段工艺(BEOL)层。半导体装置组合件包含直接连接到硅衬底的BEOL层的图形处理单元(GPU)或中央处理单元(CPU)。半导体装置组合件包含直接连接到硅衬底的BEOL层的多个存储器装置，其中GPU或CPU和多个存储器装置通过硅衬底彼此通信。多个存储器装置可以是高带宽存储器装置。
本公开的实施例是一种制造半导体装置组合件的方法。所述方法包括将CMOS处理应用于硅衬底及在硅衬底的第一侧上形成BEOL层。所述方法包含将第一半导体装置直接附接到BEOL层及将第二半导体装置直接附接到BEOL层。所述方法包括在硅衬底的第二侧上形成重布层及将多个焊球附接到重布层。第一半导体装置可以是处理单元，例如图形处理器，且第二半导体装置可以是存储器装置，例如高带宽存储器装置。多个焊球使得半导体装置组合件能够连接到另一装置。
本公开的实施例是一种制造半导体装置组合件的方法。所述方法包括将多个半导体装置附接到硅晶片的第一侧上。所述方法包含将多个个别图形处理单元附接到硅晶片的第一侧上。所述方法包含在硅晶片的第二侧上产生重布层及将多个互连件附接到硅晶片的第二侧上的重布层。所述方法包含处理硅晶片以形成多个个别半导体装置组合件，所述多个个别半导体装置组合件各自包括至少一个半导体装置和个别图形处理单元。
图1是半导体装置组合件100的实施例的侧视示意图。半导体装置组合件100包含衬底110，其具有第一侧或顶侧111和与第一侧111相对的第二侧或底侧112。所述衬底110可以是但不限于硅衬底。所述衬底110包含背侧重布层115，其在衬底110与衬底110的第二侧112上的多个互连件101之间提供电连接。多个互连件101使得半导体装置组合件100能够连接到例如但不限于图形卡的另一装置。
第一半导体装置140直接连接到衬底110的第一侧111。同样地，第二半导体装置130直接连接到衬底110的第一侧111。第一半导体装置140可以是处理单元，例如但不限于，GPU或中央处理单元(CPU)。第二半导体装置130可以是存储器装置。CMOS处理可能已应用于衬底110以使得衬底110能够经配置以通过衬底110实现第一半导体装置140与第二半导体装置130之间的通信。对衬底110的CMOS处理在衬底110内创建了CMOS晶体管栅极，所述CMOS晶体管栅极充当用于第一半导体装置140、第二半导体装置130和/或经由多个互连件101连接到半导体装置组合件100的外部装置之间的数据传送的缓冲器。所述CMOS晶体管栅极还可充当用以控制第一半导体装置140、第二半导体装置130和/或经由多个互连件101连接到半导体装置组合件100的外部装置之间的数据传送的逻辑。
在一实施例中，第二半导体装置130可以是但不限于高带宽存储器装置。如本文中所使用，高带宽存储器装置是任选地包含基底裸片的DRAM裸片与存储器控制器的堆叠，它们通过硅穿孔(TSV)互连，且在底侧上具有微凸块，即由爱达荷州博伊西市的美光科技(Micron Technology)公司提供的HMC等。
图2是半导体装置组合件100的实施例的俯视示意图。半导体装置组合件100包含具有第一侧或顶侧111的衬底110。衬底110可以是但不限于硅衬底。第一半导体装置140直接连接到衬底110的第一侧111。同样地，多个第二半导体装置130直接连接到衬底110的第一侧111。第一半导体装置140可以是处理单元，例如但不限于GPU，且
第二半导体装置130可以是高带宽存储器装置。CMOS处理可能已应用于硅衬底110以使得衬底110能够经配置以通过衬底110实现第一半导体装置140与第二半导体装置130之间的通信。
图3是半导体装置组合件100的实施例的横截面示意图。半导体装置组合件100包含一或多个高带宽存储器装置130。高带宽存储器装置130是电连接在一起的存储器胞元或裸片131A到131F的堆叠，如受益于本公开的所属领域的一般技术人员将了解。出于说明性目的展示存储器胞元131A到131F的数目，且其可取决于应用而变化，如所属领域的一般技术人员将了解。高带宽存储器装置130通过多个互连件102直接连接到衬底110。处理单元140还通过多个互连件103直接连接到衬底。
衬底110可以是硅衬底并且包含第一侧或顶侧111和第二侧或底侧112。衬底110可包含邻近衬底110的第一侧111的多个后段工艺(BEOL)层113。BEOL层113可包括交替的介电层113A和导电层113B。BEOL层113提供衬底110内的布线层，且将高带宽存储器装置130和处理单元140电连接到延伸通过衬底110的多个TSV 114，如所属领域的一般技术人员将了解。
衬底110可包含邻近衬底110第二侧112的背侧重布层115。背侧重布层115可包括交替的导电层115A和介电层115B。背侧重布层115将高带宽存储器装置130和处理单元140电连接到衬底110的第二侧112上的多个互连件101，如所属领域的一般技术人员将了解。衬底110的第二侧112上的多个互连件101使得半导体装置组合件100能够连接到另一装置，如受益于本公开的所属领域的一般技术人员将了解。
CMOS处理可应用于如本文中所论述的衬底110。CMOS处理可应用于如本文中所论述的衬底110，如由CMOS层116示意性地指示。衬底110的CMOS层116包含CMOS晶体管栅极，如受益于本公开的所属领域的一般技术人员将了解。出于说明性目的展示CMOS层116的大小、形状、位置和/或配置，且其可变化，如受益于本公开的所属领域的一般技术人员将了解。
图4是制造半导体装置组合件的方法200的实施例的流程图。方法200包括在210处将CMOS处理应用于硅衬底。方法200包含在220处在硅衬底的第一侧上形成BEOL层。在230处，方法200包含将第一半导体装置直接附接到衬底的BEOL层。方法200包含在240处将第二半导体装置直接附接到衬底的BEOL层。第一半导体装置可以是处理单元，且第二半导体装置可以是存储器装置，例如高带宽存储器装置。方法200包含在250处在硅衬底的第二侧上形成重布层及在260处将多个焊球附接到重布层。
图5是制造半导体装置组合件的方法300的实施例的流程图。方法300包含在310处向晶片提供附接到晶片的多个处理单元及单一化所述晶片以产生多个个别处理单元。所述处理单元可以是图形处理单元。在320处，方法300包含将多个半导体装置附接到硅晶片上。半导体装置可以是存储器装置，且具体地说可以是高带宽存储器装置。所述方法300包含在315处单一化所述晶片以产生多个个别处理单元。所述方法300包含在330处将多个个别处理单元附接到硅晶片的第一表面或侧上。所述处理单元结合一或多个半导体装置附接到硅晶片。
方法300包含在340处模制和/或研磨硅晶片的部分以更好地使得焊球能够附接到衬底的部分和/或用于大体保护硅免于外部应力和/或环境影响。在350处，方法300包含将硅晶片的第一表面附接到载体晶片。载体晶片使得能够对硅晶片的第二表面实行处理。方法300包含在360处在硅晶片的第二表面上产生重布层，及在370处将多个焊球附接到重布层。方法300包含在380处将硅晶片与载体晶片解除接合。方法300包含在390处单一化硅晶片以产生多个半导体装置组合件，每一半导体装置组合件具有附接到硅晶片的一部分的至少一个处理单元和至少一个半导体装置。半导体装置组合件接着可连接到例如但不限于图形卡的另一装置。
制造半导体装置组合件的方法300实现使用比当前方法少的步骤产生多个半导体装置组合件。制造半导体装置组合件的方法300使如本文中关于图7展示的制造半导体装置组合件的过程或现有方法呈流线型。
图7是制造半导体装置组合件的现有方法500的流程图。方法500包含在510处提供处理器晶片，及在515处单一化处理器晶片以产生多个个别处理单元。方法500需要在520处将例如高带宽存储器装置的多个半导体装置附接到控制器或接口晶片，及在525处单一化控制器晶片以提供附接到控制器裸片的个别半导体装置。
方法500包含在530处提供中介层晶片，及在540处将插入晶片单一化成个别裸片。方法500包含在550处提供衬底及在555处将中介层裸片附接到衬底上。在中介层裸片附接到衬底之后，方法500包含在560处将控制器裸片附接到中介层裸片上，所述控制器裸片具有附接到其的半导体装置。半导体装置组合件可包含多个半导体装置。每一半导体装置在520处附接到控制器晶片，并且将当在525处单一化控制器晶片时附接到控制器裸片。每一半导体装置将接着需要在560处经由经附接控制器裸片附接到中介层裸片。方法500包含在565处将个别处理单元附接到中介层裸片上。方法500包含在570处模制和/或研磨衬底的部分以更好地使得焊球能够附接到衬底的部分和/或用于大体保护硅免于外部应力和/或环境影响。方法500包含在580处将多个焊球附接到衬底。半导体装置组合件接着可连接到例如但不限于图形卡的另一装置。
尽管已经关于某些实施例描述了本公开，但对于所属领域的技术人员显而易见的其它实施例(包含并不提供本文中所阐述的所有特征和优点的实施例)同样在本公开的范围内。本公开可涵盖本文中未明确地展示或描述的其它实施例。因此，本公开的范围仅参考所附权利要求书和其等效物界定。

Claims (16)

1.一种半导体装置组合件，其包括：
衬底，其具有第一侧和第二侧，所述衬底具有多个互补型金属氧化物半导体电路；
第一半导体装置，其直接连接到所述衬底的所述第一侧；
第二半导体装置，其直接连接到所述衬底的所述第一侧，其中所述衬底经配置以使得所述第一半导体装置和所述第二半导体装置能够通过所述衬底彼此直接地通信；
重布层，其定位于所述衬底的所述第二侧上；及
多个互连件，其连接到所述重布层，其中所述重布层实现所述多个互连件与至少所述第一半导体装置之间的连接。
2.根据权利要求1所述的半导体装置组合件，其中所述多个互补型金属氧化物半导体电路提供用于所述第一半导体装置与所述第二半导体装置之间的数据传送的缓冲器。
3.根据权利要求2所述的半导体装置组合件，其中所述多个互补型金属氧化物半导体电路提供用以控制所述第一半导体装置与所述第二半导体装置之间的数据传送的逻辑。
4.根据权利要求1所述的半导体装置组合件，其中所述衬底是硅衬底，其经配置以将所述第一半导体装置和所述第二半导体装置连接到所述重布层。
5.根据权利要求4所述的半导体装置组合件，其中所述第一半导体装置是处理单元。
6.根据权利要求5所述的半导体装置组合件，其中所述处理单元进一步包括图形处理单元GPU或中央处理单元CPU。
7.根据权利要求6所述的半导体装置组合件，其中所述第二半导体装置是存储器装置。
8.根据权利要求7所述的半导体装置组合件，其中所述存储器装置进一步包括高带宽存储器装置。
9.根据权利要求4所述的半导体装置组合件，其进一步包括直接连接到所述硅衬底的所述第一侧的第三半导体装置，其中所述第三半导体装置是存储器装置且其中所述第一半导体装置和所述第三半导体装置通过所述硅衬底彼此通信。
10.根据权利要求1所述的半导体装置组合件，其中所述衬底的所述第一侧包括后段工艺BEOL层且其中所述第一半导体装置和所述第二半导体装置直接连接到所述BEOL层。
11.根据权利要求10所述的半导体装置组合件，其包括穿过所述衬底的多个通孔，其中所述多个通孔将所述BEOL层电连接到所述重布层。
12.一种半导体装置组合件，其包括：
硅衬底，其具有第一侧和第二侧，所述硅衬底具有互补型金属氧化物半导体电路，且所述第一侧包含后段工艺BEOL层；
图形处理单元GPU或中央处理单元CPU，其直接连接到所述硅衬底的所述BEOL层；及
多个存储器装置，其直接连接到所述硅衬底的所述BEOL层，其中所述GPU或CPU及所述多个存储器装置通过所述硅衬底彼此直接地通信。
13.根据权利要求12所述的半导体装置组合件，其中所述互补型金属氧化物半导体电路提供用于所述GPU或CPU与所述多个存储器装置之间的数据传送的缓冲器。
14.根据权利要求12所述的半导体装置组合件，其中所述多个存储器装置包括至少两个高带宽存储器装置。
15.根据权利要求12所述的半导体装置组合件，其包括所述硅衬底的所述第二侧上的重布层，所述重布层连接到多个焊球。
16.根据权利要求15所述的半导体装置组合件，其进一步包括穿过所述硅衬底的至少一个通孔，所述至少一个通孔将所述BEOL层电连接到所述重布层。
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