CN111145679A - Bidirectional grid driving array circuit - Google Patents
Bidirectional grid driving array circuit Download PDFInfo
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- CN111145679A CN111145679A CN202010111190.XA CN202010111190A CN111145679A CN 111145679 A CN111145679 A CN 111145679A CN 202010111190 A CN202010111190 A CN 202010111190A CN 111145679 A CN111145679 A CN 111145679A
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- 230000002457 bidirectional effect Effects 0.000 title abstract description 37
- 239000000872 buffer Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 16
- 230000003139 buffering effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a bidirectional grid driving array circuit which comprises a grid driving circuit, a forward scanning redundancy circuit, a reverse scanning redundancy circuit and a selection circuit. The gate driving circuit comprises a plurality of driving shift registers respectively coupled to the scanning lines of the pixels. The positive scan redundancy circuit is coupled to the last shift register, and the negative scan redundancy circuit is coupled to the first shift register. The selection circuit is respectively coupled with the grid driving circuit, the forward scanning redundancy circuit and the reverse scanning redundancy circuit, and the selection circuit closes the reverse scanning redundancy circuit according to a forward scanning signal or closes the forward scanning redundancy circuit according to a reverse scanning signal.
Description
Technical Field
The present invention relates to a Gate On Array (GOA) circuit, and more particularly, to a GOA circuit capable of reducing required line buffering.
Background
For various display devices, a plurality of pixel units included in the display device can transmit a plurality of gate driving signals to each pixel unit by arranging a gate driving array circuit, and control the on/off of each pixel unit or control the brightness of pixels to enable the display device to present a corresponding picture.
In the scanning technology, a display device capable of bidirectional scanning is already provided, and display quality is expected to be improved by scanning in different directions. However, the control circuit for performing bidirectional scanning needs to consume more line buffers to achieve the bidirectional scanning effect during scanning due to the arrangement of circuit elements, and the hardware arrangement is rather expensive and wasteful, so how to overcome the above problems is an important issue to be addressed.
In summary, the conventional bidirectional gate driver array circuit still has a considerable defect in use, so that the invention improves the defect of the prior art by designing a circuit capable of reducing line buffer, thereby ensuring that the bidirectional gate driver array circuit can be applied to most control chips and further enhancing the industrial application.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a bidirectional gate driving array circuit, which reduces the problem of large amount of line temporary storage required during scanning by the bidirectional gate driving array circuit through the design of the selection circuit.
In accordance with the above objectives, the present invention provides a bidirectional gate driving array circuit, which includes a gate driving circuit (GOA circuit), a positive scan redundancy (dummy) circuit, a negative scan redundancy (dummy) circuit, and a selection circuit. The gate driving circuit receives a forward scanning signal and performs forward scanning from the first shift register towards the last shift register, or receives a reverse scanning signal and performs reverse scanning from the last shift register towards the first shift register. The positive scan redundancy circuit includes a plurality of positive scan redundancy shift registers, and a first positive scan redundancy shift register of the positive scan redundancy circuit is coupled to a last shift register. The anti-scan redundancy circuit comprises a plurality of anti-scan redundancy shift registers, and the last anti-scan redundancy shift register of the anti-scan redundancy circuit is coupled to the first shift register. The selection circuit is respectively coupled with the grid driving circuit, the forward scanning redundancy circuit and the reverse scanning redundancy circuit, and the selection circuit closes the reverse scanning redundancy circuit according to a forward scanning signal or closes the forward scanning redundancy circuit according to a reverse scanning signal.
Specifically, the selection circuit may include a first switch, a second switch, a third switch and a fourth switch, wherein the first switch is coupled to the first reverse scan redundancy shift register of the reverse scan redundancy circuit, the second switch is coupled to the first shift register, the third switch is coupled to the last shift register, and the fourth switch is coupled to the last forward scan redundancy shift register of the forward scan redundancy circuit. The forward scanning signal turns off the first switch and the third switch to disconnect the first reverse scanning redundant shift register and the last shift register, and turns on the second switch and the fourth switch to connect the first shift register and the last forward scanning redundant shift register for forward scanning, or the reverse scanning signal turns off the second switch and the fourth switch to disconnect the first shift register and the last forward scanning redundant shift register, and turns on the first switch and the third switch to connect the first reverse scanning redundant shift register and the last shift register for reverse scanning.
As described above, according to the bidirectional gate driving array circuit disclosed in the embodiment of the present invention, the reverse scan redundancy circuit can be avoided during the forward scan, and the number of required line buffers can be reduced; similarly, when scanning in the reverse direction, the redundancy circuit in the forward scanning can be avoided, and the number of required line buffers is reduced. Therefore, the number of line buffers required to be supported by the control chip of the bidirectional grid drive array circuit is saved, thereby reducing the overall cost and increasing the selectivity of the applicable chip.
Drawings
In order to make the technical features, contents and advantages of the present invention, and technical effects thereof, more apparent, the present invention will be described in detail with reference to the accompanying drawings, which are used for expressing forms of embodiments, wherein:
fig. 1 is a schematic diagram of a bidirectional gate driving array circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a bidirectional gate driving array circuit according to another embodiment of the invention.
Fig. 3 is a waveform diagram of a bidirectional gate driving array circuit according to another embodiment of the invention.
FIG. 4 is a schematic diagram of a bidirectional gate driving array circuit according to another embodiment of the invention.
FIG. 5 is a schematic diagram of a bidirectional gate driving array circuit according to still another embodiment of the invention.
FIG. 6 is a waveform diagram of a one-to-three bidirectional gate driving array circuit according to an embodiment of the present invention.
FIG. 7 is a waveform diagram of a one-fifth bi-directional gate driving array circuit according to an embodiment of the present invention.
Description of reference numerals:
10. 20, 30, 40: bidirectional grid driving array circuit
11. 21, 31, 41: gate drive circuit
12. 22, 32, 42: forward scan redundancy circuit
13. 23, 33, 43: anti-scan redundancy circuit
14: selection circuit
CK 1-CK 8: clock signal
Da: data of
DP 1-DPm, D5-D8: forward-scanning redundant shift register
DR 1-DRm, D1-D4: anti-sweep redundant shift register
D/U: reverse scanning signal line
D2U: inverse scan signal
G1-Gn: drive shift register
G (1) to G (n): gate drive signal
H1-H14: clock period
PS: forward scanning
And RS: reverse scan
ST, ST (1) to ST (n), VST: initiating signal
S1: first selection circuit
S2: second selection circuit
S3: third selection circuit
S4: fourth selection circuit
TN 1-TN 4: n-type transistor
TP 1-TP 2: p-type transistor
U/D: forward scanning signal line
U2D: forward scanning signal
Detailed Description
To facilitate understanding of the technical features, contents, and advantages of the present invention and the technical effects achieved thereby, the present invention will be described in detail with reference to the accompanying drawings in the form of embodiments, wherein the drawings are provided for illustration and an auxiliary specification, and are not necessarily true to scale and precise arrangement after the implementation of the present invention, and therefore, the appended claims should not be read as limiting the present invention to the actual implementation of the claims.
In the drawings, the thickness or width of layers, films, panels, regions, light guides, and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected," may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements. Further, it will be understood that, although the terms "first", "second", "third" and/or the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should be used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Therefore, they are used for descriptive purposes only and not to be construed as indicating or implying relative importance or order relationships thereof.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Please refer to fig. 1, which is a schematic diagram of a bidirectional gate driving array circuit according to an embodiment of the invention. As shown, the bidirectional gate driving array circuit 10 includes a gate driving circuit 11, a forward scan redundancy circuit 12, a reverse scan redundancy circuit 13, and a selection circuit 14. The gate driving circuit 11 includes n driving shift registers (G1-Gn) respectively coupled to the scan lines of the pixels for controlling the on/off of the pixels and writing data into the pixels. When the forward scan PS is performed, the first shift register G1 of the gate driving circuit 11 receives the start signal ST of the forward scan signal, outputs the first gate driving signal G (1), and drives the gates of the transistors in the pixels. The second shift register G2 receives the gate driving signal G (1) from the first shift register G1 as its enable signal ST (1), and outputs the second gate driving signal G (2) until the last shift register Gn receives the gate driving signal G (n-1) from the previous shift register Gn-1, and outputs the last gate driving signal G (n) as an enable signal. In fig. 1, the output arrow of each driving shift register is a forward scan PS as an example, and a signal is output from the first shift register G1 in the direction of the last shift register Gn, whereas a reverse scan RS is performed from the last shift register Gn in the direction of the first shift register G1. In the reverse scan RS, the last shift register Gn receives the start signal ST and outputs the gate driving signal G (1) as the start signal ST (1) of the previous stage until the first shift register G1 outputs the gate driving signal G (n), thereby completing the reverse scan RS.
In order to increase the reliability of the gate driving circuit 11, a positive scan redundancy circuit 12 is disposed after the gate driving circuit 11, and includes m positive scan redundancy shift registers (DP 1-DPm), as shown in the figure, the first positive scan redundancy shift register DP1 of the positive scan redundancy circuit 12 is coupled to the last shift register Gn. These positive scan redundant shift registers are not used to drive the pixels, but instead provide the next stage shift register signals. Since the bi-directional gate driving array circuit has the function of reverse scan RS, a reverse scan redundancy circuit 13 is also required before the gate driving circuit 11, the reverse scan redundancy circuit 13 includes m reverse scan redundancy shift registers (DR 1-DRm), and the last reverse scan redundancy shift register DRm of the reverse scan redundancy circuit 13 is coupled to the first shift register G1. In this embodiment, the corresponding number of shift registers are provided in the forward scan redundancy circuit 12 and the reverse scan redundancy circuit 13, and in this embodiment, the number of shift registers provided in the gate driving circuit 11, the forward scan redundancy circuit 12 and the reverse scan redundancy circuit 13 is a multiple of the number of phases (Phase) in the bidirectional gate driving array circuit. For example, if the number of clock signals for the bi-directional gate driver array circuit is L, the results of n/L and m/L are constant.
Based on the above circuit design, when performing the forward scan PS, the original start signal ST will pass through the inverse scan redundancy circuit 13 first, and the requirement of line buffer (line buffer) is increased, where the line buffer is the number of clock cycles (clock) from the start of the start signal ST to the time before the first data is written. When the reverse scan redundancy circuit 13 increases the forward scan PS, the start signal ST starts to line buffering required for the first shift register G1 to output the first gate driving signal G (1). Similarly, during the reverse scan RS, the forward scan redundancy circuit 12 adds the line buffer required from the start of the start signal ST to the output of the first gate driving signal G (1) from the last shift register Gn. Generally, the Integrated Circuit (IC) has a limited number of line buffers to support, with fewer than 4 selectivity, and if the bi-directional gate driver array circuit 10 requires more than 4 line buffers, which is specially customized, the manufacturing cost of the entire gate driver array will be significantly increased.
In order to save the problem of adding line buffers caused by the front-end redundancy circuit, the present embodiment provides a selection circuit 14, which is respectively coupled to the gate driving circuit 11, the forward scan redundancy circuit 12 and the reverse scan redundancy circuit 13, and when performing the forward scan PS, the selection circuit 14 turns off the reverse scan redundancy circuit 13 according to the received forward scan signal U2D, so that the start signal ST avoids the reverse scan redundancy circuit 13, thereby reducing the number of line buffers used. In contrast, when the reverse scan RS is performed, the selection circuit 14 turns off the forward scan redundancy circuit 12 according to the received reverse scan signal D2U, so that the start signal ST avoids the forward scan redundancy circuit 12, and the number of line buffers used is also reduced.
Please refer to fig. 2, which is a schematic diagram of a bidirectional gate driving array circuit according to another embodiment of the present invention. As shown, the bidirectional gate driving array circuit 20 includes a gate driving circuit 21, a forward scan redundancy circuit 22 and a reverse scan redundancy circuit 23, which are 1-by-3 structures. The gate driving circuit 21 includes n driving shift registers (G1-Gn), the forward scan redundancy circuit 22 includes 4 shift registers (the first forward scan redundancy shift register D5-the fourth forward scan redundancy shift register D8), the reverse scan redundancy circuit 23 includes 4 shift registers (the first reverse scan redundancy shift register D1-the fourth reverse scan redundancy shift register D4), the selection circuit includes a first selection circuit S1, a second selection circuit S2, a third selection circuit S3 and a fourth selection circuit S4, the first selection circuit S1 is coupled to the first reverse scan redundancy shift register D1 of the reverse scan redundancy circuit 23, the second selection circuit S2 is coupled to the first shift register G1 of the gate driving circuit 21, the third selection circuit S3 is coupled to the last shift register of the gate driving circuit 21, the fourth selection circuit S4 is coupled to the fourth forward scan redundancy shift register G D8. of the forward scan redundancy circuit 22, the first selection circuit S D8. and the third selection circuit S3 are connected to the reverse scan redundancy circuit S3 The second selection circuit S2 and the fourth selection circuit S4 are connected to the normal scan signal line U/D, and when the normal scan signal line U/D is at a high potential (U2D is equal to 1) and the reverse scan signal line D/U is at a low potential (D2U is equal to 0), the bidirectional gate driver array circuit 20 performs the forward scan PS to scan from the first shift register G1 toward the last shift register Gn; when the normal scan signal line U/D is at a low potential (U2D is equal to 0) and the reverse scan signal line D/U is at a high potential (D2U is equal to 1), the bidirectional gate driver array circuit 20 performs the reverse scan RS, and scans from the last shift register Gn to the first shift register G1.
When the forward scan signal line U/D is at a high voltage (U2D is equal to 1) and the reverse scan signal line D/U is at a low voltage (D2U is equal to 0) during the forward scan PS, the first selection circuit S1 and the third selection circuit S3 are turned off to disconnect the first reverse scan redundant shift register D1 and the last shift register Gn, and the second selection circuit S2 and the fourth selection circuit S4 are turned on to connect the first shift register G1 and the fourth forward scan redundant shift register D8 for the forward scan PS. Conversely, when the reverse scan RS is performed, the normal scan signal line U/D is at a low potential (U2D is 0) and the reverse scan signal line D/U is at a high potential (D2U is 1), the second selection circuit S2 and the fourth selection circuit S4 are turned off to disconnect the first shift register G1 and the fourth normal scan redundant shift register D4, and the first selection circuit S1 and the third selection circuit S3 are turned on to turn on the first reverse scan redundant shift register D1 and the last shift register Gn to perform the reverse scan RS.
Please refer to fig. 3, which is a waveform diagram of a bidirectional gate driving array circuit according to another embodiment of the present invention. Continuing with the embodiment of FIG. 2, when the forward scan signal line U/D is high and the reverse scan signal line D/U is low during the forward scan PS, the first selection circuit S1 is turned off to disconnect the first reverse scan redundant shift register D1, so that the first reverse scan redundant shift register D1 is controlled to output no signal. At this time, the second selection circuit S2 is turned on so that the first shift register G1 can receive the first start signal ST1 of the start signal ST circuit and further output the same driving signal waveform according to the clock signal HC1, and since the first start signal ST1 does not need to pass through the first anti-scan redundant shift register D1 to the fourth anti-scan redundant shift register D4, the required line buffer can be saved from the original 7 lines to 3 lines, thereby effectively reducing the number of line buffers. At this time, the third selection circuit S3 is similarly turned off to disconnect the last shift register Gn, and similarly, no signal is output until the previous stage shift register G is receivedn-2Outputs the last gate driving signal g (n). The fourth selection circuit S4 is turned on to control the fourth positive scan redundant shift register D8, and the gate driving circuit of the last stage is reset. In the present embodiment, the odd shift registers (G1, G3 …) are controlled by the first enable signal ST1, and the even shift registers (G2, G4 …) are controlled by the second enable signal ST 2. Since the bidirectional gate driver of the present embodimentThe dynamic array circuit includes four clock signals, the number of the phases of the four clock signals is 4, the number of the shift registers included in the gate driving circuit is a multiple of 4 according to the previous embodiment, and the number of the positive scan redundant shift registers and the negative scan redundant shift registers must be a multiple of 4.
Please refer to fig. 4, which is a schematic diagram of a bidirectional gate driving array circuit according to another embodiment of the present invention. As shown, the bidirectional gate driving array circuit 30 includes a gate driving circuit 31, a forward scan redundancy circuit 32, and a reverse scan redundancy circuit 33. In the embodiment, the first switch of the selection circuit includes a first N-type transistor TN1, the second switch includes a second N-type transistor TN2, the third switch includes a third N-type transistor TN3, and the fourth switch includes a fourth N-type transistor TN 4934, one end of the first N-type transistor TN1 is connected to the start signal ST circuit, the other end of the first N-type transistor TN1 is connected to the first reverse scan shift register TN1, and the control end of the first N-type transistor TN/u is connected to the reverse scan signal line D/u 2 One terminal of the first shift register is connected to the start signal ST circuit, the other terminal is connected to the first shift register G1, and the control terminal is connected to the normal scan signal line U/D. The third N-type transistor TN3 has one terminal connected to the start signal ST circuit, the other terminal connected to the last shift register Gn, and a control terminal connected to the inverse scan signal line D/U. One end of the fourth N-type transistor TN4 is connected to the start signal ST circuit, the other end is connected to the fourth positive scan redundant shift register D8, and the control end is connected to the positive scan signal line U/D.
During forward scanning of the PS, the forward scanning signal line U/D is at a high voltage level (U2D equals 1) and the reverse scanning signal line D/U is at a low voltage level (D2U equals 0), the first N-type transistor TN1 and the third N-type transistor TN3 are turned off to disconnect the first reverse scanning redundant shift register D1 and the last shift register Gn, and the second N-type transistor TN2 and the fourth N-type transistor TN4 are turned on to turn on the first shift register G1 and the fourth forward scanning redundant shift register D8 for forward scanning of the PS. In contrast, during the reverse scan RS, the forward scan signal line U/D is at a low voltage (U2D ═ 0) and the reverse scan signal line D/U is at a high voltage (D2U ═ 1), the second N-type transistor TN2 and the fourth N-type transistor TN4 are turned off to disconnect the first shift register G1 and the fourth forward scan redundant shift register D4, and the first N-type transistor TN1 and the third N-type transistor TN3 are turned on to turn on the first reverse scan redundant shift register D1 and the last shift register Gn to perform the reverse scan RS.
Fig. 5 is a schematic diagram of a bidirectional gate driving array circuit according to still another embodiment of the invention. As shown, the bidirectional gate driving array circuit 40 includes a gate driving circuit 41, a forward scan redundancy circuit 42, and a reverse scan redundancy circuit 43. In the embodiment, the first switch of the selection circuit includes a first P-type transistor TP1, the second switch includes a first N-type transistor TN1, the third switch includes a second N-type transistor TN2, and the fourth switch includes a second P-type transistor TP2, one end of the first P-type transistor 1 is connected to the start signal ST circuit, the other end of the first P-type transistor TN2 is connected to the first reverse scan redundant shift register 1, and the control end of the first P-type transistor TN is connected to the first N-type transistor TN1 One terminal of the first shift register is connected to the start signal ST circuit, the other terminal is connected to the first shift register G1, and the control terminal is connected to the normal scan signal line U/D. The second N-type transistor TN2 has one terminal connected to the start signal ST circuit, the other terminal connected to the last shift register Gn, and a control terminal connected to the reverse scan signal line D/U. One end of the second P-type transistor TP2 is connected to the start signal ST circuit, the other end is connected to the fourth forward scan redundant shift register D8, and the control end is connected to the reverse scan signal line D/U.
When the forward scan signal line U/D is at a high potential (U2D is 1) and the reverse scan signal line D/U is at a low potential (D2U is 0) in the forward scan PS, the first P-type transistor TP1 and the second N-type transistor TN2 are disconnected from the first reverse scan redundant shift register D1 and the last shift register Gn, and the first N-type transistor TN1 and the second P-type transistor TP2 turn on the first shift register G1 and the fourth forward scan redundant shift register D8 to perform the forward scan PS. In contrast, when the reverse scan RS is performed, the forward scan signal line U/D is at a low potential (U2D is 0) and the reverse scan signal line D/U is at a high potential (D2U is 1), the first N-type transistor TN1 and the second P-type transistor TP2 are disconnected from the first shift register G1 and the fourth forward scan redundant shift register D4, and the first P-type transistor TP1 and the second N-type transistor TN2 turn on the first reverse scan redundant shift register D1 and the last shift register Gn to perform the reverse scan RS.
Please refer to fig. 6, which is a waveform diagram of a triple bi-directional gate driving array circuit according to an embodiment of the present invention. As shown in fig. 4 or fig. 5, when the bidirectional gate driver array circuit of the present embodiment is a one-to-three type, the waveform diagram shows that when the selection circuit is not provided, the clock signals (CK 1-CK 4) are sequentially generated after the start signal VST is sent out in the first clock cycle H1, however, due to the design of the bidirectional circuit, the first shift register G1 is also preceded by the anti-scan redundant shift registers (D1-D4), the start signal VST needs to have 4 more line buffers to provide the clock signals of the anti-scan redundant shift registers (D1-D4), so when the first shift register G1 actually writes the data Da, it is the eighth clock cycle H8, that is, the original bidirectional gate driver array circuit needs 7 line buffers to actually write the pixel data Da. When the selection circuit of the present embodiment is added, since the selection circuit turns off the anti-scan redundancy circuit, the line buffering required by the anti-scan redundancy shift registers (D1-D4) can be reduced, so that the new first shift register G1n can write the data Da in the fourth clock cycle, thereby saving 3 line buffering. The circuit buffering quantity required to be supported by the control chip is effectively reduced, and the overall cost is further reduced.
Please refer to fig. 7, which is a waveform diagram of a one-to-five bidirectional gate driving array circuit according to an embodiment of the invention. As shown in the figure, when the bi-directional gate driver array circuit of the present embodiment is a one-to-five type, the waveform diagram shows that when the selection circuit is not provided, the start signal VST is sent out in the first clock cycle H1, and the clock signals (CK 1-CK 8) thereof are sequentially generated, similar to the previous embodiment, the start signal VST needs to reverse the clock signals of the redundant shift registers (D1-D8), so that when the first shift register G1 actually writes the data Da, the clock cycle H13 is the thirteenth clock cycle H13, that is, the original bi-directional gate driver array circuit needs 12 line buffers to actually write the pixel data Da. When the selection circuit of the present embodiment is added, since the selection circuit turns off the anti-scan redundancy circuit, the line buffer required by the anti-scan redundancy shift registers (D1-D8) can be reduced, so that the new first shift register G1n can write the data Da in the fifth clock cycle H5, and 8 line buffers are saved. The circuit buffering quantity required to be supported by the control chip is effectively reduced, and the overall cost is further reduced.
The foregoing is by way of example only, and not limiting. Any equivalent modifications or variations without departing from the spirit and scope of the present invention should be included in the claims.
Claims (7)
1. A bi-directional gate drive array circuit, comprising:
a gate driving circuit, including a plurality of driving shift registers respectively coupled to a scan line of the plurality of pixels, for receiving a forward scan signal to perform a forward scan from a first shift register toward a last shift register, or receiving a reverse scan signal to perform a reverse scan from the last shift register toward the first shift register;
a positive scan redundancy circuit comprising a plurality of positive scan redundancy shift registers, a first positive scan redundancy shift register of the positive scan redundancy circuit coupled to the last shift register;
a reverse scan redundancy circuit comprising a plurality of reverse scan redundancy shift registers, a last reverse scan redundancy shift register of the reverse scan redundancy circuit coupled to the first shift register; and
and the selection circuit is respectively coupled with the grid drive circuit, the forward scanning redundancy circuit and the reverse scanning redundancy circuit, and the selection circuit closes the reverse scanning redundancy circuit according to the forward scanning signal or closes the forward scanning redundancy circuit according to the reverse scanning signal.
2. The bi-directional gate drive array circuit of claim 1, wherein the selection circuit comprises a first switch, a second switch, a third switch and a fourth switch, the first switch is coupled to a first reverse scan redundancy shift register of the reverse scan redundancy circuit, the second switch is coupled to the first shift register, the third switch is coupled to the last shift register and the fourth switch is coupled to a last forward scan redundancy shift register of the forward scan redundancy circuit;
the forward scan signal turns off the first switch and the third switch to disconnect the first reverse scan redundancy shift register and the last shift register, and turns on the second switch and the fourth switch to connect the first shift register and the last forward scan redundancy shift register for the forward scan, or the reverse scan signal turns off the second switch and the fourth switch to disconnect the first shift register and the last forward scan redundancy shift register, and turns on the first switch and the third switch to connect the first reverse scan redundancy shift register and the last shift register for the reverse scan.
3. The bi-directional gate drive array circuit of claim 2, wherein the first switch comprises a first transistor and a second transistor, the first transistor has one terminal connected to a forward scan signal line, the other terminal connected to the first reverse scan redundant shift register and a control terminal connected to an enable signal circuit, the second transistor has one terminal connected to a reverse scan signal line, the other terminal connected to the first reverse scan redundant shift register and a control terminal connected to the enable signal circuit;
the second switch comprises a third transistor and a fourth transistor, one end of the third transistor is connected with the forward scanning signal line, the other end of the third transistor is connected with the first shift register, the control end of the third transistor is connected with the starting signal circuit, one end of the fourth transistor is connected with the reverse scanning signal line, the other end of the fourth transistor is connected with the first shift register, and the control end of the fourth transistor is connected with the starting signal circuit;
the third switch comprises a fifth transistor and a sixth transistor, wherein one end of the fifth transistor is connected with the normal scanning signal line, the other end of the fifth transistor is connected with the last shift register, the control end of the fifth transistor is connected with the starting signal circuit, one end of the sixth transistor is connected with the reverse scanning signal line, the other end of the sixth transistor is connected with the last shift register, and the control end of the sixth transistor is connected with the starting signal circuit; and
the fourth switch comprises a seventh transistor and an eighth transistor, wherein one end of the seventh transistor is connected with the forward scanning signal line, the other end of the seventh transistor is connected with the last forward scanning redundancy shift register, the control end of the seventh transistor is connected with the starting signal circuit, one end of the eighth transistor is connected with the reverse scanning signal line, the other end of the eighth transistor is connected with the last forward scanning redundancy shift register, and the control end of the eighth transistor is connected with the starting signal circuit.
4. The bi-directional gate drive array circuit of claim 2, wherein the first switch comprises a first N-type transistor having one terminal connected to an enable signal circuit, another terminal connected to the first anti-scan redundant shift register, and a control terminal connected to an anti-scan signal line;
the second switch comprises a second N-type transistor, one end of the second N-type transistor is connected with the starting signal circuit, the other end of the second N-type transistor is connected with the first shift register, and the control end of the second N-type transistor is connected with a positive scanning signal line;
the third switch comprises a third N-type transistor, one end of the third N-type transistor is connected with the starting signal circuit, the other end of the third N-type transistor is connected with the last shift register, and the control end of the third N-type transistor is connected with the reverse scanning signal line; and
the fourth switch comprises a fourth N-type transistor, one end of the fourth N-type transistor is connected with the starting signal circuit, the other end of the fourth N-type transistor is connected with the last positive-scan redundant shift register, and the control end of the fourth N-type transistor is connected with the positive-scan signal line.
5. The bi-directional gate drive array circuit of claim 2, wherein the first switch comprises a first P-type transistor having one end connected to an enable signal circuit, another end connected to the first reverse scan redundant shift register, and a control end connected to a forward scan signal line;
the second switch comprises a first N-type transistor, one end of the first N-type transistor is connected with the starting signal circuit, the other end of the first N-type transistor is connected with the first shift register, and the control end of the first N-type transistor is connected with the positive scanning signal line;
the third switch comprises a second N-type transistor, one end of the second N-type transistor is connected with the starting signal circuit, the other end of the second N-type transistor is connected with the last shift register, and the control end of the second N-type transistor is connected with a reverse scanning signal line; and
the fourth switch comprises a second P-type transistor, one end of the second P-type transistor is connected with the starting signal circuit, the other end of the second P-type transistor is connected with the last positive-scan redundant shift register, and the control end of the second P-type transistor is connected with the reverse-scan signal line.
6. The bi-directional gate driver array circuit of claim 1, wherein the clock signal of the bi-directional gate driver array circuit comprises a number of phases, the number of the plurality of driving shift registers is a multiple of the number of phases, and the number of the plurality of forward scan redundant shift registers and the number of the plurality of reverse scan redundant shift registers are both a multiple of the number of phases.
7. The bi-directional gate drive array circuit of claim 1, wherein the number of the plurality of forward scan redundant shift registers is the same as the number of the plurality of reverse scan redundant shift registers.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108130628A TWI708227B (en) | 2019-08-27 | 2019-08-27 | Bidirectional gate on array circuit |
| TW108130628 | 2019-08-27 |
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| CN111145679A true CN111145679A (en) | 2020-05-12 |
| CN111145679B CN111145679B (en) | 2022-10-18 |
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| CN202010111190.XA Active CN111145679B (en) | 2019-08-27 | 2020-02-24 | Bidirectional grid driving array circuit |
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| TW (1) | TWI708227B (en) |
Cited By (1)
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| TWI756969B (en) * | 2020-12-07 | 2022-03-01 | 友達光電股份有限公司 | Shift register circuit |
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| TWI818667B (en) * | 2022-08-10 | 2023-10-11 | 友達光電股份有限公司 | Display panel |
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| Publication number | Publication date |
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| TW202109482A (en) | 2021-03-01 |
| CN111145679B (en) | 2022-10-18 |
| TWI708227B (en) | 2020-10-21 |
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