CN111140483A - Micro fluid delivery module - Google Patents
Micro fluid delivery module Download PDFInfo
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- CN111140483A CN111140483A CN201811312925.4A CN201811312925A CN111140483A CN 111140483 A CN111140483 A CN 111140483A CN 201811312925 A CN201811312925 A CN 201811312925A CN 111140483 A CN111140483 A CN 111140483A
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
- F04B49/00—Control, e.g. of pump delivery, or pump pressure of, or safety measures for, machines, pumps, or pumping installations, not otherwise provided for, or of interest apart from, groups F04B1/00 - F04B47/00
- F04B49/06—Control using electricity
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Abstract
A microfluidic transport module comprising: a microprocessor for outputting a clock signal, a latch signal and a data signal; the special application integrated circuit is electrically connected with the microprocessor and used for receiving a clock signal, a latch signal and a data signal, and comprises a plurality of control circuits, wherein each control circuit comprises: the shift register is electrically connected with the microprocessor to receive the clock pulse signal and the data signal; the latch circuit is electrically connected with the microprocessor and the shift register so as to receive a latch signal and a data signal; the circuit is electrically connected with the latch circuit to receive the data signal output by the latch circuit; an inverter, electrical connections and circuitry; an oscillation circuit outputting an oscillation signal; and the micro-electromechanical pumps are respectively and correspondingly electrically connected with the control circuits.
Description
Technical Field
The present invention relates to a micro fluid delivery module, and more particularly, to a module for precisely controlling a plurality of micro electromechanical pumps by using a control circuit to assist a microprocessor.
Background
With the increasing development of technology, the applications of fluid delivery devices are becoming more diversified, such as industrial applications, biomedical applications, medical care, electronic heat dissipation, and so on, and even recently, the image is seen in wearable devices of hot doors, and it is seen that the conventional pump tends to be miniaturized, please refer to fig. 1, which is a schematic diagram of the structure of a mems pump module shown in fig. 1, although the known mems pump module can miniaturize the volume of a mems pump 3 ' to the micrometer level, the micrometer level mems pump 3 ' will limit the fluid transmission amount due to the undersized volume, so that a plurality of mems pumps 3 ' are needed to be used in combination, and at present, the current situation is individually controlled by a high-level microprocessor 1 ', but the high-level microprocessor 1 ' is high in cost, and each mems pump 3 ' must be connected by two pins, which increases the cost of the high-level microprocessor 1 ', therefore, how to reduce the cost of the driving end of the micro-electromechanical pump module is a difficulty to be overcome at present.
Disclosure of Invention
The main objective of the present invention is to provide a micro fluid delivery module, which is used for assisting a microprocessor to control a micro electromechanical pump at a micron level by using an application specific integrated circuit, so as to effectively control a plurality of micro electromechanical pumps.
To achieve the above object, a micro fluid transfer module according to a broader aspect of the present invention comprises: the microprocessor is arranged on the first printed circuit board and used for outputting a clock signal, a latch signal and a data signal; a second printed circuit board; the first flexible flat cable is arranged between the first printed circuit board and the second printed circuit board, and the second printed circuit board is electrically connected with the first printed circuit board through the first flexible flat cable; a special application integrated circuit disposed on the second printed circuit board and electrically connected to the microprocessor through the first flexible flat cable for receiving the clock signal, the latch signal and the data signal, the special application integrated circuit including a plurality of control circuits, each control circuit including: a shift register electrically connected to the microprocessor for receiving the clock signal and the data signal; a latch circuit electrically connected to the microprocessor and the shift register for receiving the latch signal and the data signal output by the shift register; the latch circuit is electrically connected with the circuit and used for receiving the data signal output by the latch circuit; and a reverser electrically connected to the sum circuit; an oscillation circuit electrically connected to the AND circuit for outputting an oscillation signal; a third printed circuit board; the second flexible flat cable is arranged between the second printed circuit board and the third printed circuit board, and the third printed circuit board is electrically connected with the second printed circuit board through the second flexible flat cable; and a plurality of MEMS pumps arranged on the third PCB and electrically connected with the control circuits via the second flexible flat cable.
Drawings
Fig. 1 is a schematic diagram of a micro electromechanical pump of a known micro fluid delivery module.
Fig. 2A is a schematic structural diagram of the micro fluid delivery module according to the present disclosure.
Fig. 2B is a schematic circuit structure diagram of the micro fluid delivery module according to the present disclosure.
FIG. 3A is a diagram of a shift register and a latch circuit of the first set of control circuits of FIG. 2.
FIG. 3B is a schematic circuit diagram of the shift transmission gate of FIG. 3A.
FIG. 3C is a circuit diagram of the latch pass gate of FIG. 3A.
Fig. 4A is a circuit diagram of the oscillator circuit of fig. 2.
FIG. 4B is a waveform diagram of the oscillator circuit of FIG. 4A. Fig. 5 is a circuit schematic of the sum circuit of fig. 2.
FIG. 6 is a diagram of a shift register and latch circuit of the second set of control circuits of FIG. 2.
Description of the reference numerals
100: micro fluid delivery module
1A: first printed circuit board
1B: second printed circuit board
1C: the first flexible flat cable
1D: third printed circuit board
1E: the second flexible flat cable
1. 1': microprocessor
2: application specific integrated circuit
20: control circuit
20A: first group of control circuits
20B: second group of control circuits
21: shift register
21 a: clock signal input terminal
21 b: first data receiving terminal
21 c: a first data output terminal
21 d: shift transmission gate
21 e: shift reverser
211: p-type metal-oxide-semiconductor field-correcting transistor
211 a: p-type gate input terminal
211 b: a first signal input terminal
211 c: a first signal output terminal
212: n-type metal-oxide-semiconductor field-correcting transistor
212 a: n-type gate input terminal
212b, and (3 b): second signal input terminal
212 c: second signal output terminal
213: input terminal of transmission gate
214: output end of transmission gate
22: latch circuit
22 a: latch signal input terminal
22 b: second data receiving terminal
22 c: a second data output terminal
22 d: latch transmission gate
22 e: latch reverser
23: oscillating circuit
231: first P-type metal oxide semiconductor field correcting transistor
232: second P-type metal oxide semiconductor field correcting transistor
233: third P-type metal oxide semiconductor field correcting transistor
234: a first N-type metal oxide semiconductor field-effect transistor
235: second N-type metal oxide semiconductor field correcting transistor
236: third N-type metal oxide semiconductor field correcting transistor
237: storage capacitor
238: first oscillation inverter
239: second oscillating inverter
24: and circuit
24 a: third data receiving terminal
24 b: oscillation signal receiving terminal
24 c: first control signal output terminal
24 d: second control signal output terminal
241: NAND gate
242: and circuit inverter
24 a: third data receiving terminal
24 b: oscillation signal receiving terminal
24 c: first control signal output terminal
24 d: second control signal output terminal
25: reverser
25a, 238a, 239 a: input terminal
25b, 238b, 239 b: output end
3. 3': MEMS pump
31: a first electrode
32: second electrode
Detailed Description
Exemplary embodiments that embody features and advantages of this disclosure are described in detail below in the detailed description. It will be understood that the present disclosure is capable of various modifications without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.
Referring to fig. 2A and 2B, the micro fluid delivery module 100 of the present disclosure includes: a first printed circuit board 1A, a microprocessor 1, a second printed circuit board 1B, a first soft flat cable 1C, a special application integrated circuit 2, a third printed circuit board 1D, a second soft flat cable 1E and a plurality of MEMS pumps 3, wherein the microprocessor 1 is arranged on the first printed circuit board 1A for outputting a clock signal, a latch signal and a data signal, the first soft flat cable 1C is arranged between the first printed circuit board 1A and the second printed circuit board 1B, so that the second printed circuit board 1B is electrically connected to the first printed circuit board 1A through the first soft flat cable 1C, the special application integrated circuit 2 is arranged on the second printed circuit board 1B and is electrically connected to the microprocessor 1 through the first soft flat cable 1C for receiving the clock signal, the latch signal and the data signal, the special application integrated circuit 2 has a plurality of control circuits 20, a plurality of micro-electromechanical pumps 3 are arranged on the third printed circuit board 1D, a second flexible flat cable 1E is arranged between the second printed circuit board 1B and the third printed circuit board 1D, and the third printed circuit board 1D is electrically connected to the second printed circuit board 1B through the second flexible flat cable 1E, so that each control circuit 20 on the second printed circuit board 1B is electrically connected to one of the plurality of micro-electromechanical pumps 3 on the third printed circuit board 1D through the second flexible flat cable 1E respectively and correspondingly, and is not repeated, so as to control the plurality of micro-electromechanical pumps 3 respectively; wherein each micro-electromechanical pump 3 has a first electrode 31 and a second electrode 32.
The control circuits 20 each have a shift register 21, a latch circuit 22, an and circuit 24 and an inverter 25; the shift register 21 includes at least a clock signal input terminal 21a, a first data receiving terminal 21b and a first data output terminal 21c, the clock signal input terminal 21a is electrically connected to the microprocessor 1 for receiving the clock signal outputted from the microprocessor 1, and the first data receiving terminal 21b is also electrically connected to the microprocessor 1 for receiving the data signal; the latch circuit 22 has at least one latch signal input terminal 22a, a second data receiving terminal 22b and a second data output terminal 22c, the latch signal input terminal 22a is electrically connected to the microprocessor 1 for receiving the latch signal output by the microprocessor 1, the second data receiving terminal 22b is electrically connected to the first data output terminal 21c of the shift register 21 for receiving the data signal output by the shift register 21; the circuit 24 includes a third data receiving terminal 24a, a first control signal output terminal 24c and a second control signal output terminal 24d, the third data receiving terminal 24a is electrically connected to the second data output terminal 22c of the latch circuit 22 to receive the data signal output by the latch circuit 22, and the second control signal output terminal 24d is electrically connected to the corresponding first electrode 31 of the mems pump 3; the inverter 25 has an input terminal 25a and an output terminal 25b, the input terminal 25a is electrically connected to the first control signal output terminal 24c of the circuit 24, and the output terminal 25b is electrically connected to the second electrode 32 of the mems pump 3.
The micro fluid delivery module 100 further includes an oscillator circuit 23, and the circuit 24 has an oscillator signal receiving terminal 24B electrically connected to the oscillator circuit 23 to receive an oscillator signal output by the oscillator circuit 23, and in addition, the oscillator circuit 23 may be disposed on the second printed circuit board 1B.
The aforementioned control circuits 20 can be divided into a first group of control circuits 20A and a second group of control circuits 20B, please refer to fig. 3A, fig. 3A is a circuit structure diagram of the shift register 21 and the latch circuit 22, the shift register 21 of the first group of control circuits 20A includes a plurality of shift transmission gates 21d and a plurality of shift inverters 21e, in this embodiment, the number of the shift transmission gates 21d and the number of the shift inverters 21e are both 4, as shown in fig. 3B, fig. 3B is a detailed structure diagram of the shift transmission gates 21d, each shift transmission gate 21d includes a P-type MOSFET 211, an N-type MOSFET 212, a transmission gate input 213 and a transmission gate output 214, two MOSFETs are used as switches, and the P-type MOSFET 211 has a P-type gate input 211a, A first signal input terminal 211b and a first signal output terminal 211c, the N-type mosfet 212 has an N-type gate input terminal 212a, a second signal input terminal 212b and a second signal output terminal 212c, the first signal input terminal 211b of the P-type mosfet 211 and the second signal input terminal 212b of the N-type mosfet 212 are electrically connected as the transmission gate input terminal 213, the first signal output terminal 211c and the second signal output terminal 212c are electrically connected as the transmission gate output terminal 214, and the P-type gate input terminal 211a of the P-type mosfet 211 and the N-type gate input terminal 212a of the N-type mosfet 212 are respectively electrically connected to the clock signal input terminal 21a of the shift register 21 for receiving the clock signal transmitted from the microprocessor 1; referring to fig. 3A, the 4 shift transmission gates 21d in the shift register 21 are connected in series, the transmission gate input terminal 213 of the first shift transmission gate 21d is electrically connected to the first data receiving terminal 21b of the shift register 21, the transmission gate output terminal 214 is electrically connected to the transmission gate input terminal 213 of the second shift transmission gate 21d, the transmission gate output terminal 214 of the second shift transmission gate 21d is electrically connected to the transmission gate input terminal 213 of the last shift transmission gate 21d, the transmission gate output terminal 214 of the last shift transmission gate 21d is electrically connected to the data output terminal 21c of the shift register 21, and in addition, the 4 shift inverters 21e are connected in series two by two and then connected in parallel to the second shift transmission gate 21d and the last shift transmission gate 21d respectively.
As mentioned above, the clock signals of the P-type gate input terminal 211a and the N-type gate input terminal 212a of the same shift transmission gate 21d are inverted signals, as shown in fig. 3A, when the P-type gate input terminal 211a of the first shift transmission gate 21d receives an inverted clock signal, the N-type gate input terminal 212a thereof receives a clock signal, the P-type gate input terminal 211a of the third shift transmission gate 21d receives an inverted clock signal opposite to the first P-type gate input terminal 211a, the N-type gate input terminal 212a of the third shift transmission gate 21d receives an inverted clock signal, the P-type gate input terminal 212a of the next (second) shift transmission gate 21d receives a clock signal, the N-type gate input terminal 212a thereof receives an inverted clock signal, the P-type gate input terminal 211a of the last (fourth) shift transmission gate 21d receives an inverted clock signal opposite to the P-type gate input terminal 211a of the second shift transmission gate 21d, the N-type gate input 212a receives a clock signal, and so on.
Referring to fig. 3A, the latch circuit 22 has two latch transmission gates 22d and two latch inverters 22e, as shown in fig. 3C, the two latch transmission gates 22d respectively include a P-type MOSFET 211, an N-type MOSFET 212, a transmission gate input terminal 213 and a transmission gate output terminal 214, the two Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used as switches, and the structure of the latch transmission gate 22d and the shift transmission gate 21d are transmission gates having the same structure, and therefore are not described in detail, wherein the P-type gate input terminal 211a of the P-type MOSFET of the latch transmission gate 22d and the N-type gate input terminal 212a of the N-type MOSFET are electrically connected to the latch signal input terminal 22a of the latch circuit 22 respectively, so as to receive a latch signal sent by the microprocessor 1; two latch transmission gates 22d are connected in series, the transmission gate input terminal 213 of the latch transmission gate 22d located at the front end is electrically connected to the second data receiving terminal 22b of the latch circuit 22 to further electrically connect to the first data output terminal 21c of the shift register 21, the transmission gate output terminal 214 is electrically connected to the second data input terminal 213 of the latch transmission gate 22d located at the rear end, the second data output terminal 214 of the latch transmission gate 22d located at the rear end is electrically connected to the second data output terminal 22c of the latch circuit 22, and 2 latch inverters 22e are connected in series and then connected in parallel to the latch transmission gate 22d located at the rear end; in addition, the latch signals received by the P-type gate input terminal 211a and the N-type gate input terminal 212a are inverse signals, the latch signals received by the P-type gate input terminal 211a of the front latch transmission gate 22d and the P-type gate input terminal 211a of the rear latch transmission gate 22d are also inverse signals, as shown in fig. 3A, when the P-type gate input terminal 211a of the front latch transmission gate 22d receives the latch signal, the N-type gate input terminal 212a thereof receives the inverse latch signal, the P-type gate input terminal 211a of the rear latch transmission gate 22d receives the inverse latch signal opposite to the P-type gate input terminal 211a of the front latch transmission gate 22d, and the N-type gate input terminal 212a thereof receives the latch signal.
Referring to fig. 4A, the oscillator circuit 23 includes a first P-type mosfet 231, a second P-type mosfet 232, a third P-type mosfet 233, a first N-type mosfet 234, a second N-type mosfet 235, a third N-type mosfet 236, a storage capacitor 237, a first oscillator 238 and a second oscillator 239, wherein the base of the first P-type mosfet 231 is electrically connected to the source, the base and the source of the second P-type mosfet 232, the base of the third P-type mosfet 233 and the constant voltage 3.3v, the gate of the first P-type mosfet 231 is electrically connected to the drain of the second P-type mosfet 232 and the drain of the first N-type mosfet 234, the base of the first NMOS transistor 234 is electrically connected to its source and ground, the gate is electrically connected to the gate of the second NMOS transistor 235 and the input voltage Vin, the source of the second NMOS transistor 235 is electrically connected to its base, the base of the third NMOS transistor 236 is electrically connected to ground, the drain of the third NMOS transistor 236 is electrically connected to the drain of the third PMOS transistor 233, one end of the storage capacitor 237 and the input 238a of the first oscillator-inverter 238, the output 238b of the first oscillator-inverter 238 is electrically connected to the input 239a of the second oscillator-inverter 239, finally, the output 239b of the second oscillating inverter 239 is connected to the oscillating signal receiving end 24b of the and circuit 24 and feeds back the gates of the third pmos 233 and the third nmos 236.
Referring to fig. 4B, fig. 4B is a waveform diagram of the oscillator circuit of fig. 4A, where the input voltage Vin ranges from 1V to 3.3V, when the input voltage Vin is 3.3V, the first pmos 231, the second pmos 232, the third pmos 233, the first nmos 234, and the second nmos 235 are all turned on, the third nmos 236 is turned off, the storage capacitor 237 is charged, when the storage capacitor 237 is fully charged, the storage capacitor outputs a positive signal to the input end 238a of the first oscillator inverter 238, the positive signal passes through the first oscillator inverter 238 and outputs a negative signal to the input end 239a of the second inverter 239, the negative signal passes through the second oscillator inverter 239, the oscillator circuit 23 outputs a positive signal, and the positive signal returns to the third pmos 233, The gate of the third nmos 236, at this time, the third pmos 233 will be turned off, the storage capacitor 237 will start to discharge, after the storage capacitor 237 discharges, the negative signal will be output to the input end 238a of the first oscillation inverter 238, the negative signal will be inverted by the first oscillation inverter 238 into the positive signal and output to the input end 239a of the second oscillation inverter 239, the positive signal will be inverted by the second oscillation inverter 239 into the negative signal and will be returned to the gates of the third pmos 233 and the third nmos 236, the third nmos 236 will be turned off, the first pmos 231, the second pmos 232 and the third pmos 233 will all be turned on, the storage capacitor 237 will start to charge, after charging, the positive signal will be output, continuing the above steps, the oscillator circuit 23 can continuously output opposite positive and negative signals, and the junction T1 where the storage capacitor 237 and the first oscillation inverter 238 are connected generates an oscillation signal of a nearly triangular wave, and the control signal of the nearly triangular wave is converted into a nearly square wave oscillation signal after passing through the first oscillation inverter 238, so that the output end 238b of the first oscillation inverter 238 generates a nearly square wave oscillation signal (junction T2), and then the second oscillation inverter 239 is used to adjust the nearly square wave control signal into a square wave oscillation signal, and finally the output end 239b of the second oscillation inverter 239 outputs an oscillation signal with a square wave waveform; in addition, the first oscillation inverter 238 and the second oscillation inverter 239 may also be replaced by a schmitt circuit, which is not limited thereto.
Referring to fig. 5, the and circuit 24 has a nand gate 241 and a and circuit inverter 242, two input terminals of the nand gate 241 are respectively connected to the third data receiving terminal 24a and the oscillation signal receiving terminal 24b, an output terminal thereof is electrically connected to an input terminal of the and circuit inverter 242, and an output terminal of the and circuit inverter 242 is electrically connected to the first control signal output terminal 24c and the second control signal output terminal 24 d.
As shown in fig. 2B, the and circuit 24 outputs a control signal from the first control signal output terminal 24c and the second control signal output terminal 24d according to the oscillation signal and the data signal, and receives the control signal from the first electrode 31 of the mems pump 3, and receives the inverted control signal from the inverter 25 from the second electrode 32, and the inverted control signals are received by the first electrode 31 and the second electrode 32, so that the piezoelectric element (not shown) in the mems pump 3 can receive the fluid transmission through the piezoelectric effect.
As shown in fig. 2B, the first group of control circuits 20A has a plurality of control circuits 20, a first data receiving terminal 21a of the first control circuit 20, which is a shift register 21, of the first group of control circuits 20A is electrically connected to the microprocessor 1 for receiving data signals, a first data output terminal 21c of the first control circuit 20 is electrically connected to a first data receiving terminal 21B of the shift register 21 of the next control circuit 20 in addition to the latch circuit 22 of the same control circuit 20, and the following control circuits 20 also transmit data signals downward.
Referring to fig. 3A and fig. 6, fig. 6 is a circuit diagram of the shift register 21 and the latch circuit 22 of the second set of control circuits 20B. As shown, the second set of control circuits 20B of the control circuit 20 has the same structure as the first set of control circuits 20A, and the difference is that the clock signals inputted thereto are opposite.
In summary, the present disclosure provides a micro fluid delivery module, in which a microprocessor uses a plurality of control circuits to control a plurality of micro electromechanical pumps respectively, so as to reduce the burden of the microprocessor, and easily and precisely control each micro electromechanical pump without using a high-cost high-level processor with a plurality of pins, and solve the problems of the prior art with great industrial utility value.
Various modifications may be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims.
Claims (11)
1. A microfluidic transport module, comprising:
a first printed circuit board;
a microprocessor, arranged on the first printed circuit board, for outputting a clock signal, a latch signal and a data signal;
a second printed circuit board;
a first flexible flat cable arranged between the first printed circuit board and the second printed circuit board, the second printed circuit board being electrically connected to the first printed circuit board via the first flexible flat cable;
a special application integrated circuit disposed on the second printed circuit board and electrically connected to the microprocessor through the first flexible flat cable for receiving the clock signal, the latch signal and the data signal, the special application integrated circuit including a plurality of control circuits, each of the control circuits including:
a shift register electrically connected to the microprocessor for receiving the clock signal and the data signal;
a latch circuit electrically connected to the microprocessor and the shift register for receiving the latch signal and the data signal output by the shift register;
the latch circuit is electrically connected with the circuit and used for receiving the data signal output by the latch circuit; and
an inverter electrically connected to the sum circuit;
an oscillating circuit electrically connected to the AND circuit for outputting an oscillating signal to the AND circuit;
a third printed circuit board;
the second flexible flat cable is arranged between the second printed circuit board and the third printed circuit board, and the third printed circuit board is electrically connected with the second printed circuit board through the second flexible flat cable; and
and the MEMS pumps are arranged on the third printed circuit board and are respectively and correspondingly electrically connected with the control circuits through the second flexible flat cables.
2. The micro fluid delivery module of claim 1, wherein the shift register comprises at least a clock signal input electrically connected to the microprocessor for receiving the clock signal, a first data receiving terminal electrically connected to the microprocessor for receiving the data signal, and a first data output terminal.
3. The micro fluid delivery module of claim 2, wherein the latch circuit comprises at least one latch signal input electrically connected to the microprocessor for receiving the latch signal, a second data receiver electrically connected to the first data output, and a second data output.
4. The micro fluid delivery module of claim 3, wherein the AND circuit comprises a third data receiver electrically connected to the second data output, an oscillator signal receiver electrically connected to the oscillator circuit, a first control signal output, and a second control signal output.
5. The microfluidic delivery module of claim 4 wherein said inverter is electrically connected to said first control signal output.
6. The micro fluid delivery module of claim 5, wherein each of the plurality of micro electromechanical pumps has two electrodes electrically connected to the second control signal output terminals of the inverter and the and circuit respectively.
7. The micro fluid delivery module of claim 1, wherein the oscillator circuit is disposed on the second printed circuit board.
8. The micro fluid delivery module of claim 1, wherein the shift register comprises four shift transmission gates and four shift inverters, the four shift transmission gates are connected in series, and the four shift inverters are connected in parallel with two of the four shift transmission gates.
9. The micro fluid delivery module of claim 1, wherein the latch circuit comprises two latch transmission gates connected in series and two latch inverters connected in series and then connected in parallel with one of the two latch transmission gates.
10. The micro fluid delivery module of claim 1, wherein the oscillator circuit comprises a first P-type MOSFET, a second P-type MOSFET, a third P-type MOSFET, a first N-type MOSFET, a second N-type MOSFET, a third N-type MOSFET, a storage capacitor, a first oscillator and a second oscillator, the first P-type MOSFET, the second P-type MOSFET, the third P-type MOSFET, the first N-type MOSFET, the second N-type MOSFET and the third N-type MOSFET each having a base, a gate, a source and a drain, the base of the first P-type MOSFET electrically connecting the source, the drain, the gate of the first P-type MOSFET, the first N-type MOSFET, the second P-type MOSFET and the third N-type MOSFET respectively, The base and the source of the second PMOS transistor, the base of the third PMOS transistor, and a constant voltage, the gate of the first PMOS transistor is electrically connected to the drain thereof, the gate of the second PMOS transistor, the drain of the first NMOS transistor, the base and the source of the first NMOS transistor are grounded, the gate is electrically connected to the gate of the second NMOS transistor and an input voltage, the source of the second NMOS transistor is electrically connected to the base thereof, the base of the third NMOS transistor is grounded, the drain of the third NMOS transistor is electrically connected to the drain of the third PMOS transistor, one end of the storage capacitor, and one end of the first oscillator inverter, an output terminal of the first oscillation inverter is electrically connected to an input terminal of the second oscillation inverter, and finally an output terminal of the second oscillation inverter is electrically connected to the sum circuit 24 and fed back to the gate of the third P-type mos field-correcting transistor and the gate of the third N-type mos field-correcting transistor.
11. The micro fluid transport module of claim 1, wherein the AND circuit comprises a NAND gate and an AND circuit inverter, the NAND gate and the AND circuit inverter being connected in series.
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| CN201811312925.4A CN111140483B (en) | 2018-11-06 | 2018-11-06 | Micro fluid delivery module |
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| CN201811312925.4A CN111140483B (en) | 2018-11-06 | 2018-11-06 | Micro fluid delivery module |
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| CN111140483B CN111140483B (en) | 2022-01-21 |
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| TW574688B (en) * | 2001-11-06 | 2004-02-01 | Atmel Corp | Dual mode high voltage power supply circuit for providing increased speed in programming during testing of low voltage non-volatile memories |
| CN2524265Y (en) * | 2001-12-26 | 2002-12-04 | 中国石化集团齐鲁石油化工公司 | Self-control microliquid delivery device |
| CN1534560A (en) * | 2003-04-02 | 2004-10-06 | 友达光电股份有限公司 | Data driving circuit and its method of driving data |
| US20040201323A1 (en) * | 2003-04-14 | 2004-10-14 | Wong Marvin Glenn | Shear mode liquid metal switch |
| TW200838118A (en) * | 2007-02-01 | 2008-09-16 | Sanyo Electric Co | Integrated circuit for driving a motor |
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| CN106936332A (en) * | 2015-12-31 | 2017-07-07 | 研能科技股份有限公司 | Drive circuit and its piezoelectric actuated pump being applicable |
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