TWI696908B - Miniature fluid transportation module - Google Patents

Abstract

A miniature fluid transportation module is disclosed and comprises a microprocessor, a special applying integrated circuit, an oscillating circuit and a plurality of MEMS pumps. The microprocessor outputs a time signal, a latch signal and an information signal, the special applying integrated circuit electrically couples with the microprocessor for receiving the time signal, the latch signal and the information signal and comprises a plurality of control circuits, wherein each of the control circuit comprises a shift register, a latch circuit, an AND circuit and a inverter electrical. The shift register electrically couples with the microprocessor for receiving the time signal and the information signal, the latch circuit electrically couples with the microprocessor and the shift register for receiving the latch signal and the information signal, the AND circuit electrically couples with the latch circuit for receiving the information signal outputted from the latch circuit; an inverter electrically couples with the AND circuit. The oscillating circuit outputs an oscillating signal, and the plurality of MEMS pumps electrically couple with the corresponding control circuits.

Description

Miniature fluid delivery module

This case relates to a micro-fluid delivery module, especially a module that uses a control circuit to assist a microprocessor to precisely control multiple micro-electromechanical pumps.

With the rapid development of technology, the application of fluid delivery devices is becoming more and more diversified. For example, industrial applications, biomedical applications, medical care, electronic heat dissipation, etc., and even the most popular wearable devices have been seen in the past. The traditional pump has gradually been towards the miniaturization of the device, please refer to Figure 1, Figure 1 is a schematic diagram of the structure of the micro-electro-mechanical pump module, although the conventional micro-electro-mechanical pump module can pump micro-electro-mechanical The volume of 3'is miniaturized to the micron level, but the micro-electromechanical pump 3'of the micron level will limit the fluid transmission volume due to the too small volume, so multiple micro-electromechanical pumps 3'are required for use. The high-end microprocessor 1'is individually controlled, but the high-end microprocessor 1'itself is costly, and each MEMS pump 3'must have two pins connected, increasing the cost of the high-end microprocessor 1', As a result, the cost of the MEMS pump module remains high and it is difficult to popularize. Therefore, how to reduce the cost of the driving end of the MEMS pump module is currently the first difficulty to overcome.

The main purpose of this case is to provide a micro-fluid delivery module for the special application of integrated circuits to assist the microprocessor to control micro-level micro-electromechanical pumps to achieve effective control of multiple micro-electromechanical pumps.

To achieve the above purpose, the broader implementation of this case is to provide a micro-fluid delivery module, including: a microprocessor, output a clock signal, a latch signal and a data signal; a special application integrated circuit, electrical The microprocessor is connected to receive the clock signal, the latch signal and the data signal. The special application integrated circuit includes a plurality of control circuits. Each control circuit includes: a shift register, electrically connected The microprocessor receives the clock signal and the data signal; a latch circuit electrically connects the microprocessor and the shift register to receive the latch signal and the output from the shift register Data signal; a sum circuit, electrically connected to the latch circuit to receive the data signal output by the latch circuit; an inverter, electrically connected to the sum circuit; an oscillating circuit, electrically connected to the sum circuit to output a The oscillating signal is sent to the sum circuit; a plurality of micro-electromechanical pumps are respectively electrically connected to the control circuits.

100: Micro fluid delivery module

1. 1’: Microprocessor

2: Special application integrated circuit

20: control circuit

20A: the first group of control circuits

20B: The second group of control circuits

21: Shift register

21a: Clock signal input

21b: the first data receiver

21c: the first data output

21d: shift transmission gate

21e: shift inverter

211: P-type metal oxide half field effect transistor

211a: P-type gate input

211b: the first signal input

211c: the first signal output

212: N-type metal oxide half field effect transistor

212a: N-type gate input

212b: Second signal input

212c: Second signal output

213: Second data input terminal

214: Second data output

22: Latch circuit

22a: Latch signal input

22b: Second data receiving end

22c: Second data output

22d: Latch transmission gate

22e: latch reverser

23: Oscillation circuit

231: The first P-type metal oxide half field effect transistor

232: Second P-type metal oxide half field effect transistor

233: Third P-type metal oxide half field effect transistor

234: The first N-type metal oxide half field effect transistor

235: Second N-type metal oxide half field effect transistor

236: Third N-type metal oxide half field effect transistor

237: storage capacitor

238: The first shock reverser

239: Second shock reverser

24: and circuit

24a: Third data receiving end

24b: Receiver of shock signal

24c: the first control signal output

24d: second control signal output

241: Reverse gate

242: And circuit inverter

25: Inverter

25a, 238a, 239a: input terminal

25b, 238b, 239b: output

3. 3’: MEMS pump

31: First electrode

32: Second electrode

Vin: input voltage

T1, T2: contact

FIG. 1 is a schematic structural diagram of a conventional micro-fluid delivery module.

Figure 2A is a schematic diagram of the architecture of the micro-fluid delivery module in this case

Figure 2B is a schematic diagram of the circuit structure of the micro-fluid delivery module of the present case.

FIG. 3A is a schematic diagram of the shift register and latch circuit of the first group of control circuits in FIG. 2.

FIG. 3B is a schematic diagram of the circuit structure of the shift transmission gate in FIG. 3A.

FIG. 3C is a schematic diagram of the circuit architecture of the latch transmission gate in FIG. 3A.

FIG. 4A is a circuit schematic diagram of the oscillation circuit of FIG. 2.

FIG. 4B is a waveform diagram of the oscillation circuit of FIG. 4A.

Fig. 5 is a schematic diagram of the circuit of Fig. 2 and the circuit.

FIG. 6 is a schematic diagram of a shift register and a latch circuit of the second group of control circuits in FIG. 2.

Some typical embodiments embodying the features and advantages of this case will be described in detail in the description in the following paragraphs. It should be understood that this case can have various changes in different forms, and it does not deviate from the scope of this case, and the descriptions and illustrations therein are essentially used for explanation, not for limiting this case.

Please refer to FIGS. 2A and 2B. The micro-fluid delivery module 100 in this case includes: a microprocessor 1, a special application integrated circuit 2 and a plurality of microelectromechanical pumps 3, and the special application integrated circuit 2 has A plurality of control circuits 20 receive a clock signal, a latch signal and a data signal output by the microprocessor 1, each control circuit 20 is corresponding to one of the micro-electromechanical pumps 3 and is not repeated To control the microelectromechanical pumps 3 separately; wherein each microelectromechanical pump 3 has a first electrode 31 and a second electrode 32.

The above-mentioned control circuits 20 each have a shift register 21, a latch circuit 22, a sum circuit 24, and an inverter 25; the shift register 21 includes at least one clock signal input terminal 21a 1. A first data receiving terminal 21b and a first data output terminal 21c. The clock signal input terminal 21a is electrically connected to the microprocessor 1 for receiving the clock signal output by the microprocessor 1. The first data receiving terminal 21b The microprocessor 1 is also electrically connected to receive data signals; the latch circuit 22 has at least one latch signal input terminal 22a, a second data receiver terminal 22b and a second data output terminal 22c, and the latch signal input terminal 22a is electrically Connected to the microprocessor 1 to receive the latch signal output by the microprocessor 1, the second data receiving terminal 22b is electrically connected to the first data output terminal 21c of the shift register 21 to receive the output of the shift register 21 Data signal; and the circuit 24 includes a third data receiving end 24a, a first control signal output end 24c and a second control signal output end 24d, the third data receiving end 24a is electrically connected to the second data output of the latch circuit 22 Terminal 22c to receive the data signal output by the latch circuit 22, the second control signal output terminal 24d is electrically connected to the corresponding first electrode 31 of the corresponding microelectromechanical pump 3; the inverter 25 has an input terminal 25a and an output terminal 25b, the input terminal 25a is electrically connected to the first control signal output terminal 24c of the circuit 24, and the output terminal 25b is electrically connected to the second electrode 32 of the MEMS pump 3.

The micro-fluid delivery module 100 in this case further includes an oscillating circuit 23, and the circuit 24 has an oscillating signal receiving end 24b electrically connected to the oscillating circuit 23 to receive an oscillating signal output by the oscillating circuit 23.

The aforementioned control circuits 20 can be divided into a first group of control circuits 20A and a second group of control circuits 20B. Please refer to FIG. 3A. FIG. 3A shows the circuit structure of the shift register 21 and the latch circuit 22 In the figure, the shift register 21 of the first group of control circuits 20A includes a plurality of shift transmission gates 21d and a plurality of shift inverters 21e. In this embodiment, the shift transmission gates 21d and the shift inversion The number of the devices 21e is four, as shown in FIG. 3B. FIG. 3B is a detailed structural diagram of the shift transmission gate 21d. Each shift transmission gate 21d includes a P-type metal oxide half field effect transistor 211, An N-type metal oxide semiconductor field effect transistor 212, a second data input terminal 213 and a second data output terminal 214, two metal oxide semiconductor field effect transistors (MOSFETs) are used as switches, and P-type metal oxide semiconductor field effect transistors The transistor 211 has a P-type gate input terminal 211a, a first signal input terminal 211b, and a first signal output terminal 211c. The N-type metal oxide half field effect transistor 212 has an N-type gate input terminal 212a, a first Two signal input terminals 212b and a second signal output terminal 212c, the first signal input terminal 211b of the P-type metal-oxide half field effect transistor 211 and the second signal input terminal 212b of the N-type metal-oxide half field effect transistor 212 are electrically connected as The second data input terminal 213, the first signal output terminal 211c and the second signal output terminal 212c are electrically connected as the second data output terminal 214, and the P-type gate input terminals 211a and N of the P-type metal oxide semi-field effect transistor 211 The N-type gate input terminals 212a of the MOSFET 212 are electrically connected to the clock signal input terminal 21a of the shift register 21 respectively to receive the clock signal from the microprocessor 1; please refer to In FIG. 3A, the four shift transmission gates 21d in the shift register 21 are connected in series, and the second data input terminal 213 of the shift transmission gate 21d is electrically connected to the first data of the shift register 21 The receiving terminal 21b, the second data output terminal 214 is electrically connected to the second data input terminal 213 of the next shift transmission gate 21d, and the second data output terminal 214 of the second shift transmission gate 21d is electrically connected to the next The second data input terminal 213 of the shift transmission gate 21d, and the second data output terminal 214 of the shift transmission gate 21d are electrically connected to the second data input terminal 213 of the shift transmission gate 21d at the tail end, and the tail end is shifted The second data output terminal 214 of the transmission gate 21d is electrically connected to the first data output terminal 21c of the shift register 21. In addition, the four shift inverters 21e are connected in series with each other and are respectively transferred to the aforementioned second shift transmission. The gate 21d and the shift transmission gate 21d at the tail end are connected in parallel.

As described above, the clock signals of the P-type gate input terminal 211a and the N-type gate input terminal 212a of the same shift transmission gate 21d are reverse signals, as shown in FIG. 3A, the head shift transmission gate 21d When the P-type gate input terminal 211a receives the reverse clock signal, its N-type gate input terminal 212a receives the clock signal, and the P-type gate input terminal 211a of the third-order shift transmission gate 21d Receiving the clock signal opposite to the first P-type gate input terminal 211a, the N-type gate input terminal 212a of the third-order shift transmission gate 21d receives the reverse clock signal, and the second (second position) The P-type gate input terminal 211a of the shift transmission gate 21d receives the clock signal, the N-type gate input terminal 212a receives the reverse clock signal, and the P-type gate of the shift gate 21d at the tail end (fourth digit) The pole input terminal 211a receives the reverse clock signal opposite to the P-type gate input terminal 211a of the second shift transmission gate 21d, and the N-type gate input terminal 212a receives the clock signal, and so on.

Please continue to refer to FIG. 3A. The latch circuit 22 has two latch transmission gates 22d and two latch inverters 22e. Please refer to FIG. 3C. The two latch transmission gates 22d each include a P-type metal oxide half field effect Transistor 211, an N-type metal oxide half field effect transistor 212, a second data input terminal 213 and a second data output terminal 214, two metal oxide semiconductor field effect transistors (MOSFET) are used as switches, latch The structure of the transmission gate 22d is the same as the above-mentioned shift transmission gate 21d, so it will not be described in detail. Among them, the P-type gate input terminal 211a of the P-type metal-oxide-half field effect transistor 211 of the latch transmission gate 22d , N-type metal oxide half field effect transistor 212 N-type The gate input terminal 212a is electrically connected to the latch signal input terminal 22a of the latch circuit 22, respectively, to receive the latch signal sent by the microprocessor 1; the two latch transmission gates 22d are connected in series, and the latch transmission gate at the front end The second data input terminal 213 of 22d is electrically connected to the second data receiving terminal 22b of the latch circuit 22 to further electrically connect to the first data output terminal 21c of the shift register 21, and the second data output terminal 214 is electrically connected to The second data input terminal 213 of the rear latch transmission gate 22d is electrically connected to the second data output terminal 22c of the latch circuit 22 while the two latches are reversed. 22e is connected in series with the rear latch transmission gate 22d in parallel; in addition, the latch signals received by the P-type gate input terminal 211a and the N-type gate input terminal 212a are reverse signals, and the front-end latch transmission gate The latch signal of the 22d P-type gate input end 211a and the rear-end latch transmission gate 22d P-type gate input end 211a is also a reverse signal, as shown in FIG. 3A, the front-end latch transmission gate 22d When its P-type gate input terminal 211a receives the latch signal, its N-type gate input terminal 212a receives the reverse latch signal, and the P-type gate input terminal 211a of the rear latch transmission gate 22d receives and front-end latch The reverse latch signal of the P-type gate input terminal 211a of the transmission gate 22d is opposite, and the N-type gate input terminal 212a receives the latch signal.

As shown in FIG. 4A, the oscillation circuit 23 includes a first P-type metal-oxide half-field transistor 231, a second P-type metal-oxide half-field transistor 232, and a third P-type metal-oxide half-field transistor 233 , A first N-type metal oxide half-field transistor 234, a second N-type metal oxide half-field transistor 235, a third N-type metal oxide half-field transistor 236, a storage capacitor 237, a first oscillation inversion The commutator 238 and a second oscillating inverter 239, the base of the first P-type metal-oxide half-effect transistor 231 is electrically connected to the source, the base and source of the second P-type metal-oxide half-field transistor 232, The base of the third P-type MOS transistor 233 and a certain voltage of 3.3 volts, the gate of the first P-type MOS transistor 231 is electrically connected to its drain and the second P-type MOS transistor The gate of 232 and the drain of the first N-type metal oxide half-field effect transistor 234, the first N-type metal oxide half-field effect The base of the transistor 234 is electrically connected to its source and ground, and the gate is electrically connected to the gate of the second N-type metal oxide half-field transistor 235 and an input voltage Vin, and the second N-type metal oxide half-field transistor The source of 235 is electrically connected to its base and the base of the third N-type metal oxide half-effect transistor 236 and grounded, and the drain of the third N-type metal oxide half-effect transistor 236 is electrically connected to the third P-type metal oxide The drain of the half field effect transistor 233, one end of the storage capacitor 237, and the input end 238a of the first oscillating inverter 238, the output end 238b of the first oscillating inverter 238 is electrically connected to the input of the second oscillating inverter 239 Terminal 239a, and finally the output end 239b of the second oscillating inverter 239 is connected to the oscillating signal receiving end 24b of the AND circuit 24 and the feedback of the third P-type metal oxide semi-field effect transistor 233 and the third N-type metal oxide half-field effect electric power The gate of crystal 236.

Please refer to Fig. 4B. Fig. 4B is the waveform diagram of the oscillation circuit in Fig. 4A. The input voltage Vin has an input voltage range of 1~3.3V. When the input voltage Vin is 3.3V, the first P-type metal oxide half field effect Transistor 231, second P-type metal oxide half-field transistor 232, third P-type metal oxide half-field transistor 233, first N-type metal oxide half-field transistor 234 and second N-type metal oxide half-field transistor All 235 are turned on, the third N-type metal oxide half-effect transistor 236 is turned off, and the storage capacitor 237 will be charged. When the storage capacitor 237 is fully charged, a positive signal is output to the input terminal of the first oscillating inverter 238 238a. After the positive signal passes through the first oscillating inverter 238, it outputs a negative signal to the input terminal 239a of the second oscillating inverter 239. After the negative signal passes through the second oscillating inverter 239, the oscillating circuit 23 will output a positive signal At the same time, the positive signal will be traced back to the gates of the third P-type metal oxide half-field transistor 233 and the third N-type metal oxide half-field transistor 236. At this time, the third P-type metal oxide half-field transistor 233 will Closed, the storage capacitor 237 will start to discharge. After the storage capacitor 237 is discharged, it will output a negative signal to the input terminal 238a of the first oscillating inverter 238. The first oscillating inverter 238 then reverses the negative signal to a positive signal Output to the input end 239a of the second oscillating inverter 239. The second oscillating inverter 239 then inverts the positive signal to a negative signal, and then traces back to the third P-type metal-oxygen half field effect transistor 233 and the third N-type gold oxide half field effect transistor The gate of the body 236, the third N-type metal oxide half-field transistor 236 is closed, the first P-type metal oxide half-field transistor 231, the second P-type metal oxide half-field transistor 232 and the third P-type metal oxide The half-effect transistors 233 are all turned on, and the storage capacitor 237 begins to charge. After charging, the positive signal is output. The above steps are continued, so that the oscillation circuit 23 can continue to output the opposite positive signal and negative signal, and the storage capacitor 237 is opposite to the first oscillation The contact T1 connected to the commutator 238 will generate a near triangle wave oscillation signal, and after the near triangle wave control signal passes through the first oscillation inverter 238, the control signal will be converted into a near square wave oscillation signal, so the first oscillation is reversed The output terminal 238b of the device 238 will generate an oscillating signal similar to a square wave (contact T2), and then use the second oscillating inverter 239 to adjust the control signal of the approximate square wave to the oscillating signal of the square wave, and finally the second oscillating signal The output terminal 239b of the commutator 239 outputs a oscillating signal whose waveform is a square wave; in addition, the aforementioned first oscillating inverter 238 and second oscillating inverter 239 can also be replaced by Schmitt circuits, which is not limited to this .

Please refer to FIG. 5, and the circuit 24 has an inverting gate 241 and an inverting circuit 242. The two inputs of the inverting gate 241 are connected to the third data receiving end 24a and the oscillation signal receiving end 24b, respectively. The output terminal is electrically connected to the input terminal of the circuit inverter 242, and the output terminal of the circuit inverter 242 is electrically connected to the first control signal output terminal 24c and the second control signal output terminal 24d.

Please refer to FIG. 2B, and the circuit 24 will output the control signal from the first control signal output terminal 24c and the second control signal output terminal 24d according to the oscillating signal and the data signal. An electrode 31 receives the control signal, and the second electrode 32 receives the reverse control signal transmitted by the inverter 25. The first electrode 31 and the second electrode 32 receive the opposite control signal to make the MEMS pump 3 Piezo elements (not shown) are able to accept the transmission of fluid through the piezoelectric effect.

Please continue to refer to FIG. 2B. The first group of control circuits 20A has a plurality of control circuits 20. The first group of control circuits 20A is the first control circuit 20 which is the first of the shift register 21 The data receiving terminal 21b is electrically connected to the microprocessor 1 for receiving data signals, and the first data output terminal 21c is electrically connected to the shift register of the next control circuit 20 in addition to the latch circuit 22 of the same control circuit 20 The first data receiving end 21b of the device 21, and the subsequent control circuit 20 are the same, to transmit the data signal downwards.

Please refer to FIGS. 3A and 6 at the same time, wherein FIG. 6 is a circuit configuration diagram of the shift register 21 and the latch circuit 22 of the second group of control circuits 20B. As shown in the figure, the second group of control circuits 20B of the control circuit 20 has the same structure as the first group of control circuits 20A, and the difference is that the clock signals input by the two are opposite.

In summary, this case provides a micro-fluid delivery module. The microprocessor uses multiple control circuits to assist in controlling multiple micro-electromechanical pumps, which can reduce the burden on the microprocessor and eliminate the high cost of using multiple pins. The high-end processor can easily complete the precise control of each micro-electromechanical pump, and solve the previous problems. It has great industrial use value. You can apply according to law.

This case may be modified by any person familiar with the technology as a craftsman, but it is not as easy as the protection of the patent application.

1: microprocessor

2: Special application integrated circuit

20A: the first group of control circuits

21: Shift register

21b: the first data receiver

22: Latch circuit

22b: Second data receiving end

23: Oscillation circuit

24a: Third data receiving end

24c: the first control signal output

25: Inverter

31: First electrode

20: control circuit

20B: The second group of control circuits

21a: Clock signal input

21c: the first data output

22a: Latch signal input

22c: Second data output

24: and circuit

24b: Receiver of shock signal

24d: second control signal output

3: MEMS pump

32: Second electrode

Claims (10)

A micro-fluid delivery module includes: a microprocessor that outputs a clock signal, a latch signal and a data signal; a special application integrated circuit electrically connected to the microprocessor for receiving the clock signal, The latch signal and the data signal, the special application integrated circuit includes a plurality of control circuits, each of the control circuits includes: a shift register, electrically connected to the microprocessor to receive the clock signal and The data signal; a latch circuit electrically connected to the microprocessor and the shift register to receive the latch signal and the data signal output from the shift register; and a circuit electrically connected to the latch A lock circuit to receive the data signal output from the latch circuit; and an inverter to electrically connect the sum circuit; an oscillation circuit to electrically connect the sum circuit to output an oscillation signal to the sum circuit; and a plurality of The microelectromechanical pump is electrically connected to the plurality of control circuits respectively. The micro-fluid delivery module as described in item 1 of the patent scope, wherein the shift register includes at least one clock signal input terminal, a first data receiving terminal and a first data output terminal, the clock signal The input end is electrically connected to the microprocessor to receive the clock signal, and the first data receiving end is electrically connected to the microprocessor to receive the data signal. The micro-fluid delivery module as described in item 2 of the patent application scope, wherein the latch circuit includes at least a latch signal input terminal, a second data receiving terminal and a second data output terminal, the latch signal input The terminal is electrically connected to the microprocessor to receive the latch signal, and the second data receiving end is electrically connected to the first data output end. The micro-fluid delivery module as described in item 3 of the patent application, wherein the sum circuit includes a third data receiving end, an oscillation signal receiving end, a first control signal output end and a second control signal output end, The third data receiving end is electrically connected to the second data output end, and the oscillation signal receiving end is electrically connected to the oscillation circuit. The micro-fluid delivery module as described in item 4 of the patent application scope, wherein the inverter is electrically connected to the first control signal output end of the AND circuit. The micro-fluid delivery module as described in item 5 of the patent application scope, wherein each of the plurality of micro-electromechanical pumps has two electrodes, and the two electrodes are electrically connected to the inverter corresponding to the inverter and the second circuit Control signal output. The micro-fluid delivery module as described in item 1 of the application scope, wherein the shift register includes a four-shift transmission gate and a four-shift inverter, the four-shift transmission gates are connected in series, and the four-shift The bit inverters are connected in series with each other in parallel with two of the four shift transmission gates. The micro-fluid delivery module as described in item 1 of the patent application scope, wherein the latch circuit includes two latch transmission gates and two latch reversers, the two latch transmission gates are connected in series, and the two latch reverse The commutator is connected in series with one of the two latch transmission gates in parallel. The micro-fluid delivery module as described in item 1 of the patent application scope, wherein the oscillating circuit includes a first P-type metal-oxide half-field transistor, a second P-type metal-oxide half-field transistor, and a third P-type Metal Oxygen Field Effect Transistor, a first N-type Metal Oxygen Field Effect Transistor, a second N-type Metal Oxide Field Effect Transistor, a third N-type Metal Oxide Field Effect Transistor, a storage capacitor, a first An oscillating inverter and a second oscillating inverter, the first P-type metal oxide half field effect transistor, the second P-type metal oxide half field effect transistor, the third P-type metal oxide half field effect transistor, the The first N-type metal oxide half field effect transistor, the second N-type metal oxide half field effect transistor, and the third N-type metal oxide half field effect transistor each have a base, a gate, a source and A drain, the base of the first P-type metal-oxide half-effect transistor is electrically connected to the source thereof, the base of the second P-type metal-oxide half-effect transistor, the source thereof, the third The base of the P-type metal-oxide half-field transistor and a certain voltage, the gate of the first P-type metal-oxide half-field transistor is electrically connected to the drain of the second P-type metal-oxide half-field transistor The gate electrode, the drain electrode of the first N-type metal oxide semi-field effect transistor, the base and the source electrode of the first N-type metal oxide semi-field effect transistor are grounded in parallel, and the gate electrode is electrically connected to the The gate electrode and an input voltage of the second N-type metal oxide semiconductor field effect transistor, the source electrode of the second N-type metal oxide semiconductor field effect transistor is electrically connected to the base and the third N-type metal oxide semiconductor field field The base of the effect transistor is grounded, and the drain of the third N-type metal-oxide half-field transistor is electrically connected to the drain of the third P-type metal-oxide half-field transistor, one end of the storage capacitor, and the An input end of the first oscillating inverter, an output end of the first oscillating inverter is electrically connected to an input end of the second oscillating inverter, and finally an output end of the second oscillating inverter is electrically It is connected to the sum circuit 24 and fed back to the gate of the third P-type metal-oxide-half field-effect transistor and the gate of the third N-type metal-oxide-half field-effect transistor. The micro-fluid delivery module as described in item 1 of the scope of the patent application, wherein the sum circuit includes an inverting gate and an inverting circuit, and the inverting gate and the inverting circuit are connected in series.

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