TWM576158U - Micro fluid delivery module - Google Patents

Abstract

A micro fluid delivery module comprises: a microprocessor, outputting a clock signal, a latch signal and a data signal; a special application integrated circuit electrically connected to the microprocessor for receiving a clock signal, a latch signal and a data signal, special The application integrated circuit includes a plurality of control circuits, each control circuit includes: a shift register, electrically connected to the microprocessor to receive the clock signal and the data signal; and a latch circuit electrically connected to the microprocessor and The shift register is configured to receive the latch signal and the data signal; and the circuit is electrically connected to the latch circuit to receive the data signal output by the latch circuit; the inverter, the electrical connection and the circuit; the oscillating circuit outputs an oscillating signal; A plurality of micro electromechanical pumps are respectively electrically connected to the control circuits.

Description

Micro fluid delivery module

The present invention relates to a micro fluid delivery module, and more particularly to a module that utilizes a control circuit to assist a microprocessor to accurately control a plurality of microelectromechanical pumps.

With the rapid development of technology, the application of fluid delivery devices is becoming more and more diversified. For industrial applications, biomedical applications, medical care, electronic heat dissipation, etc., even the most popular wearable devices can be seen in the shadows. Traditional pumps have gradually become smaller toward the device. Please refer to Figure 1. Figure 1 is a schematic diagram of the structure of the MEMS pump module. The MEMS pump module can be used to pump MEMS. The volume of 3' is miniaturized to the micron level, but the micro-electromechanical pumping 3' will limit the fluid transfer volume due to the small volume, so it is necessary to use multiple MEMS pumps 3', and now it is through a The high-end microprocessor 1' is individually controlled, but the high-end microprocessor 1' itself is costly, and each MEMS pump 3' must have two pins connected, increasing the cost of the high-order microprocessor 1' As a result, the cost of the MEMS pump module is high and difficult to popularize. Therefore, how to reduce the cost of the driving end of the MEMS pump module is the first difficulty to overcome.

The main purpose of this case is to provide a micro fluid delivery module for special application of integrated circuit to assist the microprocessor to control the micro-scale micro-electromechanical pump to achieve effective control of multiple micro-electromechanical pumps.

To achieve the above objective, a broader embodiment of the present invention provides a microfluidic delivery module comprising: a microprocessor for outputting a clock signal, a latch signal, and a data signal; a special application integrated circuit, Connected to the microprocessor for receiving the clock signal, the latch signal and the data signal, the special application integrated circuit comprises a plurality of control circuits, each control circuit comprises: a shift register, an electrical connection The microprocessor receives the clock signal and the data signal; a latch circuit electrically connects the microprocessor and the shift register to receive the latch signal and the output of the shift register a data signal; the circuit is electrically connected to the latch circuit to receive the data signal output by the latch circuit; an inverter is electrically connected to the circuit; and an oscillating circuit is electrically connected to the circuit for output A oscillating signal is sent to the circuit; a plurality of MEMS pumps are electrically connected to the control circuits.

Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It is to be understood that the present invention is capable of various modifications in various embodiments, and is not intended to limit the scope of the invention.

Referring to FIGS. 2A and 2B, the micro fluid delivery module 100 of the present invention comprises: a microprocessor 1, a special application integrated circuit 2, and a plurality of microelectromechanical pumps 3, and the special application integrated circuit 2 has The plurality of control circuits 20 receive a clock signal, a latch signal and a data signal, and each control circuit 20 is electrically connected to one of the micro electromechanical pumps 3, and is not repeated. The microelectromechanical pump 3 is controlled by each of the microelectromechanical pumps 3, wherein each of the microelectromechanical pumps 3 has a first electrode 31 and a second electrode 32.

Each of the control circuits 20 has a shift register 21, a latch circuit 22, a circuit 24 and an inverter 25; the shift register 21 includes at least one clock signal input terminal 21a. a first data receiving end 21b and a first data output end 21c, the clock signal input end 21a is electrically connected to the microprocessor 1 for receiving the clock signal output by the microprocessor 1, the first data receiving end 21b The microprocessor 1 is also electrically connected to receive the data signal; the latch circuit 22 has at least one latch signal input terminal 22a, a second data receiving terminal 22b and a second data output terminal 22c, and the latch signal input terminal 22a is electrically The microprocessor 1 is connected to receive the latch signal outputted by the microprocessor 1, and the second data receiving end 22b is electrically connected to the first data output terminal 21c of the shift register 21 to receive the output of the shift register 21. The data signal 24 includes a third data receiving terminal 24a, a first control signal output terminal 24c and a second control signal output terminal 24d. The third data receiving terminal 24a is electrically connected to the second data output of the latch circuit 22. End 22c, to receive the output of the latch circuit 22 The second control signal output terminal 24d is electrically connected to the first electrode 31 of the corresponding microelectromechanical pump 3; the inverter 25 has an input terminal 25a and an output terminal 25b, and the input terminal 25a is electrically connected and the circuit 24 is The first control signal output terminal 24c and the output terminal 25b are electrically connected to the second electrode 32 of the microelectromechanical pump 3.

The micro fluid delivery module 100 of the present invention further includes an oscillating circuit 23, and the circuit 24 has an oscillating signal receiving end 24b electrically connected to the oscillating circuit 23 for receiving an oscillating signal output from the oscillating circuit 23.

The foregoing control circuits 20 can be divided into a first group of control circuits 20A and a second group of control circuits 20B, as shown in FIG. 3A, and FIG. 3A shows the circuit structure of the shift register 21 and the latch circuit 22. The shift register 21 of the first group of control circuits 20A includes a plurality of shift transfer gates 21d and a plurality of shift inverters 21e. In this embodiment, the shift transfer gate 21d and the shift reverse The number of the devices 21e is four, as shown in FIG. 3B, and FIG. 3B is a detailed structural view of the shift transmission gate 21d. Each of the shift transmission gates 21d includes a P-type MOS field-effect transistor 211, An N-type metal oxide half field effect transistor 212, a transmission gate input terminal 213 and a transmission gate output terminal 214, two metal oxide semiconductor field effect transistors (MOSFETs) are used as switches, and P-type gold oxide half field effect transistors The 211 has a P-type gate input terminal 211a, a first signal input terminal 211b and a first signal output terminal 211c. The N-type gold-oxygen half field effect transistor 212 has an N-type gate input terminal 212a and a second signal. The input end 212b and the second signal output end 212c, the first signal input of the P-type MOS half-effect transistor 211 The second signal input terminal 212b of the 211b and the N-type MOS field-effect transistor 212 is electrically connected as the transmission gate input terminal 213, and the first signal output terminal 211c and the second signal output terminal 212c are electrically connected as the transmission gate output terminal 214, and The P-type gate input terminal 211a of the P-type MOS field-effect transistor 211 and the N-type gate input terminal 212a of the N-type MOS field-effect transistor 212 are electrically connected to the clock signal input of the shift register 21, respectively. The terminal 21a is configured to receive the clock signal sent by the microprocessor 1; please continue to refer to FIG. 3A, the four shift transmission gates 21d in the shift register 21 are connected in series, and the first shift transmission gate 21d The transfer gate input terminal 213 is electrically connected to the first data receiving end 21b of the shift register 21, and the transfer gate output terminal 214 is electrically connected to the transfer gate input terminal 213 of the next shift transfer gate 21d, the next shift The transmission gate output 214 of the transmission gate 21d is electrically connected to the transmission gate input terminal 213 of the shift transmission gate 21d again, and the transmission gate output terminal 214 of the shift transmission gate 21d is again electrically connected to the shift transmission gate of the tail end. 21d transmission gate input terminal 213, tail terminal shift transmission gate 21d transmission gate output The terminal 214 is electrically connected to the data output end 21c of the shift register 21, and further, the four shift inverters 21e are connected in series with the second shift transfer gate 21d and the shift transmission gate of the tail end respectively. 21d in parallel.

As described above, the clock signal of the P-type gate input terminal 211a and the N-type gate input terminal 212a of the same shift transmission gate 21d is a reverse signal. As shown in FIG. 3A, the first shift transmission gate 21d is shown. When the P-type gate input terminal 211a receives the reverse clock signal, the N-type gate input terminal 212a receives the clock signal, and the P-gate input terminal 211a of the third-position shift transmission gate 21d is Receiving a clock signal opposite to the first P-type gate input terminal 211a, the N-type gate input terminal 212a of the third-position shift transmission gate 21d receives the reverse clock signal, and second (second bit) The P-type gate input terminal 211a of the shift transmission gate 21d receives the clock signal, the N-type gate input terminal 212a receives the reverse clock signal, and the tail terminal (fourth bit) shifts the transmission gate 21d to the P-type gate. The pole input terminal 211a receives a reverse clock signal opposite the P-type gate input terminal 211a of the second bit shifting transmission gate 21d, the N-type gate input terminal 212a receives the clock signal, and so on.

Continuing to refer to FIG. 3A, the latch circuit 22 has two latch transmission gates 22d and two latch reversers 22e. Referring to FIG. 3C, the two latch transmission gates 22d respectively include a P-type MOSFET. The transistor 211, an N-type MOS field effect transistor 212, a transmission gate input terminal 213 and a transmission gate output terminal 214, two metal oxide semiconductor field effect transistors (MOSFETs) are used as switches, and the latch transmission gate is used. The structure of 22d is the same as that of the above-mentioned shift transmission gate 21d, and therefore will not be described again. The P-type gate input terminal 211a and N type of the P-type MOS field-effect transistor of the latch transmission gate 22d are not described. The N-type gate input terminal 212a of the gold-oxygen half-field effect transistor is electrically connected to the latch signal input terminal 22a of the latch circuit 22, respectively, to receive the latch signal sent by the microprocessor 1; the two latch transmission gates 22d are connected in series Connected, the transmission gate input end 213 of the latch transmission gate 22d at the front end is electrically connected to the second data receiving end 22b of the latch circuit 22 to further electrically connect the first data output terminal 21c of the shift register 21 for transmission. The brake output 214 is electrically connected to the latch transmission gate 22d at the rear end The second data input end 213, the second data output end 214 of the latch transmission gate 22d of the rear end is electrically connected to the second data output end 22c of the latch circuit 22, and the two latch reversers 22e are connected in series and rear end. The latch transmission gates 22d are connected in parallel; in addition, the latch signals received by the P-type gate input terminal 211a and the N-type gate input terminal 212a are reverse signals, and the P-type gate input terminal of the front latching transmission gate 22d The latch signal of the P-type gate input terminal 211a of the 211a and the rear latch transmission gate 22d is also a reverse signal. As shown in FIG. 3A, the front end latch transmission gate 22d has its P-type gate input terminal 211a. When receiving the latch signal, its N-type gate input terminal 212a receives the reverse latch signal, and the P-type gate input terminal 211a of the rear latch transmission gate 22d receives the P-type gate of the front-end latch transmission gate 22d. The input terminal 211a is opposite the reverse latch signal, and the N-type gate input terminal 212a receives the latch signal.

Referring to FIG. 4A, the oscillating circuit 23 includes a first P-type MOS field effect transistor 231, a second P-type MOS field-effect transistor 232, and a third P-type MOS field-effect transistor 233. a first N-type gold-oxygen half-field effect transistor 234, a second N-type gold-oxygen half-field effect transistor 235, a third N-type gold-oxygen half-field effect transistor 236, a storage capacitor 237, and a first shock counter The base 232 and the second oscillating inverter 239, the base of the first P-type MOS field 231, and the base and source of the second P-type MOS field 232, The base of the third P-type MOS field 233 and a certain voltage of 3.3 volts, the gate of the first P-type MOS field 231 is electrically connected to the drain and the second P-type MOSFET The gate of 232 and the drain of the first N-type gold-oxygen half-field transistor 234, the base of the first N-type gold-oxygen half-field transistor 234 is electrically connected to its source and grounded, and the gate is electrically connected to the second The gate of the N-type gold-oxygen half-field calibration transistor 235 and an input voltage Vin, the source of the second N-type gold-oxygen half-field calibration transistor 235 is electrically connected to its base, the third N The base of the gold-oxygen half-field calibration transistor 236 is grounded, and the drain of the third N-type gold-oxygen half-field transistor 236 is electrically connected to the drain of the third P-type metal oxide half-field transistor 233, one end of the storage capacitor 237, and The input 238a of the first oscillating inverter 238, the output 238b of the first oscillating inverter 238 is electrically coupled to the input 239a of the second oscillating inverter 239, and finally the output 239b of the second oscillating inverter 239 The oscillating signal receiving end 24b of the circuit 24 is connected to the gate of the third P-type MOS field 233 and the third N-type MOS field 236.

Please refer to Figure 4B. Figure 4B is the waveform diagram of the oscillation circuit of Figure 4A. The input voltage Vin input voltage range is 1~3.3V. When the input voltage Vin is 3.3V, the first P-type MOS half-field calibration The transistor 231, the second P-type MOS field 232, the third P-type MOS field 233, the first N-type MOS field 234 and the second N-type MOS half-field transistor 235 is all turned on, and the third N-type MOS half-effect transistor 236 is turned off. At this time, the storage capacitor 237 is charged. When the storage capacitor 237 is fully charged, a positive signal is output to the input end of the first oscillating inverter 238. 238a, the positive signal passes through the first oscillating inverter 238 and outputs a negative signal to the input terminal 239a of the second oscillating inverter 239. After the negative signal passes through the second oscillating inverter 239, the oscillating circuit 23 outputs a positive signal. At the same time, the positive signal will go back to the gate of the third P-type MOS half-electrode 233 and the third N-type MOS half-electrode 236. At this time, the third P-type MOS half-field 233 will When the battery is turned off, the storage capacitor 237 will start to discharge. After the storage capacitor 237 is discharged, it will output a negative signal to the first earthquake. The input 238a of the inverter 238, the first oscillating inverter 238 reverses the negative signal to the positive signal output to the input terminal 239a of the second oscillating inverter 239, and the second oscillating inverter 239 returns the positive signal. The reverse direction is a negative signal output, and back to the gate of the third P-type MOS field 233 and the third N-type MOS field 236, and the third N-type MOS half-field 236 is When closed, the first P-type MOS half-effect transistor 231, the second P-type MOS half-field 232 and the third P-type MOS half-field 233 are all turned on, and the storage capacitor 237 starts to be charged, and then discharged after charging. The positive signal continues the above steps, so that the oscillating circuit 23 can continuously output the opposite positive signal and the negative signal, and the contact T1 connected to the first oscillating inverter 238 at the storage capacitor 237 generates a near triangular wave oscillating signal, and the near After the triangular wave control signal passes through the first oscillating inverter 238, the control signal is converted into a near-square wave oscillating signal, so an oscillation signal similar to a square wave is generated at the output terminal 238b of the first oscillating inverter 238 (contact T2) ), and then use the second oscillating inverter 239 to be near The control signal of the square wave is adjusted to the oscillation signal of the square wave, and finally the output signal 239b of the second oscillation inverter 239 outputs the oscillation signal of the square wave; in addition, the first oscillation invertor 238 and the second oscillation mentioned above The inverter 239 can also be replaced by a Schmidt circuit, and is not limited thereto.

Referring to FIG. 5, the circuit 24 has a reverse gate 241 and a circuit inverter 242. The two input terminals of the reverse gate 241 are respectively connected to the third data receiving end 24a and the oscillating signal receiving end 24b. The output terminal of the electrical connection and the circuit inverter 242, and the output of the circuit inverter 242 are electrically connected to the first control signal output terminal 24c and the second control signal output terminal 24d.

Please refer to FIG. 2B, and the circuit 24 outputs the control signal from the first control signal output terminal 24c and the second control signal output terminal 24d according to the oscillation signal and the data signal output, and is controlled by the micro electromechanical pump 3 An electrode 31 receives the control signal, and the second electrode 32 receives the reverse control signal transmitted by the inverter 25, and the first electrode 31 and the second electrode 32 receive the opposite control signal to cause the microelectromechanical pump 3 to A piezoelectric element (not shown) is adapted to transmit a fluid through a piezoelectric effect.

Referring to FIG. 2B, the first group of control circuits 20A has a plurality of control circuits 20, and the control circuit 20, which is first in the first group of control circuits 20A, is the first data receiving end of the shift register 21. 21b is electrically connected to the microprocessor 1 for receiving the data signal, and the first data output end 21c is electrically connected to the latch circuit 22 of the same control circuit 20, and is also electrically connected to the shift register 21 of the next control circuit 20. The first data receiving end 21b, the subsequent control circuit 20, also transmits the data signal downward.

Please refer to FIG. 3A and FIG. 6 at the same time. FIG. 6 is a circuit configuration diagram of the shift register 21 and the latch circuit 22 of the second group control circuit 20B. As shown, the second group of control circuits 20B of the control circuit 20 has the same structure as the first group of control circuits 20A, with the difference being that the clock signals input to the two are opposite.

In summary, the present invention provides a micro fluid delivery module that utilizes multiple control circuit assists to separately control multiple MEMS pumps, thereby reducing the burden on the microprocessor without the high cost of using multiple pins. With high-end processors, it is easy to accurately control each MEMS pump, and solve the previous problems, which is of great industrial value.

This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.

100‧‧‧Microfluidic transport module

1, 1'‧‧‧Microprocessor

2‧‧‧Special application integrated circuit

20‧‧‧Control circuit

20A‧‧‧First set of control circuits

20B‧‧‧Second group control circuit

21‧‧‧Shift register

21a‧‧‧clock signal input

21b‧‧‧First data receiver

21c‧‧‧First data output

21d‧‧‧Shift transmission gate

21e‧‧‧Shift reverser

211‧‧‧P type MOS half-field calibration crystal

211a‧‧‧P type gate input

211b‧‧‧first signal input

211c‧‧‧first signal output

212‧‧‧N type MOS half-field calibration crystal

212a‧‧‧N type gate input

212b‧‧‧second signal input

212c‧‧‧second signal output

213‧‧‧Transmission gate input

214‧‧‧Transmission gate output

22‧‧‧Latch circuit

22a‧‧‧Latch signal input

22b‧‧‧second data receiver

22c‧‧‧second data output

22d‧‧‧Latch transmission brake

22e‧‧‧Latch reverser

23‧‧‧ oscillating circuit

231‧‧‧First P-type MOS half-field calibration crystal

232‧‧‧Second P-type gold oxide half-field calibration crystal

233‧‧‧ Third P-type MOS half-field calibration crystal

234‧‧‧First N-type gold oxide half-field calibration crystal

235‧‧‧Second N-type gold oxygen half-field electric crystal

236‧‧‧Third N-type gold oxygen half-field electric crystal

237‧‧‧ Storage Capacitor

238‧‧‧First shock reverser

239‧‧‧Second shock reverser

24‧‧‧ and circuit

24a‧‧‧ Third data receiver

24b‧‧‧ Shocking signal receiver

24c‧‧‧first control signal output

24d‧‧‧second control signal output

241‧‧‧Anti-gate

242‧‧‧ and circuit inverter

24a‧‧‧ Third data receiver

24b‧‧‧ Shocking signal receiver

24c‧‧‧first control signal output

24d‧‧‧second control signal output

25‧‧‧ reverser

25a, 238a, 239a‧‧‧ input

25b, 238b, 239b‧‧‧ output

3, 3'‧‧‧Microelectromechanical pump

31‧‧‧First electrode

32‧‧‧second electrode

Figure 1 is a schematic diagram of the structure of a conventional microfluidic delivery module. Fig. 2A is a schematic view showing the structure of the micro fluid conveying module of the present invention. Fig. 2B is a schematic view showing the circuit structure of the micro fluid conveying module of the present invention. Figure 3A is a schematic diagram of the shift register and the latch circuit of the first group of control circuits of Figure 2. FIG. 3B is a schematic diagram of the circuit structure of the shift transmission gate of FIG. 3A. Figure 3C is a schematic diagram of the circuit architecture of the latch transmission gate of Figure 3A. Fig. 4A is a circuit diagram of the oscillating circuit of Fig. 2. Fig. 4B is a waveform diagram of the oscillating circuit of Fig. 4A. Figure 5 is a circuit diagram of the circuit of Figure 2. Figure 6 is a schematic diagram of the shift register and the latch circuit of the second group of control circuits of Figure 2.

Claims (10)

A micro fluid delivery module includes: a microprocessor that outputs a clock signal, a latch signal, and a data signal; a special application integrated circuit electrically connected to the microprocessor for receiving the clock signal, The latching signal and the data signal, the special application integrated circuit includes a plurality of control circuits, each of the control circuits includes: a shift register, electrically connected to the microprocessor to receive the clock signal and The data signal; a latch circuit electrically connecting the microprocessor and the shift register to receive the latch signal and the data signal output by the shift register; and a circuit electrically connecting the latch a lock circuit for receiving the data signal output by the latch circuit; and an inverter for electrically connecting the circuit; an oscillating circuit electrically connecting the circuit to output an oscillating signal to the circuit; and a plurality of The MEMS pump is electrically connected to the plurality of control circuits respectively. The micro fluid delivery module of claim 1, wherein the shift register comprises at least one clock signal input end, a first data receiving end and a first data output end, the clock signal The input terminal is electrically connected to the microprocessor to receive the clock signal, and the first data receiving end is electrically connected to the microprocessor to receive the data signal. The micro fluid delivery module of claim 2, wherein the latch circuit comprises at least one latch signal input end, a second data receiving end and a second data output end, the latch signal input The terminal is electrically connected to the microprocessor to receive the latch signal, and the second data receiving end is electrically connected to the first data output end. The microfluidic delivery module of claim 3, wherein the circuit comprises a third data receiving end, an oscillating signal receiving end, a first control signal output end, and a second control signal output end. The third data receiving end is electrically connected to the second data output end, and the oscillating signal receiving end is electrically connected to the oscillating circuit. The microfluidic delivery module of claim 4, wherein the inverter is electrically connected to the first control signal output of the circuit. The microfluidic delivery module of claim 5, wherein the plurality of microelectromechanical pumps each have two electrodes, the two electrodes being electrically connected to the corresponding inverter and the second of the circuit Control signal output. The micro fluid delivery module of claim 1, wherein the shift register comprises a four shift transmission gate and a four shift inverter, the four shift transmission gates are connected in series, and the four shifts The bit inverters are connected in series two by two and are respectively connected in parallel with two of the four shift transmission gates. The micro fluid delivery module of claim 1, wherein the latch circuit comprises two latch transmission gates and two latch reversers, the two latch transmission gates being connected in series, the two latches being reversed The transmitter is connected in series with one of the two latch transmission gates. The microfluidic delivery module of claim 1, wherein the oscillating circuit comprises a first P-type MOS field effect transistor, a second P-type MOS field effect transistor, and a third P-type. Gold oxygen half field effect transistor, a first N-type gold oxygen half field effect transistor, a second N-type gold oxygen half field effect transistor, a third N-type gold oxygen half field effect transistor, a storage capacitor, a first An oscillating inverter and a second oscillating inverter, the first P-type MOS field effect transistor, the second P-type MOS field-effect transistor, the third P-type MOS field-effect transistor, The first N-type gold-oxygen half-field effect transistor, the second N-type gold-oxygen half-field effect transistor, and the third N-type gold-oxygen half-field effect transistor each have a base, a gate, a source and a a drain, the base of the first P-type MOSFET is electrically connected to the source, the base of the second P-type MOS field, and the source, the third P a base of the MOS field half crystal and a certain voltage, the gate of the first P-type MOSFET is electrically connected to the drain and the second P The gate of the gold oxide half field calibration crystal, the drain of the first N-type gold oxide half field calibration crystal, the base of the first N-type gold oxide half field calibration crystal and the source thereof are grounded, and The gate is electrically connected to the gate of the second N-type MOSFET, and an input voltage, and the source of the second N-type MOSFET is electrically connected to the base thereof. The base of the third N-type gold-oxygen half-field electric crystal is grounded, and the drain of the third N-type gold-oxygen half-field electric crystal is electrically connected to the drain of the third P-type metal oxide half-field electric crystal. One end of the storage capacitor and one input end of the first oscillating inverter, one output of the first oscillating inverter is electrically connected to one input end of the second oscillating inverter, and finally the second oscillating An output of one of the drivers is electrically coupled to the AND circuit 24 and is fed back to the gate of the third P-type MOSFET, the gate of the third N-type MOS field. The microfluidic delivery module of claim 1, wherein the circuit comprises a reverse gate and a circuit inverter, and the reverse gate and the circuit inverter are connected in series.