TWM576158U - Micro fluid delivery module - Google Patents
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Abstract
一種微型流體輸送模組,包含:微處理器,輸出時脈訊號、閂鎖訊號及資料訊號;特殊應用積體電路,電連接微處理器用以接收時脈訊號、閂鎖訊號及資料訊號,特殊應用積體電路包含有複數個控制電路,每一控制電路包含有:移位暫存器,電連接微處理器以接收該時脈訊號及該資料訊號;閂鎖電路,電連接微處理器及移位暫存器,以接收閂鎖訊號及資料訊號;及電路,電連接閂鎖電路,以接收閂鎖電路輸出之資料訊號;反向器,電連接及電路;震盪電路,輸出震盪訊號;複數個微機電泵浦,與該些控制電路分別對應電連接。 A micro fluid delivery module comprises: a microprocessor, outputting a clock signal, a latch signal and a data signal; a special application integrated circuit electrically connected to the microprocessor for receiving a clock signal, a latch signal and a data signal, special The application integrated circuit includes a plurality of control circuits, each control circuit includes: a shift register, electrically connected to the microprocessor to receive the clock signal and the data signal; and a latch circuit electrically connected to the microprocessor and The shift register is configured to receive the latch signal and the data signal; and the circuit is electrically connected to the latch circuit to receive the data signal output by the latch circuit; the inverter, the electrical connection and the circuit; the oscillating circuit outputs an oscillating signal; A plurality of micro electromechanical pumps are respectively electrically connected to the control circuits.
Description
本案係關於一種微型流體輸送模組,尤指一種利用控制電路輔助微處理器來精確控制多個微機電泵浦的模組。The present invention relates to a micro fluid delivery module, and more particularly to a module that utilizes a control circuit to assist a microprocessor to accurately control a plurality of microelectromechanical pumps.
隨著科技的日新月異,流體輸送裝置的應用上亦愈來愈多元化,舉凡工業應用、生醫應用、醫療保健、電子散熱等等,甚至近來熱門的穿戴式裝置皆可見它的踨影,可見傳統的泵浦已漸漸有朝向裝置微小化的趨勢,請參閱第1圖,第1圖為微機電泵浦模組之架構示意圖,習知的微機電泵浦模組雖可將微機電泵浦3’的體積微小化至微米等級,但微米等級的微機電泵浦3’會因為過小的體積限制了流體傳輸量,故需要多個微機電泵浦3’搭配使用,而目前皆是透過一個高階微處理器1’作個別控制,但高階微處理器1’本身成本高,且每個微機電泵浦3’都都必須要兩個接腳連接,增加了高階微處理器1’的成本,導致微機電泵浦模組之成本居高不下,難以普及,因此,如何降低微機電泵浦模組的驅動端的成本,實為目前首要克服的難關。With the rapid development of technology, the application of fluid delivery devices is becoming more and more diversified. For industrial applications, biomedical applications, medical care, electronic heat dissipation, etc., even the most popular wearable devices can be seen in the shadows. Traditional pumps have gradually become smaller toward the device. Please refer to Figure 1. Figure 1 is a schematic diagram of the structure of the MEMS pump module. The MEMS pump module can be used to pump MEMS. The volume of 3' is miniaturized to the micron level, but the micro-electromechanical pumping 3' will limit the fluid transfer volume due to the small volume, so it is necessary to use multiple MEMS pumps 3', and now it is through a The high-end microprocessor 1' is individually controlled, but the high-end microprocessor 1' itself is costly, and each MEMS pump 3' must have two pins connected, increasing the cost of the high-order microprocessor 1' As a result, the cost of the MEMS pump module is high and difficult to popularize. Therefore, how to reduce the cost of the driving end of the MEMS pump module is the first difficulty to overcome.
本案之主要目的在於提供一種微型流體輸送模組,用以特殊應用積體電路協助微處理器來控制微米等級的微機電泵浦,來達到有效控制多個微機電泵浦。The main purpose of this case is to provide a micro fluid delivery module for special application of integrated circuit to assist the microprocessor to control the micro-scale micro-electromechanical pump to achieve effective control of multiple micro-electromechanical pumps.
為達上述目的,本案之較廣義實施態樣為提供一種微型流體輸送模組,包含:一微處理器,輸出一時脈訊號、一閂鎖訊號及一資料訊號;一特殊應用積體電路,電連接該微處理器用以接收該時脈訊號、該閂鎖訊號及該資料訊號,該特殊應用積體電路包含有複數個控制電路,每一控制電路包含有:一移位暫存器,電連接該微處理器以接收該時脈訊號及該資料訊號;一閂鎖電路,電連接該微處理器及該移位暫存器,以接收該閂鎖訊號及該移位暫存器輸出之該資料訊號;;一及電路,電連接該閂鎖電路,以接收該閂鎖電路輸出之該資料訊號;一反向器,電連接該及電路;一震盪電路,電連接該及電路,以輸出一震盪訊號至該及電路;複數個微機電泵浦,與該些控制電路分別對應電連接。To achieve the above objective, a broader embodiment of the present invention provides a microfluidic delivery module comprising: a microprocessor for outputting a clock signal, a latch signal, and a data signal; a special application integrated circuit, Connected to the microprocessor for receiving the clock signal, the latch signal and the data signal, the special application integrated circuit comprises a plurality of control circuits, each control circuit comprises: a shift register, an electrical connection The microprocessor receives the clock signal and the data signal; a latch circuit electrically connects the microprocessor and the shift register to receive the latch signal and the output of the shift register a data signal; the circuit is electrically connected to the latch circuit to receive the data signal output by the latch circuit; an inverter is electrically connected to the circuit; and an oscillating circuit is electrically connected to the circuit for output A oscillating signal is sent to the circuit; a plurality of MEMS pumps are electrically connected to the control circuits.
體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖示在本質上當作說明之用,而非用以限制本案。Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It is to be understood that the present invention is capable of various modifications in various embodiments, and is not intended to limit the scope of the invention.
請參閱第2A圖及第2B圖,本案之微型流體輸送模組100,包含:一微處理器1、一特殊應用積體電路2及複數個微機電泵浦3,特殊應用積體電路2具有複數個控制電路20,接收微處理器1輸出之一時脈訊號、一閂鎖訊號及一資料訊號,每一控制電路20皆各自對應電連接該些微機電泵浦3的其中之一,且不重複,用以分別控制該些微機電泵浦3;其中,每一微機電泵浦3皆具有一第一電極31及一第二電極32。Referring to FIGS. 2A and 2B, the micro fluid delivery module 100 of the present invention comprises: a microprocessor 1, a special application integrated circuit 2, and a plurality of microelectromechanical pumps 3, and the special application integrated circuit 2 has The plurality of control circuits 20 receive a clock signal, a latch signal and a data signal, and each control circuit 20 is electrically connected to one of the micro electromechanical pumps 3, and is not repeated. The microelectromechanical pump 3 is controlled by each of the microelectromechanical pumps 3, wherein each of the microelectromechanical pumps 3 has a first electrode 31 and a second electrode 32.
上述之該些控制電路20皆分別具有一移位暫存器21、一閂鎖電路22、一及電路24以及一反向器25;移位暫存器21包含有至少一時脈訊號輸入端21a、一第一資料接收端21b及一第一資料輸出端21c,時脈訊號輸入端21a電連接微處理器1,用以接收微處理器1所輸出之時脈訊號,第一資料接收端21b亦電連接微處理器1,以接收資料訊號;閂鎖電路22具有至少一閂鎖訊號輸入端22a、一第二資料接收端22b及一第二資料輸出端22c,閂鎖訊號輸入端22a電連接微處理器1以接收微處理器1輸出之閂鎖訊號,該第二資料接收端22b電連接移位暫存器21之第一資料輸出端21c,以接收移位暫存器21所輸出之資料訊號;及電路24包含有一第三資料接收端24a、第一控制訊號輸出端24c及一第二控制訊號輸出端24d,第三資料接收端24a電連接閂鎖電路22的第二資料輸出端22c,來接收閂鎖電路22輸出之該資料訊號,第二控制訊號輸出端24d電連接其對應之微機電泵浦3之第一電極31;反向器25具有一輸入端25a及一輸出端25b,輸入端25a電連接及電路24之第一控制訊號輸出端24c,輸出端25b電連接微機電泵浦3之第二電極32。Each of the control circuits 20 has a shift register 21, a latch circuit 22, a circuit 24 and an inverter 25; the shift register 21 includes at least one clock signal input terminal 21a. a first data receiving end 21b and a first data output end 21c, the clock signal input end 21a is electrically connected to the microprocessor 1 for receiving the clock signal output by the microprocessor 1, the first data receiving end 21b The microprocessor 1 is also electrically connected to receive the data signal; the latch circuit 22 has at least one latch signal input terminal 22a, a second data receiving terminal 22b and a second data output terminal 22c, and the latch signal input terminal 22a is electrically The microprocessor 1 is connected to receive the latch signal outputted by the microprocessor 1, and the second data receiving end 22b is electrically connected to the first data output terminal 21c of the shift register 21 to receive the output of the shift register 21. The data signal 24 includes a third data receiving terminal 24a, a first control signal output terminal 24c and a second control signal output terminal 24d. The third data receiving terminal 24a is electrically connected to the second data output of the latch circuit 22. End 22c, to receive the output of the latch circuit 22 The second control signal output terminal 24d is electrically connected to the first electrode 31 of the corresponding microelectromechanical pump 3; the inverter 25 has an input terminal 25a and an output terminal 25b, and the input terminal 25a is electrically connected and the circuit 24 is The first control signal output terminal 24c and the output terminal 25b are electrically connected to the second electrode 32 of the microelectromechanical pump 3.
本案之微型流體輸送模組100更包含有一震盪電路23,及電路24具有一震盪訊號接收端24b電連接震盪電路23,以接收震盪電路23輸出的一震盪訊號。The micro fluid delivery module 100 of the present invention further includes an oscillating circuit 23, and the circuit 24 has an oscillating signal receiving end 24b electrically connected to the oscillating circuit 23 for receiving an oscillating signal output from the oscillating circuit 23.
前述之該些控制電路20可區分為第一組控制電路20A及第二組控制電路20B,請參閱第3A圖所示,第3A圖為移位暫存器21與閂鎖電路22的電路結構圖,第一組控制電路20A之移位暫存器21包含有複數個移位傳輸閘21d及複數個移位反向器21e,於本實施例中,移位傳輸閘21d及移位反向器21e的數量皆為4個,如第3B圖所示,第3B圖為移位傳輸閘21d之細部結構圖,每一移位傳輸閘21d分別包含一P型金氧半場效電晶體211、一N型金氧半場效電晶體212、一傳輸閘輸入端213及一傳輸閘輸出端214,兩個金屬氧化物半導體場效電晶體(MOSFET)作為開關使用,P型金氧半場效電晶體211具有一P型閘極輸入端211a、一第一訊號輸入端211b及一第一訊號輸出端211c,N型金氧半場效電晶體212具有一N型閘極輸入端212a、一第二訊號輸入端212b及一第二訊號輸出端212c,P型金氧半場效電晶體211之第一訊號輸入端211b及N型金氧半場效電電晶體212之第二訊號輸入端212b電連接作為傳輸閘輸入端213,第一訊號輸出端211c及第二訊號輸出端212c電連接作為傳輸閘輸出端214,而P型金氧半場效電晶體211的P型閘極輸入端211a及N型金氧半場效電晶體212的N型閘極輸入端212a皆分別電連接移位暫存器21之時脈訊號輸入端21a用來接收微處理器1所發出之時脈訊號;請繼續參閱第3A圖,移位暫存器21內的4個移位傳輸閘21d為串聯連接,為首的移位傳輸閘21d其傳輸閘輸入端213電連接至移位暫存器21的第一資料接收端21b,傳輸閘輸出端214電連接到次之的移位傳輸閘21d的傳輸閘輸入端213,次之的移位傳輸閘21d的傳輸閘輸出端214電連接到再次之的移位傳輸閘21d的傳輸閘輸入端213,再次之的移位傳輸閘21d的傳輸閘輸出端214電連接尾端之移位傳輸閘21d的傳輸閘輸入端213,尾端移位傳輸閘21d的傳輸閘輸出端214電連接移位暫存器21之資料輸出端21c,此外,4個移位反向器21e兩兩串連後分別與前述的次之移位傳輸閘21d及尾端之移位傳輸閘21d並聯。The foregoing control circuits 20 can be divided into a first group of control circuits 20A and a second group of control circuits 20B, as shown in FIG. 3A, and FIG. 3A shows the circuit structure of the shift register 21 and the latch circuit 22. The shift register 21 of the first group of control circuits 20A includes a plurality of shift transfer gates 21d and a plurality of shift inverters 21e. In this embodiment, the shift transfer gate 21d and the shift reverse The number of the devices 21e is four, as shown in FIG. 3B, and FIG. 3B is a detailed structural view of the shift transmission gate 21d. Each of the shift transmission gates 21d includes a P-type MOS field-effect transistor 211, An N-type metal oxide half field effect transistor 212, a transmission gate input terminal 213 and a transmission gate output terminal 214, two metal oxide semiconductor field effect transistors (MOSFETs) are used as switches, and P-type gold oxide half field effect transistors The 211 has a P-type gate input terminal 211a, a first signal input terminal 211b and a first signal output terminal 211c. The N-type gold-oxygen half field effect transistor 212 has an N-type gate input terminal 212a and a second signal. The input end 212b and the second signal output end 212c, the first signal input of the P-type MOS half-effect transistor 211 The second signal input terminal 212b of the 211b and the N-type MOS field-effect transistor 212 is electrically connected as the transmission gate input terminal 213, and the first signal output terminal 211c and the second signal output terminal 212c are electrically connected as the transmission gate output terminal 214, and The P-type gate input terminal 211a of the P-type MOS field-effect transistor 211 and the N-type gate input terminal 212a of the N-type MOS field-effect transistor 212 are electrically connected to the clock signal input of the shift register 21, respectively. The terminal 21a is configured to receive the clock signal sent by the microprocessor 1; please continue to refer to FIG. 3A, the four shift transmission gates 21d in the shift register 21 are connected in series, and the first shift transmission gate 21d The transfer gate input terminal 213 is electrically connected to the first data receiving end 21b of the shift register 21, and the transfer gate output terminal 214 is electrically connected to the transfer gate input terminal 213 of the next shift transfer gate 21d, the next shift The transmission gate output 214 of the transmission gate 21d is electrically connected to the transmission gate input terminal 213 of the shift transmission gate 21d again, and the transmission gate output terminal 214 of the shift transmission gate 21d is again electrically connected to the shift transmission gate of the tail end. 21d transmission gate input terminal 213, tail terminal shift transmission gate 21d transmission gate output The terminal 214 is electrically connected to the data output end 21c of the shift register 21, and further, the four shift inverters 21e are connected in series with the second shift transfer gate 21d and the shift transmission gate of the tail end respectively. 21d in parallel.
承上所述,同一移位傳輸閘21d的P型閘極輸入端211a與N型閘極輸入端212a的時脈訊號為反向訊號,如第3A圖所示,為首的移位傳輸閘21d之P型閘極輸入端211a接收反向之時脈訊號時,其N型閘極輸入端212a則接收時脈訊號,排第三位的移位傳輸閘21d之P型閘極輸入端211a則接收與首位之P型閘極輸入端211a相反之時脈訊號,排第三位的移位傳輸閘21d之N型閘極輸入端212a接收反向之時脈訊號,次之(第二位)移位傳輸閘21d的P型閘極輸入端211a接收時脈訊號、N型閘極輸入端212a接收反向之時脈訊號,尾端(第四位)的移位傳輸閘21d的P型閘極輸入端211a接收與第二位之移位傳輸閘21d的P型閘極輸入端211a相反的反向之時脈訊號,其N型閘極輸入端212a接收時脈訊號,以此類推。As described above, the clock signal of the P-type gate input terminal 211a and the N-type gate input terminal 212a of the same shift transmission gate 21d is a reverse signal. As shown in FIG. 3A, the first shift transmission gate 21d is shown. When the P-type gate input terminal 211a receives the reverse clock signal, the N-type gate input terminal 212a receives the clock signal, and the P-gate input terminal 211a of the third-position shift transmission gate 21d is Receiving a clock signal opposite to the first P-type gate input terminal 211a, the N-type gate input terminal 212a of the third-position shift transmission gate 21d receives the reverse clock signal, and second (second bit) The P-type gate input terminal 211a of the shift transmission gate 21d receives the clock signal, the N-type gate input terminal 212a receives the reverse clock signal, and the tail terminal (fourth bit) shifts the transmission gate 21d to the P-type gate. The pole input terminal 211a receives a reverse clock signal opposite the P-type gate input terminal 211a of the second bit shifting transmission gate 21d, the N-type gate input terminal 212a receives the clock signal, and so on.
請繼續參閱第3A圖,閂鎖電路22具有二閂鎖傳輸閘22d及二閂鎖反向器22e,請參考第3C圖所示,二閂鎖傳輸閘22d分別包含有一P型金氧半場效電晶體211、一N型金氧半場效電晶體212、一傳輸閘輸入端213及一傳輸閘輸出端214,兩個金屬氧化物半導體場效電晶體(MOSFET)作為開關使用,閂鎖傳輸閘22d的結構與上述之移位傳輸閘21d為相同結構之傳輸閘,故不加以贅述,其中,閂鎖傳輸閘22d的P型金氧半場效電晶體的P型閘極輸入端211a、N型金氧半場效電晶體的N型閘極輸入端212a分別電連接閂鎖電路22之閂鎖訊號輸入端22a,使其接收微處理器1所發送之閂鎖訊號;兩閂鎖傳輸閘22d串聯連接,位於前端的閂鎖傳輸閘22d的傳輸閘輸入端213電連接閂鎖電路22的第二資料接收端22b,來進一步電連接移位暫存器21的第一資料輸出端21c,而傳輸閘輸出端214電連接位於後端的閂鎖傳輸閘22d的第二資料輸入端213,後端的閂鎖傳輸閘22d的第二資料輸出端214電連接閂鎖電路22的第二資料輸出端22c,而2個閂鎖反向器22e串連後與後端的閂鎖傳輸閘22d並聯連接;此外,P型閘極輸入端211a與N型閘極輸入端212a所接收的閂鎖訊號為反向訊號,前端之閂鎖傳輸閘22d的P型閘極輸入端211a與後端之閂鎖傳輸閘22d的P型閘極輸入端211a的閂鎖訊號亦為反向訊號,如第3A圖所示,前端的閂鎖傳輸閘22d其P型閘極輸入端211a接收閂鎖訊號時,其N型閘極輸入端212a接收反向閂鎖訊號,後端之閂鎖傳輸閘22d之P型閘極輸入端211a接收與前端閂鎖傳輸閘22d之P型閘極輸入端211a相反之反向閂鎖訊號,其N型閘極輸入端212a接收閂鎖訊號。Continuing to refer to FIG. 3A, the latch circuit 22 has two latch transmission gates 22d and two latch reversers 22e. Referring to FIG. 3C, the two latch transmission gates 22d respectively include a P-type MOSFET. The transistor 211, an N-type MOS field effect transistor 212, a transmission gate input terminal 213 and a transmission gate output terminal 214, two metal oxide semiconductor field effect transistors (MOSFETs) are used as switches, and the latch transmission gate is used. The structure of 22d is the same as that of the above-mentioned shift transmission gate 21d, and therefore will not be described again. The P-type gate input terminal 211a and N type of the P-type MOS field-effect transistor of the latch transmission gate 22d are not described. The N-type gate input terminal 212a of the gold-oxygen half-field effect transistor is electrically connected to the latch signal input terminal 22a of the latch circuit 22, respectively, to receive the latch signal sent by the microprocessor 1; the two latch transmission gates 22d are connected in series Connected, the transmission gate input end 213 of the latch transmission gate 22d at the front end is electrically connected to the second data receiving end 22b of the latch circuit 22 to further electrically connect the first data output terminal 21c of the shift register 21 for transmission. The brake output 214 is electrically connected to the latch transmission gate 22d at the rear end The second data input end 213, the second data output end 214 of the latch transmission gate 22d of the rear end is electrically connected to the second data output end 22c of the latch circuit 22, and the two latch reversers 22e are connected in series and rear end. The latch transmission gates 22d are connected in parallel; in addition, the latch signals received by the P-type gate input terminal 211a and the N-type gate input terminal 212a are reverse signals, and the P-type gate input terminal of the front latching transmission gate 22d The latch signal of the P-type gate input terminal 211a of the 211a and the rear latch transmission gate 22d is also a reverse signal. As shown in FIG. 3A, the front end latch transmission gate 22d has its P-type gate input terminal 211a. When receiving the latch signal, its N-type gate input terminal 212a receives the reverse latch signal, and the P-type gate input terminal 211a of the rear latch transmission gate 22d receives the P-type gate of the front-end latch transmission gate 22d. The input terminal 211a is opposite the reverse latch signal, and the N-type gate input terminal 212a receives the latch signal.
請參閱第4A圖所示,震盪電路23包含有一第一P型金氧半場效電晶體231、一第二P型金氧半場效電晶體232、一第三P型金氧半場效電晶體233、一第一N型金氧半場效電晶體234、一第二N型金氧半場效電晶體235、一第三N型金氧半場效電晶體236、一儲存電容237、一第一震盪反向器238及一第二震盪反向器239,第一P型金氧半場校電晶體231的基極電連接源極、第二P型金氧半場校電晶體232的基極及源極、第三P型金氧半場校電晶體233的基極以及一定電壓3.3伏特,第一P型金氧半場校電晶體231的閘極電連接其汲極與第二P型金氧半場校電晶體232的閘極及第一N型金氧半場校電晶體234的汲極,第一N型金氧半場校電晶體234的基極電連接其源極並接地,而閘極電連接至第二N型金氧半場校電晶體235的閘極以及一輸入電壓Vin,第二N型金氧半場校電晶體235的源極會電連接其基極、第三N型金氧半場校電晶體236的基極並接地,第三N型金氧半場校電晶體236的汲極電連接第三P型金氧半場校電晶體233的汲極、儲存電容237的一端以及第一震盪反向器238的輸入端238a,第一震盪反向器238的輸出端238b電連接至第二震盪反向器239的輸入端239a,最後第二震盪反向器239的輸出端239b連接至及電路24的震盪訊號接收端24b以及回授第三P型金氧半場校電晶體233、第三N型金氧半場校電晶體236的閘極。Referring to FIG. 4A, the oscillating circuit 23 includes a first P-type MOS field effect transistor 231, a second P-type MOS field-effect transistor 232, and a third P-type MOS field-effect transistor 233. a first N-type gold-oxygen half-field effect transistor 234, a second N-type gold-oxygen half-field effect transistor 235, a third N-type gold-oxygen half-field effect transistor 236, a storage capacitor 237, and a first shock counter The base 232 and the second oscillating inverter 239, the base of the first P-type MOS field 231, and the base and source of the second P-type MOS field 232, The base of the third P-type MOS field 233 and a certain voltage of 3.3 volts, the gate of the first P-type MOS field 231 is electrically connected to the drain and the second P-type MOSFET The gate of 232 and the drain of the first N-type gold-oxygen half-field transistor 234, the base of the first N-type gold-oxygen half-field transistor 234 is electrically connected to its source and grounded, and the gate is electrically connected to the second The gate of the N-type gold-oxygen half-field calibration transistor 235 and an input voltage Vin, the source of the second N-type gold-oxygen half-field calibration transistor 235 is electrically connected to its base, the third N The base of the gold-oxygen half-field calibration transistor 236 is grounded, and the drain of the third N-type gold-oxygen half-field transistor 236 is electrically connected to the drain of the third P-type metal oxide half-field transistor 233, one end of the storage capacitor 237, and The input 238a of the first oscillating inverter 238, the output 238b of the first oscillating inverter 238 is electrically coupled to the input 239a of the second oscillating inverter 239, and finally the output 239b of the second oscillating inverter 239 The oscillating signal receiving end 24b of the circuit 24 is connected to the gate of the third P-type MOS field 233 and the third N-type MOS field 236.
請參閱第4B圖所示,第4B圖為第4A圖震盪電路的波形圖,輸入電壓Vin輸入電壓範圍為1~3.3V,當輸入電壓Vin為3.3V時,第一P型金氧半場校電晶體231、第二P型金氧半場校電晶體232、第三P型金氧半場校電晶體233、第一N型金氧半場校電晶體234及第二N型金氧半場校電晶體235皆為導通,第三N型金氧半場效電晶體236關閉,此時儲存電容237會進行充電,當儲存電容237充飽後,輸出一正訊號至第一震盪反向器238的輸入端238a,正訊號通過第一震盪反向器238後會輸出一負訊號至第二震盪反向器239的輸入端239a,負訊號通過第二震盪反向器239後,震盪電路23將輸出正訊號,同時,正訊號會回溯至第三P型金氧半場校電晶體233、第三N型金氧半場校電晶體236的閘極,此時,第三P型金氧半場校電晶體233會關閉,儲存電容237將開始放電,儲存電容237放完電後,將輸出負訊號至第一震盪反向器238的輸入端238a,第一震盪反向器238再將負訊號反向為正訊號輸出至第二震盪反向器239的輸入端239a,第二震盪反向器239再將正訊號反向為負訊號輸出,以及再回溯至第三P型金氧半場校電晶體233及第三N型金氧半場校電晶體236的閘極,第三N型金氧半場校電晶體236即關閉,第一P型金氧半場效電晶體231、第二P型金氧半場校電晶體232及第三P型金氧半場校電晶體233皆導通,儲存電容237便開始充電,充電後輸出正訊號,持續以上步驟,使得震盪電路23得以持續輸出相反之正訊號及負訊號,而於儲存電容237與第一震盪反向器238連接的接點T1會產生近三角波的震盪訊號,而近三角波的控制訊號通過第一震盪反向器238後,會將控制訊號轉換近方波震盪訊號,因此於第一震盪反向器238的輸出端238b會產生近似方波的震盪訊號(接點T2),再利用第二震盪反向器239將近似方波的控制訊號調整為方波的震盪訊號,最後由第二震盪反向器239的輸出端239b輸出波形為方波的震盪訊號;此外,前述之第一震盪反向器238、第二震盪反向器239亦可使用舒密特電路取代,並不以此為限。Please refer to Figure 4B. Figure 4B is the waveform diagram of the oscillation circuit of Figure 4A. The input voltage Vin input voltage range is 1~3.3V. When the input voltage Vin is 3.3V, the first P-type MOS half-field calibration The transistor 231, the second P-type MOS field 232, the third P-type MOS field 233, the first N-type MOS field 234 and the second N-type MOS half-field transistor 235 is all turned on, and the third N-type MOS half-effect transistor 236 is turned off. At this time, the storage capacitor 237 is charged. When the storage capacitor 237 is fully charged, a positive signal is output to the input end of the first oscillating inverter 238. 238a, the positive signal passes through the first oscillating inverter 238 and outputs a negative signal to the input terminal 239a of the second oscillating inverter 239. After the negative signal passes through the second oscillating inverter 239, the oscillating circuit 23 outputs a positive signal. At the same time, the positive signal will go back to the gate of the third P-type MOS half-electrode 233 and the third N-type MOS half-electrode 236. At this time, the third P-type MOS half-field 233 will When the battery is turned off, the storage capacitor 237 will start to discharge. After the storage capacitor 237 is discharged, it will output a negative signal to the first earthquake. The input 238a of the inverter 238, the first oscillating inverter 238 reverses the negative signal to the positive signal output to the input terminal 239a of the second oscillating inverter 239, and the second oscillating inverter 239 returns the positive signal. The reverse direction is a negative signal output, and back to the gate of the third P-type MOS field 233 and the third N-type MOS field 236, and the third N-type MOS half-field 236 is When closed, the first P-type MOS half-effect transistor 231, the second P-type MOS half-field 232 and the third P-type MOS half-field 233 are all turned on, and the storage capacitor 237 starts to be charged, and then discharged after charging. The positive signal continues the above steps, so that the oscillating circuit 23 can continuously output the opposite positive signal and the negative signal, and the contact T1 connected to the first oscillating inverter 238 at the storage capacitor 237 generates a near triangular wave oscillating signal, and the near After the triangular wave control signal passes through the first oscillating inverter 238, the control signal is converted into a near-square wave oscillating signal, so an oscillation signal similar to a square wave is generated at the output terminal 238b of the first oscillating inverter 238 (contact T2) ), and then use the second oscillating inverter 239 to be near The control signal of the square wave is adjusted to the oscillation signal of the square wave, and finally the output signal 239b of the second oscillation inverter 239 outputs the oscillation signal of the square wave; in addition, the first oscillation invertor 238 and the second oscillation mentioned above The inverter 239 can also be replaced by a Schmidt circuit, and is not limited thereto.
請參閱第5圖所示,及電路24具有一反及閘241、一及電路反向器242,反及閘241的兩輸入端分別連接第三資料接收端24a及震盪訊號接收端24b,其輸出端電連接及電路反向器242的輸入端,及電路反向器242的輸出端電連接第一控制訊號輸出端24c及第二控制訊號輸出端24d。Referring to FIG. 5, the circuit 24 has a reverse gate 241 and a circuit inverter 242. The two input terminals of the reverse gate 241 are respectively connected to the third data receiving end 24a and the oscillating signal receiving end 24b. The output terminal of the electrical connection and the circuit inverter 242, and the output of the circuit inverter 242 are electrically connected to the first control signal output terminal 24c and the second control signal output terminal 24d.
請在參閱第2B圖所示,及電路24將會依據震盪訊號及資料訊號輸出由第一控制訊號輸出端24c及第二控制訊號輸出端24d輸出控制訊號,並由微機電泵浦3的第一電極31接收控制訊號,以及由第二電極32接收反向器25傳輸之反向的控制訊號,由第一電極31與第二電極32接收相反的控制訊號來使微機電泵浦3內的壓電元件(未圖示)得以接受透過壓電效應來傳輸流體。Please refer to FIG. 2B, and the circuit 24 outputs the control signal from the first control signal output terminal 24c and the second control signal output terminal 24d according to the oscillation signal and the data signal output, and is controlled by the micro electromechanical pump 3 An electrode 31 receives the control signal, and the second electrode 32 receives the reverse control signal transmitted by the inverter 25, and the first electrode 31 and the second electrode 32 receive the opposite control signal to cause the microelectromechanical pump 3 to A piezoelectric element (not shown) is adapted to transmit a fluid through a piezoelectric effect.
請繼續參考第2B圖所示,第一組控制電路20A具有多個控制電路20,於第一組控制電路20A中居首的控制電路20其為移位暫存器21的第一資料接收端21b電連接微處理器1用以接收資料訊號,其第一資料輸出端21c除了電連接同一控制電路20的閂鎖電路22外,亦電連接下一個控制電路20的移位暫存器21的第一資料接收端21b,後續的控制電路20亦同,來將資料訊號向下傳遞。Referring to FIG. 2B, the first group of control circuits 20A has a plurality of control circuits 20, and the control circuit 20, which is first in the first group of control circuits 20A, is the first data receiving end of the shift register 21. 21b is electrically connected to the microprocessor 1 for receiving the data signal, and the first data output end 21c is electrically connected to the latch circuit 22 of the same control circuit 20, and is also electrically connected to the shift register 21 of the next control circuit 20. The first data receiving end 21b, the subsequent control circuit 20, also transmits the data signal downward.
請同時參閱第3A圖及第6圖,其中第6圖為第二組控制電路20B的移位暫存器21與閂鎖電路22的電路結構圖。如圖所示,控制電路20的第二組控制電路20B其結構與第一組控制電路20A相同,差異點為兩者輸入的時脈訊號相反。Please refer to FIG. 3A and FIG. 6 at the same time. FIG. 6 is a circuit configuration diagram of the shift register 21 and the latch circuit 22 of the second group control circuit 20B. As shown, the second group of control circuits 20B of the control circuit 20 has the same structure as the first group of control circuits 20A, with the difference being that the clock signals input to the two are opposite.
綜上所述,本案提供一種微型流體輸送模組,微處理器利用多個控制電路輔助來分別控制多個微機電泵浦,可減少微處理器的負擔,無須使用多個接腳的高成本高階處理器,便可以輕易完成精確控制各微機電泵浦,並且解決先前問題,極具產業之利用價值,爰依法提出申請。In summary, the present invention provides a micro fluid delivery module that utilizes multiple control circuit assists to separately control multiple MEMS pumps, thereby reducing the burden on the microprocessor without the high cost of using multiple pins. With high-end processors, it is easy to accurately control each MEMS pump, and solve the previous problems, which is of great industrial value.
本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.
100‧‧‧微型流體輸送模組100‧‧‧Microfluidic transport module
1、1’‧‧‧微處理器1, 1'‧‧‧Microprocessor
2‧‧‧特殊應用積體電路2‧‧‧Special application integrated circuit
20‧‧‧控制電路20‧‧‧Control circuit
20A‧‧‧第一組控制電路20A‧‧‧First set of control circuits
20B‧‧‧第二組控制電路20B‧‧‧Second group control circuit
21‧‧‧移位暫存器21‧‧‧Shift register
21a‧‧‧時脈訊號輸入端21a‧‧‧clock signal input
21b‧‧‧第一資料接收端21b‧‧‧First data receiver
21c‧‧‧第一資料輸出端21c‧‧‧First data output
21d‧‧‧移位傳輸閘21d‧‧‧Shift transmission gate
21e‧‧‧移位反向器21e‧‧‧Shift reverser
211‧‧‧P型金氧半場校電晶體211‧‧‧P type MOS half-field calibration crystal
211a‧‧‧P型閘極輸入端211a‧‧‧P type gate input
211b‧‧‧第一訊號輸入端211b‧‧‧first signal input
211c‧‧‧第一訊號輸出端211c‧‧‧first signal output
212‧‧‧N型金氧半場校電晶體212‧‧‧N type MOS half-field calibration crystal
212a‧‧‧N型閘極輸入端212a‧‧‧N type gate input
212b‧‧‧第二訊號輸入端212b‧‧‧second signal input
212c‧‧‧第二訊號輸出端212c‧‧‧second signal output
213‧‧‧傳輸閘輸入端213‧‧‧Transmission gate input
214‧‧‧傳輸閘輸出端214‧‧‧Transmission gate output
22‧‧‧閂鎖電路22‧‧‧Latch circuit
22a‧‧‧閂鎖訊號輸入端22a‧‧‧Latch signal input
22b‧‧‧第二資料接收端22b‧‧‧second data receiver
22c‧‧‧第二資料輸出端22c‧‧‧second data output
22d‧‧‧閂鎖傳輸閘22d‧‧‧Latch transmission brake
22e‧‧‧閂鎖反向器22e‧‧‧Latch reverser
23‧‧‧震盪電路23‧‧‧ oscillating circuit
231‧‧‧第一P型金氧半場校電晶體231‧‧‧First P-type MOS half-field calibration crystal
232‧‧‧第二P型金氧半場校電晶體232‧‧‧Second P-type gold oxide half-field calibration crystal
233‧‧‧第三P型金氧半場校電晶體233‧‧‧ Third P-type MOS half-field calibration crystal
234‧‧‧第一N型金氧半場校電晶體234‧‧‧First N-type gold oxide half-field calibration crystal
235‧‧‧第二N型金氧半場校電晶體235‧‧‧Second N-type gold oxygen half-field electric crystal
236‧‧‧第三N型金氧半場校電晶體236‧‧‧Third N-type gold oxygen half-field electric crystal
237‧‧‧儲存電容237‧‧‧ Storage Capacitor
238‧‧‧第一震盪反向器238‧‧‧First shock reverser
239‧‧‧第二震盪反向器239‧‧‧Second shock reverser
24‧‧‧及電路24‧‧‧ and circuit
24a‧‧‧第三資料接收端24a‧‧‧ Third data receiver
24b‧‧‧震盪訊號接收端24b‧‧‧ Shocking signal receiver
24c‧‧‧第一控制訊號輸出端24c‧‧‧first control signal output
24d‧‧‧第二控制訊號輸出端24d‧‧‧second control signal output
241‧‧‧反及閘241‧‧‧Anti-gate
242‧‧‧及電路反向器242‧‧‧ and circuit inverter
24a‧‧‧第三資料接收端24a‧‧‧ Third data receiver
24b‧‧‧震盪訊號接收端24b‧‧‧ Shocking signal receiver
24c‧‧‧第一控制訊號輸出端24c‧‧‧first control signal output
24d‧‧‧第二控制訊號輸出端24d‧‧‧second control signal output
25‧‧‧反向器25‧‧‧ reverser
25a、238a、239a‧‧‧輸入端25a, 238a, 239a‧‧‧ input
25b、238b、239b‧‧‧輸出端25b, 238b, 239b‧‧‧ output
3、3’‧‧‧微機電泵浦3, 3'‧‧‧Microelectromechanical pump
31‧‧‧第一電極31‧‧‧First electrode
32‧‧‧第二電極32‧‧‧second electrode
第1圖為習知的微型流體輸送模組之架構示意圖。 第2A圖為本案微型流體輸送模組之架構示意圖 第2B圖為本案微型流體輸送模組之電路結構示意圖。 第3A圖為第2圖之第一組控制電路其移位暫存器及閂鎖電路示意圖。 第3B圖為第3A圖之移位傳輸閘之電路架構示意圖。 第3C圖為第3A圖之閂鎖傳輸閘之電路架構示意圖。 第4A圖為第2圖之震盪電路的電路示意圖。 第4B圖為第4A圖之震盪電路的波形圖。 第5圖為第2圖之及電路的電路示意圖。 第6圖為第2圖之第二組控制電路其移位暫存器及閂鎖電路示意圖。Figure 1 is a schematic diagram of the structure of a conventional microfluidic delivery module. Fig. 2A is a schematic view showing the structure of the micro fluid conveying module of the present invention. Fig. 2B is a schematic view showing the circuit structure of the micro fluid conveying module of the present invention. Figure 3A is a schematic diagram of the shift register and the latch circuit of the first group of control circuits of Figure 2. FIG. 3B is a schematic diagram of the circuit structure of the shift transmission gate of FIG. 3A. Figure 3C is a schematic diagram of the circuit architecture of the latch transmission gate of Figure 3A. Fig. 4A is a circuit diagram of the oscillating circuit of Fig. 2. Fig. 4B is a waveform diagram of the oscillating circuit of Fig. 4A. Figure 5 is a circuit diagram of the circuit of Figure 2. Figure 6 is a schematic diagram of the shift register and the latch circuit of the second group of control circuits of Figure 2.
Claims (10)
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TWI696908B (en) * | 2018-11-06 | 2020-06-21 | 研能科技股份有限公司 | Miniature fluid transportation module |
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TWI696908B (en) * | 2018-11-06 | 2020-06-21 | 研能科技股份有限公司 | Miniature fluid transportation module |
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