TWI540558B - A bi-directional scanning gate driver module - Google Patents

Description

Bidirectional scanning gate drive module

The invention relates to a gate driving module, in particular to a bidirectional scanning gate driving module.

According to the thin film transistor display, it has become the mainstream of current display technology products, especially for the light weight and convenient carrying of mobile phones. During the operation of the panel, each gate drive circuit is connected to its own scan line, and the scan line will sequentially send a pulse signal, which will turn on all the transistors on the scan line to send the liquid crystal voltage data from the data drive circuit. Into the liquid crystal capacitor. In this way, the liquid crystal transmittance is controlled to achieve a display effect of different brightness, which is the function of the gate driving circuit.

However, after the liquid crystal voltage data transmission is completed, the scanning line must be discharged through the discharge path, and the transistor at the panel is turned off, and in order to achieve the required scanning line discharge speed, the size of the transistor of the discharge path must be large, which will result in The layout area of the gate drive circuit is increased.

Furthermore, the general gate drive circuit will have a transistor that generates an on-state current at any time, so the transistor will increase the overall power consumption. In addition, on the high-resolution panel, the charging time of each scanning line is short, so the load on the charging path for charging the scanning line must be reduced to reduce the rise time and fall time of the load on the charging path for charging and discharging. Improvement.

In view of the above problems, the present invention proposes a technique of bidirectional scanning gate driving module.

One of the objectives of the present invention is to provide a bidirectional scanning gate driving module that can increase the charging and discharging speed of the scanning line, reduce the layout area, and reduce power consumption.

To achieve the above objective, the present invention provides a bidirectional scanning gate driving module having a multi-level gate driving circuit, and each stage gate driving circuit has a plurality of scanning circuits, wherein a first scanning circuit receives a forward signal a reverse signal and a first clock signal, and generating a first scan signal according to the forward signal and the first clock signal, or generating a first scan signal according to the reverse signal and the first clock signal; and The second scanning circuit receives the forward signal, the reverse signal and the second clock signal, generates a second scan signal according to the forward signal and the second clock signal, or generates the second scan signal according to the reverse signal and the second clock signal The second scan signal; when the gate drive module is a forward scan, the forward signal is a first level, the reverse signal is a second level, and the forward signal charges the first scan circuit and the second scan The circuit scans in the forward direction. When the gate drive module is a reverse scan, the forward signal is the second level, the reverse signal is the first level, and the reverse signal is used to charge the second scan circuit and the first scan. Circuit in reverse Scan.

1‧‧‧First stage gate drive circuit

2‧‧‧Second stage gate drive circuit

3‧‧‧third-level gate drive circuit

4‧‧‧4th gate drive circuit

5‧‧‧ Fifth-level gate drive circuit

6‧‧‧ sixth-level gate drive circuit

10‧‧‧Setting unit

11‧‧‧Drive unit

12‧‧‧Setting unit

13‧‧‧Drive unit

14‧‧‧Control unit

15‧‧‧Anti-noise unit

16‧‧‧Anti-noise unit

A0‧‧‧ start signal

A1‧‧‧ control signal

A2‧‧‧ control signal

C1‧‧‧ capacitor

C2‧‧‧ capacitor

C3‧‧‧Control signal

CLK1‧‧‧ first clock signal

CLK2‧‧‧ second clock signal

CLK3‧‧‧ third clock signal

CLK4‧‧‧ fourth clock signal

M1‧‧‧ first setting component

M2‧‧‧Second setting component

M3‧‧‧ drive components

M4‧‧‧second transistor

M5‧‧‧First transistor

M6‧‧‧ third setting component

M7‧‧‧ fourth setting component

M8‧‧‧ drive components

M9‧‧‧4th transistor

M10‧‧‧ Third transistor

M11‧‧‧O crystal

M12‧‧‧O crystal

M13‧‧‧O crystal

M14‧‧‧O crystal

M15‧‧‧protection unit

REF‧‧‧ reference level

S0‧‧‧ start signal

S1‧‧‧ first scan signal

S2‧‧‧ second scan signal

S3‧‧‧ third scan signal

S4‧‧‧ fourth scan signal

S5‧‧‧ fifth scan signal

S6‧‧‧ sixth scan signal

S7‧‧‧ seventh scan signal

S8‧‧‧8th scan signal

S9‧‧‧ ninth scanning signal

S10‧‧‧10th scan signal

S11‧‧‧ eleventh scan signal

S12‧‧‧ twelfth scan signal

T1‧‧‧ first interval

T2‧‧‧Second interval

T3‧‧‧ third interval

T4‧‧‧4th interval

T5‧‧‧ fifth interval

T6‧‧‧ sixth interval

T7‧‧‧ seventh interval

T8‧‧‧ eighth interval

T9‧‧‧9th interval

T10‧‧‧10th interval

T11‧‧‧11th interval

T12‧‧‧Twelfth interval

VDDF‧‧‧ forward signal

VDDR‧‧‧reverse signal

1A is a schematic diagram of an embodiment of a gate driving module of the present invention; FIG. 1B is a schematic diagram of another embodiment of the gate driving module of the present invention when scanning 2 is a circuit diagram of an embodiment of a gate driving circuit of the first A diagram of the present invention; FIG. 3 is a timing diagram of an embodiment of a gate driving circuit for forward scanning according to the present invention; and FIG. 4 is a circuit diagram of an embodiment of a gate driving circuit of the first FIG. And the fifth diagram: it is a timing diagram of an embodiment of the gate drive circuit in the reverse scan of the present invention.

In order to enable the reviewing committee to have a better understanding and understanding of the features and functions of the present invention, the following is a description of the embodiments and the accompanying drawings, and the following is a description of the present invention. A schematic diagram of one embodiment of a gate drive module scanning. As shown in the figure, the bidirectional scanning gate driving module of the present invention has a multi-level gate driving circuit 1-3, and each stage gate driving circuit 1-3 has a plurality of scanning circuits and respectively outputs two scanning signals S1~ S6. The first gate driving circuit 1 of the present invention receives a start signal S0, a first clock signal CLK1 and a second clock signal CLK2 to generate a first scan signal S1 and a second scan signal S2, the first scan The signal S1 and the second scan signal S2 control the plurality of pixels through the plurality of scan lines, wherein the second scan signal S2 is also the start signal of the second gate drive circuit 2, and the scan signal output by the second gate drive circuit 2 is similarly S4 is also the start signal of the third gate driving circuit 3. In other words, if the gate driving circuit 1 is not the first stage, the gate driving circuit 1 similarly receives the scanning signal generated by the previous stage gate driving circuit as the starting signal S0.

Please refer to FIG. 1B, which is a schematic diagram of another embodiment of the gate driving module of the present invention. As shown in the figure, the multi-level gate driving circuit 4-6 is connected in series and each stage of the gate driving circuit 4-6 outputs two scanning signals S7~S12, respectively, and the gate driving circuit 4-6 is also accepted before The scan signal of the first gate drive circuit is used as the start Signal to generate a scan signal to scan a complex pixel. However, the difference between the first B-picture embodiment and the first A-picture embodiment is that the order of the gate driving circuit outputting the scanning signals is different, and the output order of the first A-picture embodiment is from the first-stage gate driving circuit 1 to the third. The stage gate drive circuit 3, the output sequence of the first B embodiment is from the sixth stage gate drive circuit 6 to the fourth stage gate drive circuit 4, and the two embodiments output scan signals in reverse order. In other words, the gate drive module of the present invention can scan the panel bidirectionally, wherein the first A-picture embodiment can be referred to as a forward scan and the first B-picture embodiment is referred to as a reverse scan.

Please refer to the second figure, which is a circuit diagram of an embodiment of the gate driving circuit of the first embodiment of the present invention. As shown in the figure, the first stage gate driving circuit 1 has two scanning circuits. The first scanning circuit includes a setting unit 10 and a driving unit 11. The second scanning circuit includes a setting unit 12 and a driving unit 13. . The setting unit 10 receives a forward signal VDDF and a start signal S0. The start signal S0 controls the setting unit 10 to charge the forward signal VDDF to generate a control signal a1. The driving unit 11 is coupled to the setting unit 10 and receives the control signal a1 and the first clock signal CLK1. The control signal a1 and the first clock signal CLK1 control the driving unit 11 to generate a first scanning signal S1. In other words, the first scan circuit receives the forward signal VDDF and the first clock signal CLK1, and generates the first scan signal S1 according to the forward signal VDDF and the first clock signal CLK1.

The setting unit 12 of the second scanning circuit also receives the other start signal A0 and the forward signal VDDF to generate a control signal a2. The driving unit 13 is coupled to the setting unit 12 and receives the control signal a2 and the second clock signal CLK2. The control signal a2 controls the driving unit 13 to generate a second scanning signal S2 according to the second clock signal CLK2. In other words, the second scan circuit receives the forward signal VDDF and the second clock signal CLK2, and generates the second scan signal S2 according to the forward signal VDDF and the second clock signal CLK2. So the first aspect of the invention The first gate driving circuit 1 outputs the first scanning signal S1 and the second scanning signal S2.

Based on the above, the forward signal VDDF first charges the first scan circuit to generate the first scan signal S1, and then the forward signal VDDF charges the second scan circuit to generate the second scan signal S2, so that the charging path of the forward signal VDDF There is no need to charge the first scanning circuit and the second scanning circuit at the same time, and the charging speed can be increased. In other words, the present invention does not connect the charging point of the first scanning circuit (where the control signal a1 is generated) to the charging point of the second scanning circuit (where the control signal a2 is generated), and reduces the charging path of the forward signal VDDF. The load in . The second stage gate driving circuit 2 and the third stage gate driving circuit 3 operate in the same manner as the first stage gate driving circuit 1, and will not be described again here.

Referring to the second figure, the setting unit 10 of the first scanning circuit includes a first setting component M1 and a second setting component M2. The first setting component M1 has an input terminal, a control terminal and an output terminal, and the input terminal receives The forward signal VDDF, the control terminal receives the start signal S0, the output terminal is coupled to the driving unit 11, and the first setting component M1 generates the control signal a1 according to the start signal S0 and the forward signal VDDF. The second setting component M2 has an input terminal, a control terminal and an output terminal. The input terminal receives the reverse signal VDDR, and the control terminal receives a third scan signal S3 outputted by the second-stage gate driving circuit 2, and the output terminal is coupled. Connected to the driving unit 11, the second setting component M2 sets the control signal a1 according to the third scanning signal S3 and the reverse signal VDDR. In addition, the forward signal is a first level, the reverse signal is a second level, and the first level is higher than the second level.

Furthermore, the driving unit 11 of the first scanning circuit comprises a driving component M3 and a capacitor C1. The driving component M3 can be a transistor having an input terminal, a control terminal and an output terminal. The signal signal CLK1, the control end is coupled to the setting unit 10, and the output end is coupled to the first scanning circuit of the second stage gate driving circuit 2, and the driving element The piece M3 generates the first scanning signal S1 according to the first clock signal CLK1 and the control signal a1. The capacitor C1 is coupled between the control terminal and the output terminal of the driving component M3. The capacitor C1 boosts the level of the first scanning signal S1 according to the control signal a1 and the first clock signal CLK1.

In the above, when the control signal a1 is not controlled, the driving element M3 is turned on, the level of the first end of the capacitor C1 is the level of the control signal a1; when the control signal a1 controls the driving element M3 to be turned on, the capacitor C1 is the second one. The level of the terminal is the level of the first clock signal CLK1, and the level of the first end of the capacitor C1 is changed to the level of the control signal a1 plus the level of the first clock signal CLK1. Thus, when the first clock signal CLK1 is at a high level, the first end of the capacitor C1 is the level of the control signal a1 plus the level of the first clock signal CLK1, that is, the capacitor C1 is controlled according to the control signal a1 and the first The one-time signal CLK1 boosts the level of the first scanning signal S1.

In other words, the driving component M3 of the present invention drives the first scanning signal S1 to a third level according to the first clock signal CLK1, and the driving component M3 drives the first scanning signal S1 to a fourth according to the first clock signal CLK1. Level, wherein the third level is higher than the fourth level. Therefore, in the present invention, the driving element M3 is used to raise and lower the level of the scanning signal S1, and the transistor for lowering the level of the scanning signal (discharge) is not required, and the area of the gate driving circuit layout can be reduced.

Referring to the second figure, the first gate driving circuit 1 of the present invention has an anti-noise circuit including a control unit 14 and a plurality of anti-noise units 15, 16. The anti-noise circuit is coupled to the first scan circuit and the second scan circuit, and receives the first clock signal CLK1 or the second clock signal CLK2 to reduce noise of the first scan circuit and noise of the second scan circuit. The control unit 14 receives the first clock signal CLK1, the second clock signal CLK2, the control signal a1 generated by the first scanning circuit, and the control signal generated by the second scanning circuit. A2, and the control signal a1 generated by the first scanning circuit and the control signal a2 generated by the second scanning circuit control the anti-noise circuit to not enable anti-noise operation, and the first clock signal CLK1 and the first clock signal CLK2 control the anti-jamming The circuit is enabled for anti-noise operation.

Furthermore, the anti-noise unit 15 of the first scanning circuit comprises a first transistor M5 and a second transistor M4. The first transistor M5 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 11 of the first scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to a reference level REF (eg : Ground potential), the first transistor M5 stabilizes the level of the control terminal of one of the driving units 11 of the first scanning circuit at the reference level REF. The second transistor M4 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 11 of the first scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF. The transistor M4 stabilizes the level of the output of one of the driving units 11 of the first scanning circuit to the reference level REF.

The anti-noise unit 16 of the second scanning circuit includes a third transistor M10 and a fourth transistor M9. The third transistor M10 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 13 of the second scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF. The transistor M10 stabilizes the level of the control terminal of one of the driving units 13 of the second scanning circuit at the reference level REF. The fourth transistor M9 has an input terminal, a control terminal and an output terminal. The input terminal is coupled to the driving unit 13 of the second scanning circuit, the control terminal is coupled to the control unit 14, and the output terminal is coupled to the reference level REF. The transistor M9 stabilizes the level of the output of one of the driving units 13 of the second scanning circuit at the reference level REF.

Furthermore, the control unit 14 further includes a protection unit M15 having an input end, a control end and an output end. The input end is coupled to the first transistor M5, the second transistor M4, the third transistor M10 and the first Four transistor M9, the control terminal receives a third clock signal CLK3, the output terminal is coupled to the reference level REF, and the protection unit M15 periodically periodically switches the first transistor M5, the second transistor M4, the third transistor M10, and the fourth transistor M9 according to the third clock signal CLK3. The control terminal is maintained at the reference level REF. Based on the above, the design of the first gate driving circuit 1 of the present invention does not include a transistor that generates an on-current at any time, and power consumption can be reduced.

In the above, the control unit 14 includes a plurality of transistors M11~M14. When the control signal a1 controls the transistor M13 to be turned on, the control signal C3 is the reference level REF. Therefore, the anti-noise circuit does not enable anti-noise operation, in other words, the control signal a1. Anti-noise operation is not enabled by the control anti-noise circuit. When the control signal a1 controls the transistor M13 to be turned off, if the first clock signal CLK1 controls the transistor M11 to be turned on, the control signal C3 is at the level of the first clock signal CLK1, so that the anti-noise circuit enables anti-noise operation. In other words, the control signal a1 and the first clock signal CLK1 control the anti-noise circuit to enable anti-noise operation. In addition, the control signal a2 and the second clock signal CLK2 operate in the same manner as the control signal a1 and the first clock signal CLK1, and are not repeated here.

Based on the above, the first scanning circuit and the second scanning circuit of the present invention share an anti-noise circuit to reduce the layout area of the anti-noise circuit. Furthermore, the anti-noise circuit of the present invention resets the control terminal and the output terminal of the driving units 11, 13 and maintains the reference level REF, so that the bidirectional gate driving circuit 1 can reduce the setting of the reset component. It is also possible to reduce the layout area. In other words, the anti-noise circuit of the present invention simultaneously performs the functions of anti-noise and reset. Therefore, the present invention can reduce the layout area of the plurality of reset components of the gate driving circuit, that is, the invention simultaneously combines the anti-noise circuit required for the dual output gate driving circuit into the first-level gate driving circuit, and effectively reduces The components required for anti-noise circuits.

Please refer to the third figure, which is one of the gate driving circuits in the forward scanning of the present invention. Timing diagram of the example. The timing chart is a timing diagram of the third-stage gate driving circuit 3 of the present invention, and the operation timings of the remaining first-stage gate driving circuit 1 and the second-stage gate driving circuit 2 correspond to the timing of the third-stage gate driving circuit 3. Figure.

In the first interval T1, the third scanning signal S3 is at a high level, and the third scanning signal S3 is a start signal of the third-stage gate driving circuit 3, such that the first setting element M1 and the transistor M13 are in an on state; In this way, the level of the control signal a1 gradually rises due to the charging of the forward signal VDDF, and since the first clock signal CLK1 and the second clock signal CLK2 are reference levels REF, there is no coupling noise, so the control signal C3 is discharged via the transistor M13 to the reference level REF; at this time, the anti-noise circuit is not enabled, and the fifth scan signal S5 is also the reference level REF as the first clock signal CLK1. In the second interval T2, the level of the control signal a1 is charged to the level of the forward signal VDDF, and the second scanning circuit of the third stage gate driving circuit 3 receives the second stage of the gate driving circuit 2. The four scanning signals S4, such that the level of the control signal a2 will gradually increase.

In the third interval T3, the first clock signal CLK1 is changed to a high level, and the level of the control signal a1 is raised to the level of the forward signal VDDF via the charging of the capacitor C1, and the first clock signal CLK1 is added. At the same time, the fifth scan signal S5 can also be raised to a high level, the fifth scan signal S5 and the scan line is charged to a high level; further, the fifth scan signal S5 controls the fourth stage gate drive circuit first In the scanning circuit, the forward signal VDDF can charge the first scanning circuit of the fourth-stage gate driving circuit 4, and the remaining operation modes are the same as the first scanning circuit of the third-stage gate driving circuit 3, and are not repeated; The level of the signal a2 is raised to the level of the forward signal VDDF.

In the fourth interval T4, the first clock signal CLK1 is lowered to the reference level REF, and the level of the control signal a1 is also lowered to the level of the forward signal VDDF, and the fifth scanning signal S5 is also lowered to the reference level REF. The second clock signal CLK2 is changed by the reference level REF The level of the control signal a2 is the level of the forward signal VDDF plus the level of the second clock signal CLK2; at this time, the sixth scanning signal S6 can also be raised to a high level and the scanning line is charged; Similarly, the sixth scanning signal S6 controls the second scanning circuit of the next-stage gate driving circuit. In the fifth interval T5, the second clock signal CLK2 is lowered to the reference level REF, the level of the control signal a2 is also lowered to the level of the forward signal VDDF, and the sixth scanning signal S6 is also lowered to the reference level REF; Furthermore, since the third clock signal CLK3 is at a high level, the seventh scan signal S7 of the fourth-stage gate driving circuit 4 is raised to a high level; in addition, the seventh scanning signal S7 controls the third-level gate driving. The second setting component M2 of the first scanning circuit of the circuit 3 reduces the level of the control signal a1 from the level of the forward signal VDDF to the level of the reference level REF.

In the sixth interval T6, the level of the control signal a2 in the third-stage gate driving circuit 3 is lowered to the reference level REF, and the seventh scanning signal S7 of the fourth-stage gate driving circuit 4 is due to the third clock signal CLK3. The fourth clock signal CLK4 is at a high level, and the fourth stage gate driving circuit 4 is controlled to generate an eighth scanning signal S8. In the seventh interval T7, the first clock signal CLK1 is periodically at a high level, and the transistor M11 of the control unit 14 is turned on, so that the level of the control signal C3 is the first clock signal CLK1. In addition, since the third-stage gate driving circuit 3 does not currently operate, in order to prevent the first clock signal CLK1 from coupling noise to the scanning line, the interval does not use the discharging mechanism to lower the level of the control signal C3, thereby The control signal C3 controls the anti-noise unit 15, 16 to enable anti-noise operation, so that the control terminal and the output terminal of the driving units 11, 13 are reference level REF, and the coupling noise of the first clock signal CLK1 is reduced.

In the eighth interval T8, the first clock signal CLK1 is at a low level (for example, the reference level REF), the transistor M11 is in an off state, and the second clock signal CLK2 is periodically The level is high, and the level of the control signal C3 is not reduced by the discharge, so the anti-noise unit 15 and 16 still perform anti-noise operation, so that the second clock signal CLK2 is not coupled to the scan line. Noise. In the ninth interval T9, the third clock signal CLK3 controls the transistor M15 to be turned on, and the level of the control signal C3 is lowered to the reference level REF, and the anti-noise unit 15, 16 stops performing anti-noise operation; Therefore, the first clock signal CLK1 and the second clock signal CLK2 in the interval are at a low level, so there is no coupling noise, and no anti-noise operation is required. The description of the subsequent tenth interval T10 to the twelfth interval T12 as the aforementioned sixth interval T6 to eighth interval T8 will not be repeated herein.

It can be seen from the above description that the multi-stage gate driving circuit of the high-resolution display, during operation, the third clock signal CLK3 simultaneously controls the discharge of the third-stage gate driving circuit 3 and the four-stage gate driving circuit. The first clock signal CLK1 simultaneously controls the discharge of the fourth stage gate driving circuit 4 and the charging of the fifth stage gate driving circuit 5.

Please refer to the fourth figure, which is a circuit diagram of an embodiment of the gate driving circuit of the first B diagram of the present invention. As shown in the figure, it is the fifth-stage gate driving circuit 5 in the reverse scanning, which is different from the third-stage gate driving circuit 3 in the forward scanning, in the third-stage gate driving in the forward scanning. The circuit 3 is controlled by the second-stage gate driving circuit 2 to generate the scanning signals S5 and S6, and the fifth-stage gate driving circuit 5 is controlled by the sixth-stage gate driving circuit 6 to generate the ninth scanning signal S9 during the reverse scanning. And the tenth scanning signal S10; the third-stage gate driving circuit 3 is controlled by the fourth-stage gate driving circuit 4 to discharge the control signals a1 and a2 in the forward scanning, and the fifth-level gate driving circuit 5 is reverse-scanned in the reverse scanning The fourth stage gate drive circuit controls to discharge the control signals a1, a2.

According to the above, in the forward scanning, the forward signal VDDF is the first level reverse signal VDDR is the second level, and the forward signal VDDF is the second level reverse signal VDDR is the first level in the reverse scanning, so The forward signal VDDF charges the gate drive circuit during forward scanning The reverse signal VDDR discharges the gate drive circuit. In the reverse scan, the reverse signal VDDR charges the gate drive circuit and the forward signal VDDF discharges the gate drive circuit. Moreover, the timing at the time of reverse scanning is as shown in the fifth figure, which is a timing chart of an embodiment of the gate driving circuit in the reverse scanning of the present invention. As shown, the fifth timing is opposite to the third timing, and the opposite timing is used to cause the gate drive circuit to operate in reverse scan. In other words, the first scanning circuit of the first stage gate driving circuit 1 generates the first scanning signal S1 according to the reverse signal VDDR and the first clock signal CLK1, and the second scanning circuit of the first stage gate driving circuit 1 is based on the opposite The first scan signal S2 is generated to the signal VDDR and the second clock signal CLK2. Therefore, the gate driving module of the present invention can scan the display in both directions.

In summary, the present invention provides a bidirectional scanning gate driving module having a multi-level gate driving circuit, and each stage gate driving circuit has a plurality of scanning circuits, wherein a first scanning circuit receives a forward signal a reverse signal and a first clock signal, and generating a first scan signal according to the forward signal and the first clock signal, or generating a first scan signal according to the reverse signal and the first clock signal; and The second scanning circuit receives the forward signal, the reverse signal and the second clock signal, generates a second scan signal according to the forward signal and the second clock signal, or generates the second scan signal according to the reverse signal and the second clock signal The second scan signal; when the gate drive module is a forward scan, the forward signal is a first level, the reverse signal is a second level, and the forward signal charges the first scan circuit and the second scan The circuit scans in the forward direction. When the gate drive module is a reverse scan, the forward signal is the second level, the reverse signal is the first level, and the reverse signal is used to charge the second scan circuit and the first scan. Circuit to operate reverse sweep .

1‧‧‧First stage gate drive circuit

10‧‧‧Setting unit

11‧‧‧Drive unit

12‧‧‧Setting unit

13‧‧‧Drive unit

14‧‧‧Control unit

15‧‧‧Anti-noise unit

16‧‧‧Anti-noise unit

A0‧‧‧ start signal

A1‧‧‧ control signal

A2‧‧‧ control signal

C1‧‧‧ capacitor

C2‧‧‧ capacitor

C3‧‧‧Control signal

CLK1‧‧‧ first clock signal

CLK2‧‧‧ second clock signal

CLK3‧‧‧ third clock signal

M1‧‧‧ first setting component

M2‧‧‧Second setting component

M3‧‧‧ drive components

M4‧‧‧second transistor

M5‧‧‧First transistor

M6‧‧‧ third setting component

M7‧‧‧ fourth setting component

M8‧‧‧ drive components

M9‧‧‧4th transistor

M10‧‧‧ Third transistor

M11‧‧‧O crystal

M12‧‧‧O crystal

M13‧‧‧O crystal

M14‧‧‧O crystal

M15‧‧‧protection unit

REF‧‧‧ reference level

S0‧‧‧ start signal

S1‧‧‧ first scan signal

S2‧‧‧ second scan signal

S3‧‧‧ third scan signal

S4‧‧‧ fourth scan signal

VDDF‧‧‧ forward signal

VDDR‧‧‧reverse signal

Claims (8)

A bidirectional scanning gate driving module has a multi-level gate driving circuit, each stage gate driving circuit has a plurality of scanning circuits, wherein: a first scanning circuit receives a forward signal, a reverse signal and a The first clock signal generates a first scan signal according to the forward signal and the first clock signal, or generates the first scan signal according to the reverse signal and the first clock signal; and a second scan The circuit receives the forward signal, the reverse signal and a second clock signal, generates a second scan signal according to the forward signal and the second clock signal, or according to the reverse signal and the second time The pulse signal generates the second scan signal; wherein, when the gate drive module is a forward scan, the forward signal is a first level, and the reverse signal is a second level, the forward direction The signal is charged by the first scanning circuit and the second scanning circuit to operate the forward scanning. When the gate driving module is a reverse scanning, the forward signal is the second level, and the reverse signal is The first level, the reverse signal charging a second scanning circuit and the first scanning circuit to operate the reverse scanning; wherein the first stage gate driving circuit of the plurality of stages of the gate driving circuit comprises the first scanning circuit, the first scanning circuit comprises: a setting The unit receives a start signal and the forward signal, the start signal controls the setting unit to charge the forward signal to generate a control signal, and a driving unit coupled to the setting unit to receive the control signal And the first clock signal, the control signal and the first clock signal control the driving unit to generate the first scan signal, and the driving unit drives the first scan signal according to the first clock signal The driving unit is driven to lower the first scanning signal to a fourth level according to the first clock signal, and the third level is higher than the fourth level. The bidirectional scanning gate driving module of claim 1, wherein the setting unit comprises: a first setting component having an input end, a control end and an output end, the input end receiving the forward direction a signal, the control terminal receives the start signal, the output end is coupled to the driving unit, the first setting component generates the control signal according to the start signal and the forward signal; and a second setting component has an input a terminal, a control terminal, and an output terminal, the input terminal receives the reverse signal, the control terminal receives a third scan signal generated by a second-stage gate driving circuit, and the output terminal is coupled to the driving unit, the first The second setting component sets the control signal according to the third scanning signal and the reverse signal. The bidirectional scanning gate driving module of claim 1, wherein the driving unit comprises: a driving component having an input terminal, a control terminal and an output terminal, wherein the input terminal receives the first clock The signal is coupled to the setting unit, the output end is coupled to a first scanning circuit of the second stage gate driving circuit, and the driving component generates the first according to the first clock signal and the control signal a scan signal; and a capacitor coupled between the control terminal and the output terminal of the driving component, and the level of the first scan signal is raised according to the control signal and the first clock signal. The bidirectional scanning gate driving module of claim 1, further comprising: an anti-noise circuit coupled to the first scanning circuit and the second scanning circuit to receive the first clock signal, The noise of the first scanning circuit and the noise of the second scanning circuit are reduced. The bidirectional scanning gate driving module of claim 4, wherein the anti-noise circuit comprises: a control unit, receiving the first clock signal, the second clock signal, and the first scanning circuit And generating a control signal and a control signal of the second scanning circuit, the control signal generated by the first scanning circuit and the control signal of the second scanning circuit controlling the anti-noise circuit to not enable anti-noise operation, The first clock signal and the first clock signal control the anti-noise circuit to enable anti-noise operation. The bidirectional scanning gate driving module of claim 4, wherein the anti-noise circuit comprises: a first transistor having an input end, a control end and an output end, wherein the input end is coupled The driving unit of the first scanning circuit is coupled to the control unit, the output end is coupled to a reference level, and the first transistor is configured to control the level of the control end of the driving unit of the first scanning circuit Stabilizing the reference level; a second transistor having an input terminal, a control terminal and an output terminal, the input terminal being coupled to the driving unit of the first scanning circuit, the control terminal being coupled to the control unit, The output terminal is coupled to the reference level, and the second transistor stabilizes the level of the output end of the driving unit of the first scanning circuit at the reference level; a third transistor has an input end and a a control end and an output end, the input end is coupled to a driving unit of the second scanning circuit, the control end is coupled to the control unit, the output end is coupled to the reference level, and the third transistor is configured to be the second Scanning circuit of the driving unit a control terminal is stabilized at the reference level; and a fourth transistor has an input terminal, a control terminal and an output terminal, the input terminal being coupled to the driving unit of the second scanning circuit, the control terminal The control unit is coupled to the reference level, and the fourth transistor stabilizes the level of the output end of the driving unit of the second scanning circuit at the reference level. The bidirectional scanning gate driving module of claim 5, wherein the control unit further comprises: a protection unit having an input end, a control end and an output end, wherein the input end is coupled to the first a third transistor, the second transistor, the third transistor, and the fourth transistor, the control terminal receives a third clock signal, the output terminal is coupled to the reference level, and the protection unit is configured according to the third time And maintaining the control terminal of the first transistor, the second transistor, the third transistor, and the fourth transistor periodically at the reference level. The bidirectional scanning gate driving module of claim 1, wherein the gate driving module receives a third clock signal, and the third clock signal simultaneously controls one of the gate driving modules The first-stage gate driving circuit discharges and the second-stage gate driving circuit is charged, and the first clock signal simultaneously controls the second-stage gate driving circuit discharge of the gate driving module and a third-level gate The drive circuit is charged.