CN111128770B - Method for forming aluminum pad and device containing aluminum pad - Google Patents

Method for forming aluminum pad and device containing aluminum pad Download PDF

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CN111128770B
CN111128770B CN201911291628.0A CN201911291628A CN111128770B CN 111128770 B CN111128770 B CN 111128770B CN 201911291628 A CN201911291628 A CN 201911291628A CN 111128770 B CN111128770 B CN 111128770B
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layer
hard mask
metal interconnection
groove
dielectric layer
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CN111128770A (en
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郭振强
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • H01L2224/03612Physical or chemical etching by physical means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362Photolithography
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622Manufacturing methods by patterning a pre-deposited material using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05016Shape in side view
    • H01L2224/05017Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application discloses a forming method of an aluminum pad and a device comprising the aluminum pad, wherein the method comprises the following steps: forming a second dielectric layer on the first dielectric layer; etching and removing the second dielectric layer on the target metal interconnection line through a photoetching process to form a groove; forming an aluminum metal layer on the surfaces of the second dielectric layer and the groove, wherein the aluminum metal layer in the groove forms a recess; forming a hard mask layer on the surface of the aluminum metal layer; coating a photoresist layer on the hard mask layer; etching to remove the photoresist layer outside the trench and expose the hard mask layer outside the trench; etching to remove the hard mask layer outside the groove and expose the aluminum metal layer outside the groove; and etching to remove the aluminum metal layer outside the groove and the photoresist layer in the groove, so that the second dielectric layer is exposed, and the residual hard mask layer forms a cylindrical hard mask gasket structure on the inner wall of the recess. Because the method provided by the embodiment carries out etching only by one-time photoetching process, the complexity of the manufacturing process is reduced, and the manufacturing cost is reduced to a certain extent.

Description

Method for forming aluminum pad and device containing aluminum pad
Technical Field
The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a method for forming an aluminum pad and a device having the aluminum pad.
Background
In the field of integrated circuit manufacturing, chips are usually required to make aluminum pads (hereinafter referred to as "aluminum pads") for use as test terminals for probe card connection and bonding pads for chip package pins in back-end testing. The aluminum pad plays an important role in signal transmission and use in chip product testing.
Fig. 1 to 4 illustrate a forming method of an aluminum pad provided in the related art, including:
in step S1, as shown in fig. 1, a first layer of metal interconnect 111 and a second layer of metal interconnect 121 and 122 are formed in the first dielectric layer 110, and contact holes 1101 and 1102 are formed between the first layer of metal interconnect 111 and the second layer of metal interconnect 122.
In step S2, as shown in fig. 2, after the second dielectric layer 120 is formed on the first dielectric layer 110, the second dielectric layer on the second metal interconnection line 122 is removed by etching through a photolithography process, so as to form the trench 101.
In step S3, as shown in fig. 3, an aluminum metal layer 130 is formed on the second dielectric layer 120 and the trench 101.
In step S4, as shown in fig. 4, the aluminum metal layer on the second dielectric layer 120 is removed by a photolithography process and an etching process, and the remaining aluminum metal layer forms an aluminum pad (shown by a dotted line in fig. 4) higher than the second dielectric layer 120.
In the method for forming an aluminum pad proposed in the related art, in steps S2 and S4, the aluminum pad needs to be manufactured by two photolithography processes, which is complicated and costly.
Disclosure of Invention
The application provides a forming method of an aluminum pad, which can solve the problems that the forming method of the aluminum pad provided by the related technology is complex in process and high in manufacturing cost.
In one aspect, an embodiment of the present application provides a method for forming an aluminum pad, including:
forming a second dielectric layer on the first dielectric layer, wherein a first layer of metal interconnection lines and a second layer of metal interconnection lines are formed in the first dielectric layer, the first layer of metal interconnection lines are positioned below the second layer of metal interconnection lines, and contact holes are formed between the first layer of metal interconnection lines and the second layer of metal interconnection lines;
removing the second dielectric layer on the target metal interconnection line in the second layer of metal interconnection lines through etching by a photoetching process to form a groove and expose the target metal interconnection line;
forming an aluminum metal layer on the surfaces of the second dielectric layer and the groove, wherein the aluminum metal layer in the groove forms a recess;
forming a hard mask layer on the surface of the aluminum metal layer;
coating a photoresist layer on the hard mask layer;
etching to remove the photoresist layer outside the groove and expose the hard mask layer outside the groove;
etching to remove the hard mask layer outside the groove, so that the aluminum metal layer outside the groove is exposed;
and etching to remove the aluminum metal layer outside the groove and the photoresist layer in the groove, so that the second medium layer is exposed, and the residual hard mask layer forms a cylindrical hard mask gasket structure on the inner wall of the recess, wherein the hard mask gasket structure is higher than the upper surface of the second medium layer.
Optionally, the hard mask layer comprises silicon dioxide.
Optionally, the removing, by etching, the hard mask layer outside the trench includes:
and removing the hard mask layer outside the groove by a dry etching process.
Optionally, an included angle between the sidewall of the trench and a plane where the surface of the first dielectric layer is located is 45 degrees to 70 degrees.
Optionally, the removing the hard mask layer outside the trench by using a dry etching process includes:
and carrying out dry etching on the hard mask layer outside the groove through an incident angle of 45-70 degrees.
Optionally, the removing the photoresist layer in the trench by etching includes:
and removing the photoresist layer in the groove by a dry ashing method.
Optionally, after removing the photoresist layer in the trench by using a dry ashing method, the method further includes:
and cleaning the surface by a wet etching process.
Optionally, after the etching removes the aluminum metal layer outside the trench and the photoresist layer inside the trench, the method further includes:
forming a passivation layer on the second dielectric layer, the hard mask pad structure and the target metal interconnection line;
and etching and removing the passivation layer on the target metal interconnection line by using a photoetching process.
Optionally, the forming a passivation layer on the second dielectric layer, the hard mask pad structure, and the target metal interconnection line includes:
depositing the passivation layer on the second dielectric layer, the hard mask pad structure and the target metal interconnection line by a CVD process.
Optionally, the passivation layer includes silicon nitride and silicon dioxide.
Optionally, the hard mask layer has a thickness of 750 angstroms to 1250 angstroms.
Optionally, the first dielectric layer and the second dielectric layer comprise a low dielectric constant material.
Optionally, the low dielectric constant material comprises silicon dioxide.
Optionally, the first layer of metal interconnect lines and the second layer of metal interconnect lines include copper.
In another aspect, the present application provides a device comprising an aluminum pad, comprising:
the first dielectric layer is internally provided with a first layer of metal interconnection wires and a second layer of metal interconnection wires, the first layer of metal interconnection wires are positioned below the second layer of metal interconnection wires, and contact holes are formed between the first layer of metal interconnection wires and the second layer of metal interconnection wires;
the second dielectric layer is formed above the first dielectric layer, an aluminum metal layer with a concave section is formed in the second dielectric layer, the lower surface of the aluminum metal layer is connected with the upper surface of a target metal interconnection line in the second metal interconnection line, a cylindrical hard mask gasket structure is formed on the inner wall surface of the aluminum metal layer, and the hard mask gasket structure is higher than the upper surface of the second dielectric layer.
The technical scheme at least comprises the following advantages:
after the second dielectric layer is etched through the photoetching process to form the groove, the sunken aluminum metal layer is formed in the groove, the hard mask layer is formed on the aluminum metal layer, the photoresist layer is formed on the hard mask layer, the photoresist layer is etched, the hard mask layer is etched, and the hard mask layer forms a cylindrical hard mask gasket structure on the inner wall of the groove, so that the aluminum pad is formed.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 4 are schematic views illustrating a method of forming an aluminum pad provided in the related art;
FIG. 5 is a flow chart of a method of forming an aluminum pad provided by an exemplary embodiment of the present application;
fig. 6 to 11 are schematic views illustrating a method of forming an aluminum pad according to an exemplary embodiment of the present application;
FIG. 12 is a flowchart of a method for forming a passivation layer on an aluminum pad according to an exemplary embodiment of the present application;
fig. 13 is a schematic diagram of a device including aluminum pads provided in an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 5, which shows a flowchart of a method for forming an aluminum pad according to an exemplary embodiment of the present application, as shown in fig. 5, the method includes:
step 501, forming a second dielectric layer on the first dielectric layer, wherein a first layer of metal interconnection lines and a second layer of metal interconnection lines are formed in the first dielectric layer, the first layer of metal interconnection lines are located below the second layer of metal interconnection lines, and contact holes are formed between the first layer of metal interconnection lines and the second layer of metal interconnection lines.
And 502, removing the second dielectric layer on the target metal interconnection line in the second layer of metal interconnection lines by etching through a photoetching process to form a groove so as to expose the target metal interconnection line.
Step 503, forming an aluminum metal layer on the second dielectric layer and the surface of the trench, and forming a recess in the aluminum metal layer in the trench.
Referring to fig. 6, a schematic diagram of forming a trench 601 and an aluminum metal layer 630 is shown. As shown in fig. 6, a first layer of metal interconnect 6111 and second layers of metal interconnect 6121, 6122 are formed in the first dielectric layer 610, the first layer of metal interconnect 6111 is located below the second layers of metal interconnect 6121, 6122, and contact holes 6101, 6102 are formed between the first layer of metal interconnect 6111 and the second layer of metal interconnect 6122. It should be noted that, in fig. 6, one first-layer metal interconnection line 6111, two second-layer metal interconnection lines 6121 and 6122, and two contact holes 6101 and 6102 are formed in the first dielectric layer 610 as an exemplary illustration, and the embodiment of the present application may include any number of first-layer metal interconnection lines, second-layer metal interconnection lines, and contact holes.
Optionally, the first layer of metal interconnect lines 6111, the second layer of metal interconnect lines 6121 and 6122 comprise copper (Cu); the contact holes 6101, 6102 include tungsten (W); the first dielectric layer 610 and the second dielectric layer 620 include a low dielectric constant material (in the embodiment of the present application, the low dielectric constant material is a material having a dielectric constant lower than 5). The first layer of metal interconnect 6111 may be formed by forming a copper metal layer in a first layer of through hole formed in the first dielectric layer 610 by an electroplating process, and then planarizing; the contact holes 6101 and 6102 can be formed by depositing a tungsten metal layer in a second layer of through holes formed in the first dielectric layer 610 and above the first layer of metal interconnect line 6111 by a Physical Vapor Deposition (PVD) process, and then planarizing; the second layer of metal interconnect lines 6121 and 6122 may be formed by forming a copper metal layer in the third layer of through holes formed in the first dielectric layer 610 by an electroplating process and then planarizing.
Illustratively, in this embodiment, the second dielectric layer 620 may be deposited on the first dielectric layer 610 by a Chemical Vapor Deposition (CVD) process.
For example, in this embodiment, a photoresist may be covered in other regions except the region above the target metal interconnection line 6122 through a photolithography process, and after the second dielectric layer on the target metal interconnection line 6122 is etched, the target metal interconnection line 6122 is exposed, and the photoresist is removed.
Illustratively, an aluminum metal layer 630 may be deposited on the surfaces of the second dielectric layer 620 and the trench 601 by a PVD process.
In step 504, a hard mask layer is formed on the surface of the aluminum metal layer.
Referring to fig. 7, a schematic diagram of forming a hard mask layer 640 on an aluminum metal layer 630 is shown. Illustratively, the hard mask layer 640 may be deposited on the aluminum metal layer 630 by a CVD process. Optionally, in this embodiment, the thickness of the hard mask layer 640 is 750 angstroms to 1250 angstroms.
Step 505, a photoresist layer is coated on the hard mask layer.
Referring to fig. 8, a schematic diagram of the application of a photoresist layer 650 on the hard mask layer 640 is shown. Wherein the photoresist layer 650 comprises an organic photoresist; the photoresist layer 650 may be coated on the hard mask layer 640 by means of a suspension coating.
Step 506, the photoresist layer outside the trench is removed by etching to expose the hard mask layer outside the trench.
Referring to fig. 9, a schematic diagram illustrating the exposure of hard mask layer 640 outside the trench after etching photoresist layer 650 outside trench 601 is shown. Illustratively, the photoresist layer 650 within the trench 601 may be removed by a dry ashing process.
And 507, etching to remove the hard mask layer outside the groove so as to expose the aluminum metal layer outside the groove.
Referring to fig. 10, a schematic diagram of the aluminum metal layer 630 outside the trench is shown after etching to remove the hard mask layer outside the trench 601. Optionally, in this embodiment, the hard mask layer outside the trench 601 may be removed by a dry etching process.
Optionally, in this embodiment, as shown in fig. 6, an included angle α between a sidewall of the trench 601 and a plane where the surface of the first dielectric layer 610 is located is 45 degrees to 70 degrees; optionally, the hard mask layer outside the trench 601 is removed by a dry etching process, including but not limited to: the hard mask layer outside the trench 601 is dry etched through an incident angle of 45 to 70 degrees.
And step 508, etching to remove the aluminum metal layer outside the trench and the photoresist layer inside the trench, so that the second dielectric layer is exposed, and the remaining hard mask layer forms a cylindrical hard mask gasket structure on the inner wall of the recess, wherein the hard mask gasket structure is higher than the upper surface of the second dielectric layer.
Referring to fig. 11, a schematic diagram of a cylindrical hard mask pad structure (shown as a dotted line in fig. 11) formed after removing the aluminum metal layer outside the trench 601 and the photoresist layer inside the trench 601 is shown. The hardmask pad structure in combination with the aluminum metal layer 630 forms an aluminum pad.
In summary, in the embodiment, after the trench is formed by etching the second dielectric layer through the photolithography process, the recessed aluminum metal layer is formed in the trench, the hard mask layer is formed on the aluminum metal layer, the photoresist layer is formed on the hard mask layer, the photoresist layer is etched, and the hard mask layer is etched, so that the hard mask layer forms the cylindrical hard mask gasket structure on the inner wall of the recess, thereby forming the aluminum pad.
Example 2:
fig. 12 shows a flowchart of a method for forming a passivation layer on an aluminum pad according to an exemplary embodiment of the present application, which may be performed after step 508 in the embodiment of fig. 5, and includes:
step 1201, a passivation layer is formed on the second dielectric layer, the hard mask pad structure and the target metal interconnection line.
And 1202, etching and removing the passivation layer on the target metal interconnection line through a photoetching process.
Referring to fig. 13, a schematic diagram after forming a passivation layer 660 is shown. As shown in fig. 13, the passivation layer 660 covers other regions except for the inner walls of the recess of the aluminum metal layer 630 and the inner walls of the hard mask pad structure, leaving the upper surface of the inner walls of the recess of the aluminum metal layer 630 exposed.
Optionally, in this embodiment, a passivation layer 660 may be deposited on the second dielectric layer 620, the hard mask pad structure, and the target metal interconnect line 6122 by a CVD process; optionally, the passivation layer 660 includes silicon nitride (SiN) and silicon dioxide (SiO)2)。
For example, in this embodiment, the step 1202 "removing the passivation layer on the target metal interconnection line by etching through a photolithography process" includes, but is not limited to: and covering the photoresist in the other areas except the area above the target metal interconnection line 6122, etching the passivation layer above the target metal interconnection line 6122 until the upper surface of the inner wall of the recess of the aluminum metal layer 630 is exposed, and removing the photoresist.
Example 3:
referring to fig. 11, which shows a cross-sectional view of a device including an aluminum pad provided in an exemplary embodiment of the present application, the device being fabricated by any of the method embodiments described above, as shown in fig. 11, the device comprising:
the first dielectric layer 610 has a first layer of metal interconnect 6111 and second layers of metal interconnect 6121, 6122 formed therein, the first layer of metal interconnect 6111 is located below the second layers of metal interconnect 6121, 6122, and contact holes 6101, 6102 are formed between the first layer of metal interconnect 6111 and the second layer of metal interconnect 6122.
A second dielectric layer 620 formed above the first dielectric layer 610, wherein an aluminum metal layer 630 with a concave cross section is formed in the second dielectric layer 620, a lower surface of the aluminum metal layer 630 is connected with an upper surface of a target metal interconnect line 6122 in the second metal interconnect line, and a cylindrical hard mask gasket structure (shown by a dotted line in fig. 11) is formed on an inner wall surface of the aluminum metal layer 630, and the hard mask gasket structure is higher than the upper surface of the second dielectric layer 620.
Example 4:
referring to fig. 13, which shows a cross-sectional view of a device comprising an aluminum pad provided by an exemplary embodiment of the present application, the device being fabricated by the method of embodiment 2 described above, as shown in fig. 13, the device being different from the device provided by embodiment 3 in that:
the passivation layer 660 is formed on the other regions except for the inner walls of the recess of the aluminum metal layer 630 and the inner walls of the hard mask pad structure. Optionally, the passivation layer comprises silicon nitride and silicon dioxide.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (14)

1. A method of forming an aluminum pad, comprising:
forming a second dielectric layer on the first dielectric layer, wherein a first layer of metal interconnection lines and a second layer of metal interconnection lines are formed in the first dielectric layer, the first layer of metal interconnection lines are positioned below the second layer of metal interconnection lines, and contact holes are formed between the first layer of metal interconnection lines and the second layer of metal interconnection lines;
removing the second dielectric layer on the target metal interconnection line in the second layer of metal interconnection lines through etching by a photoetching process to form a groove and expose the target metal interconnection line;
forming an aluminum metal layer on the surfaces of the second dielectric layer and the groove, wherein the aluminum metal layer in the groove forms a recess;
forming a hard mask layer on the surface of the aluminum metal layer, wherein the hard mask layer comprises silicon dioxide;
coating a photoresist layer on the hard mask layer;
etching to remove the photoresist layer outside the groove and expose the hard mask layer outside the groove;
etching to remove the hard mask layer outside the groove, so that the aluminum metal layer outside the groove is exposed;
and etching to remove the aluminum metal layer outside the groove and the photoresist layer in the groove, so that the second medium layer is exposed, and the residual hard mask layer forms a cylindrical hard mask gasket structure on the inner wall of the recess, wherein the hard mask gasket structure is higher than the upper surface of the second medium layer.
2. The method of claim 1, wherein the etching to remove the hard mask layer outside the trench comprises:
and removing the hard mask layer outside the groove by a dry etching process.
3. The method of claim 2, wherein an angle between a sidewall of the trench and a plane in which a surface of the first dielectric layer is located is 45 degrees to 70 degrees.
4. The method of claim 3, wherein removing the hard mask layer outside the trench by a dry etching process comprises:
and carrying out dry etching on the hard mask layer outside the groove through an incident angle of 45-70 degrees.
5. The method of claim 4, wherein the etching removes the photoresist layer within the trench, comprising:
and removing the photoresist layer in the groove by a dry ashing method.
6. The method according to claim 5, further comprising, after removing the photoresist layer in the trench by a dry ashing method:
and cleaning the surface by a wet etching process.
7. The method of any one of claims 1 to 6, wherein after the etching removes the aluminum metal layer outside the trench and the photoresist layer inside the trench, the method further comprises:
forming a passivation layer on the second dielectric layer, the hard mask pad structure and the target metal interconnection line;
and etching and removing the passivation layer on the target metal interconnection line by using a photoetching process.
8. The method of claim 7, wherein said forming a passivation layer on said second dielectric layer, said hard mask pad structure and said target metal interconnect line comprises:
depositing the passivation layer on the second dielectric layer, the hard mask pad structure and the target metal interconnection line by a CVD process.
9. The method of claim 8, wherein the passivation layer comprises silicon nitride and silicon dioxide.
10. The method of any of claims 1 to 6, wherein the hard mask layer has a thickness of 750 to 1250 angstroms.
11. The method of claim 10, wherein the first dielectric layer and the second dielectric layer comprise a low dielectric constant material.
12. The method of claim 11, wherein the low dielectric constant material comprises silicon dioxide.
13. The method of claim 12, wherein the first layer of metal interconnect lines and the second layer of metal interconnect lines comprise copper.
14. A device comprising an aluminum pad, comprising:
the first dielectric layer is internally provided with a first layer of metal interconnection wires and a second layer of metal interconnection wires, the first layer of metal interconnection wires are positioned below the second layer of metal interconnection wires, and contact holes are formed between the first layer of metal interconnection wires and the second layer of metal interconnection wires;
the second dielectric layer is formed above the first dielectric layer, an aluminum metal layer with a concave section is formed in the second dielectric layer, the lower surface of the aluminum metal layer is connected with the upper surface of a target metal interconnection line in the second metal interconnection line, a cylindrical hard mask gasket structure is formed on the inner wall surface of the aluminum metal layer, the hard mask gasket structure is higher than the upper surface of the second dielectric layer, and the hard mask gasket structure comprises silicon dioxide.
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