CN100419926C - Manufacture of high-density laminated metal capacitor element - Google Patents
Manufacture of high-density laminated metal capacitor element Download PDFInfo
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- CN100419926C CN100419926C CNB021035121A CN02103512A CN100419926C CN 100419926 C CN100419926 C CN 100419926C CN B021035121 A CNB021035121 A CN B021035121A CN 02103512 A CN02103512 A CN 02103512A CN 100419926 C CN100419926 C CN 100419926C
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- dielectric layer
- capacitor element
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- metal blocks
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Abstract
The present invention relates to a manufacture method for high-density laminated metal capacitor elements. The method comprises the following steps: (a) providing a semiconductor substrate with an embedded first metal block of which the upper surface is exposed out of one part of the surface of the substrate; (b) completely forming a first dielectric layer on the semiconductor substrate; (c) selectivity eliminating the first dielectric layer to form a first opening exposed out of the first metal block in order to define the range of a second metal block; (d) filling the second metal block into the first opening to make the first metal block and the second metal block used as a bottom electrode of a capacitor element; (e) completely forming a second dielectric layer on the bottom electrode of the metal capacitor element; (f) selectivity eliminating the second dielectric layer to form a second opening exposed out of the surface of bottom electrode of the metal capacitor element; (g) forming a third dielectric layer at the bottom and on the side wall of the second opening with compliance to be used as an electricity layer of the capacitor element; (h) filling a third metal block into the second opening to be used as an upper electrode of the capacitor element.
Description
Technical field
The present invention is particularly to a kind of manufacture method that can increase high-density laminated (high density stacked) MIM copper capacity cell of electrode area relevant for a kind of manufacture method of high-density laminated metal capacitor element.
Background technology
Consult shown in Figure 1ly, it shows the generalized section of the flat MIM copper electric capacity of conventional art.Symbol 10 expression is embedded in the copper substrate at the semiconductor-based end, is used as the bottom electrode of capacity cell, and symbol 11 expressions are used for being used as the copper block of the top electrode of capacity cell, the dielectric layer between the symbol 12 expression upper/lower electrodes.Though copper at present " " be the optimal selection of capacitance electrode material, but being subject to the copper metal can only remove with cmp (CMP), can't use the mode of traditional chemical dry ecthing or wet etching to remove, therefore be difficult to produce the electric capacity copper electrode that piles up shape.So at present general industry still adopts traditional flat MIM copper electric capacity.
But along with the capacity cell downsizing, and when increasing the capacity of electric capacity again, there are two research directions to consider, the firstth, improve the characteristic of dielectric material, the secondth, increase the area of capacitance electrode.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of high-density laminated metal capacitor element, utilize chemical mechanical milling method and traditional deposition, photoetching etch process, do not changing under traditional dielectric material, producing and have high-density laminated MIM metal capacitor element; Promptly under same volumetric spaces, reaching has the area of bigger capacitance electrode than traditional flat metal capacitance and the purpose of bigger electric capacity storage is arranged.
The object of the present invention is achieved like this: the present invention utilizes chemical mechanical milling method and traditional deposition, photoetching etch process, produces to have high-density laminated MIM metal capacitor element, and its making step comprises:
(a) provide a semiconductor-based end that is inlaid with one first metal blocks, the upper surface that this first metal blocks is arranged is exposed on this base part surface;
(b) above this semiconductor-based end, form one first dielectric layer comprehensively;
(c) optionally remove this first dielectric layer, and form one first opening that exposes this first metal blocks, to define the scope of one second metal blocks;
(d) in this first opening, insert this second metal blocks, make this first metal blocks and this second metal blocks be used as the bottom electrode of this metal capacitor element;
(e) remove remaining first dielectric layer, above the bottom electrode of this metal capacitor element and the semiconductor-based end, form second dielectric layer comprehensively;
(f) optionally remove this second dielectric layer, and form second opening that exposes this metal capacitor element lower electrode surface, this second aperture efficiency, first opening is big;
(g) bottom and the sidewall compliance at this second opening forms one the 3rd dielectric layer, to be used as the dielectric layer of this capacity cell;
(h) in this second opening, insert one the 3rd metal blocks, to be used as the top electrode of this capacity cell.
Wherein carrying out step (b) before, more comprising above this semiconductor-based end, forming an etching stopping layer comprehensively.Wherein after carrying out remaining first dielectric layer of removing of step (e) and comprehensivelyly before forming second dielectric layer at the bottom electrode of this metal capacitor element and the semiconductor-based end, more be included in this this semiconductor-based end and lower electrode surface compliance and form an etching stopping layer.Wherein this of said method first, second and third metal blocks for example is metal blocks such as Cu, Pt, Pd or Ru.Wherein first and second dielectric layer of this of said method for example is a silicon dioxide.Wherein the 3rd dielectric layer in order to the dielectric layer of being used as this capacity cell of said method is silicon nitride (SiN/Si
3N
4) or the dielectric material of silicon oxynitride high-dielectric coefficients such as (SiON).
Wherein the method for inserting this second and third metal blocks of said method comprises the following steps: to form this second and third metal blocks with sedimentation (for example CVD) earlier comprehensively, then utilizes chemical mechanical milling method (CMP) to carry out the planarization of this second and third metal blocks again.
Major advantage of the present invention is to provide a kind of not to be needed to change under traditional dielectric material, with deposition, photoetching etching step, add and utilize chemical mechanical milling method, unnecessary metal blocks surface is removed and polished, (for example: the method for piling up (stacked of copper) processing procedure manufacturing MIM electric capacity copper) can make the capacitance of MIM electric capacity increase than classic flat-plate formula electric capacity and use metal.
Describe in detail below in conjunction with the preferred embodiment conjunction with figs..
Description of drawings
Fig. 1 is the generalized section of the flat MIM copper electric capacity of conventional art.
Fig. 2 is the generalized section of high-density laminated MIM copper electric capacity of the present invention.
Fig. 3-the 12nd, the manufacture process schematic diagram of high-density laminated MIM copper electric capacity of the present invention.
Embodiment
Consult shown in Fig. 3-12, be high-density laminated MIM capacity cell processing procedure generalized section of the present invention.
At first, consult shown in Figure 3ly, a semiconductor-based end 100 that is inlaid with first metal blocks 110 is provided, these substrate 100 part surfaces expose the upper surface that this first metal blocks 110 is arranged, and this first metal blocks 110 is bottom electrodes of being used as capacity cell.Be noted that in addition present embodiment this first and second and three metal blocks 110 for example be metal blocks such as Cu, Pt, Pd or Ru, but present embodiment is the example explanation with the copper block.
Then consult shown in Figure 4ly, can on the semiconductor-based end 100, form an etching stopping layer 120, for example SiN or SiON earlier comprehensively.Then, first dielectric layer 130 of comprehensive landform precedent such as silicon dioxide layer then applies a photoresist layer 140 on this first dielectric layer 130 again, and with the lithographic definition pattern.Remove this photoresist layer 140 afterwards again.
Then, consult shown in Figure 5ly, optionally this first dielectric layer 130, this etching stopping layer 120 are removed in etching, and form one first opening 150 that exposes this first bronze medal block 110, with the scope of the one second bronze medal block 160 that defines this capacity cell.Engraving method for example makes with photoresist 140 to be mask, and (RIE) carries out anisotropic etching by reactive ion-etching.
Then, consult shown in Figure 6ly, in this first opening 150, form one second bronze medal block 160, for example use CVD that copper is deposited up.Then, utilize chemical mechanical milling method (chemical mechanicalpolishing; CMP) to remove this second bronze medal block 160 of part, the surface that makes the upper surface of this second bronze medal block 160 and this first dielectric layer 130 at grade, as shown in Figure 7.
At this moment, with the bottom electrode of this first bronze medal block 110 with this this capacity cell of second bronze medal block, 160 common definition formation.Then, it is clean to utilize etching method that this first dielectric layer 130, this etching stopping layer 120 are removed, as shown in Figure 8.
Consult shown in Figure 9ly, earlier compliance ground forms an etching stopping layer 170, for example SiN or SiON on the bottom electrode 110 and the second bronze medal block 160.Then, one second dielectric layer 180 of comprehensive landform precedent such as silicon dioxide layer then applies photoresist layer 190 on this second dielectric layer 180, and with the lithographic definition pattern.
Then, consult Figure 10, optionally etching is removed this second dielectric layer 180, this etching stopping layer 170 and is formed and expose second opening 200 of bottom electrode 110 and 160, with the scope of the 3rd bronze medal block 210 that defines this capacity cell.For example, make with photoresist 190 to be mask, by reactive ion-etching, carry out anisotropic etching, and form this second opening 200.Remove this photoresist layer 190 afterwards again.
Then consult shown in Figure 11, utilize chemical vapor deposition process, form one the 3rd dielectric layer 220 in the surface of second dielectric layer 180, and extend to the bottom and the sidewall of second opening 200, wherein the 3rd dielectric layer 220 can be that other high-dielectric coefficient materials such as SiN or SiON constitute, and the 3rd dielectric layer 220 is in order to be used as the dielectric layer between the upper and lower electrode of metal capacitance.Afterwards, just the deposited copper metal is inserted in second opening 200 and is formed one the 3rd bronze medal block 210, in order to the top electrode 210 of being used as this metal capacitance.
At last, carry out the cmp of copper, the top electrode 210 unnecessary parts of this electric capacity are ground off, form and the 3rd dielectric layer 220 coplines, as shown in figure 12, so promptly finish a high-density laminated MIM copper capacity cell.
Therefore, compare by Fig. 1 classic flat-plate formula MIM electric capacity and Fig. 2 stack MIM of the present invention electric capacity, under equal volume, the electrode area of stack MIM electric capacity of the present invention is more a lot of greatly than the electrode area of classic flat-plate formula MIM electric capacity, and bigger capacitance can be arranged as can be known.Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, institute does to change and retouch, and all belongs within protection scope of the present invention.
Claims (9)
1. the manufacture method of a high-density laminated metal capacitor element, it is characterized in that: it comprises the following steps:
(a) provide a semiconductor-based end that is inlaid with first metal blocks, the upper surface that this first metal blocks is arranged is exposed on this base part surface;
(b) above this semiconductor-based end, form first dielectric layer comprehensively;
(c) optionally remove this first dielectric layer, and form first opening that exposes this first metal blocks, to define the scope of second metal blocks;
(d) in this first opening, insert this second metal blocks, make this first metal blocks and this second metal blocks be used as the bottom electrode of this metal capacitor element;
(e) remove remaining first dielectric layer, above the bottom electrode of this metal capacitor element and the semiconductor-based end, form second dielectric layer comprehensively;
(f) optionally remove this second dielectric layer, and form second opening that exposes this metal capacitor element lower electrode surface, this second aperture efficiency, first opening is big;
(g) bottom and the sidewall compliance at this second opening forms the 3rd dielectric layer, to be used as the dielectric layer of this capacity cell;
(h) in this second opening, insert the 3rd metal blocks, to be used as the top electrode of this capacity cell.
2. the manufacture method of high-density laminated metal capacitor element according to claim 1 is characterized in that: carrying out step (b) before, more comprising forming an etching stopping layer comprehensively above this semiconductor-based end.
3. the manufacture method of high-density laminated metal capacitor element according to claim 1, it is characterized in that: after carrying out remaining first dielectric layer of removing of step (e) and comprehensivelyly before forming second dielectric layer at the bottom electrode of this metal capacitor element and the semiconductor-based end, more be included in this semiconductor-based end and lower electrode surface compliance and form an etching stopping layer.
4. according to the manufacture method of claim 2 or 3 described high-density laminated metal capacitor elements, it is characterized in that: this etching stopping layer is deposited silicon nitride or silicon oxynitride.
5. the manufacture method of high-density laminated metal capacitor element according to claim 1 is characterized in that: this first, second or the 3rd metal blocks be deposited copper, platinum, palladium or ruthenium.
6. the manufacture method of high-density laminated metal capacitor element according to claim 1 is characterized in that: this first, second or the 3rd metal blocks be deposited copper.
7. the manufacture method of high-density laminated metal capacitor element according to claim 1, it is characterized in that: this first or second dielectric layer is a deposition of silica.
8. the manufacture method of high-density laminated metal capacitor element according to claim 1 is characterized in that: the 3rd dielectric layer in order to the dielectric layer of being used as this capacity cell is deposited silicon nitride or silicon oxynitride.
9. the manufacture method of high-density laminated metal capacitor element according to claim 1, it is characterized in that: insert the method for this second and third metal blocks, its step comprises: form this second and third metal blocks with sedimentation earlier; And utilize chemical mechanical milling method to carry out the planarization of this second and third metal blocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021035121A CN100419926C (en) | 2002-02-05 | 2002-02-05 | Manufacture of high-density laminated metal capacitor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021035121A CN100419926C (en) | 2002-02-05 | 2002-02-05 | Manufacture of high-density laminated metal capacitor element |
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| CN1437202A CN1437202A (en) | 2003-08-20 |
| CN100419926C true CN100419926C (en) | 2008-09-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021035121A Expired - Lifetime CN100419926C (en) | 2002-02-05 | 2002-02-05 | Manufacture of high-density laminated metal capacitor element |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420102B (en) * | 2011-05-26 | 2013-06-26 | 上海华力微电子有限公司 | Method used for forming MIM (metal-insulator-metal) capacitor structure and MIM capacitor |
| CN102420101B (en) * | 2011-05-26 | 2013-08-07 | 上海华力微电子有限公司 | Method for manufacturing double-layer metal-insulator-metal capacitor by using copper damascene process |
| CN111128770B (en) * | 2019-12-16 | 2021-08-24 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad and device containing aluminum pad |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314705A (en) * | 2000-03-16 | 2001-09-26 | 国际商业机器公司 | Buried metal double mosaic board capacitor |
| US6313003B1 (en) * | 2000-08-17 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company | Fabrication process for metal-insulator-metal capacitor with low gate resistance |
-
2002
- 2002-02-05 CN CNB021035121A patent/CN100419926C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314705A (en) * | 2000-03-16 | 2001-09-26 | 国际商业机器公司 | Buried metal double mosaic board capacitor |
| US6313003B1 (en) * | 2000-08-17 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company | Fabrication process for metal-insulator-metal capacitor with low gate resistance |
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| Publication number | Publication date |
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| CN1437202A (en) | 2003-08-20 |
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