CN111128729B - LDMOS device and method for prolonging service life of hot carrier injection effect of LDMOS device - Google Patents

LDMOS device and method for prolonging service life of hot carrier injection effect of LDMOS device Download PDF

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CN111128729B
CN111128729B CN201811283776.3A CN201811283776A CN111128729B CN 111128729 B CN111128729 B CN 111128729B CN 201811283776 A CN201811283776 A CN 201811283776A CN 111128729 B CN111128729 B CN 111128729B
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shallow trench
trench isolation
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isolation structure
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CN111128729A (en
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金宏峰
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Abstract

The embodiment of the invention provides a method for prolonging the service life of a hot carrier injection effect of an LDMOS device, which comprises the following steps: providing a substrate, wherein a drain electrode doping region of an LDMOS device is formed in the substrate, a shallow trench isolation structure is formed on at least one side of the drain electrode doping region parallel to the length direction of a conductive channel, and the doping type of the drain electrode doping region is a first conductive type; doping impurity ions of a second conductive type, and forming a current blocking area at least one junction of the drain doped area and the shallow trench isolation structure; the second conductivity type is opposite to the first conductivity type; and then detecting the current of the linear region of the LDMOS device, evaluating the hot carrier injection effect service life of the LDMOS device according to the degradation degree of the current of the linear region, so that the carriers can be prevented from being captured by dislocation lattices at the junction as much as possible, the influence on the degradation of the current of the linear region is reduced, and the hot carrier service life of the LDMOS device is prolonged by improving the current degradation problem of the linear region.

Description

LDMOS device and method for prolonging service life of hot carrier injection effect of LDMOS device
Technical Field
The invention relates to the technical field of LDMOS (Laterally Diffused Metal Oxide Semiconductor), in particular to an LDMOS device and a method for prolonging the service life of a Hot Carrier Injection (HCI) effect of the LDMOS device.
Background
The hot carrier injection effect of LDMOS devices such as NLDMOS devices can cause the degradation of device parameters, the reliability and the service life of the devices are greatly reduced, and the hot carrier injection effect is an important index for evaluating the service life of the LDMOS devices. At present, the service life of the hot carrier injection effect of the LDMOS device is generally evaluated according to the degradation degree of the current in the linear region of the LDMOS device. Generally, the smaller the degradation degree of the linear region current of the LDMOS device, the longer the hot carrier injection effect lifetime of the LDMOS device.
In the manufacturing process of LDMOS devices such as NLDMOS devices, SIN (silicon nitride) is used as a hard mask to perform 0.18um Shallow Trench Isolation (STI) etching, and then a furnace process for forming a linear oxide (liner oxide) is used to perform lattice repair. But a dislocated lattice is still generated at the interface between the shallow trench isolation structure and the active region. When the service life of the hot carrier injection effect is examined, after the LDMOS device is started, the current carriers (for the NLDMOS device, the extracted current carriers are electrons) extracted by the drain doped region of the LDMOS device are most likely to be captured by the dislocated crystal lattice, so that the current in the linear region is degraded and is difficult to reach a saturation state, and the service life of the hot carrier injection effect of the LDMOS device is finally seriously influenced.
Disclosure of Invention
Therefore, a method for prolonging the lifetime of the hot carrier injection effect of the LDMOS device is needed.
A method for improving the service life of a hot carrier injection effect of an LDMOS device comprises the following steps:
providing a substrate, wherein a drain electrode doping region of an LDMOS device is formed in the substrate, a shallow trench isolation structure is formed on at least one side of the drain electrode doping region parallel to the length direction of a conductive channel, and the doping type of the drain electrode doping region is a first conductive type;
doping second conductive type impurities, and forming a current blocking area at least one junction of the drain doped area and the shallow trench isolation structure; the second conductivity type is opposite to the first conductivity type.
According to the method for prolonging the service life of the hot carrier injection effect of the LDMOS device, the second conductive type impurities are doped at the junction between the drain doped region of the LDMOS device and the shallow trench isolation structure along the length direction of the conductive channel, and the second conductive type impurities are opposite to the first conductive type impurities at the junction in conductive type. The original first conductive type impurities at the junction are neutralized by the second conductive type impurities injected later, so that the on-resistance at the junction is increased. The carriers will flow to the drain doped region by selecting the region with low on-resistance, and the carrier path is changed but does not block the flow of carriers to the drain doped region. Therefore, the method can effectively avoid the carrier from being captured by the dislocated crystal lattice at the junction without adding extra complex process steps and high process cost, reduces the influence on linear region current, effectively improves the degradation problem of linear region current, and prolongs the service life of the hot carrier injection effect of the LDMOS device.
In one embodiment, a gate is formed on the substrate, a conductive channel region is formed in the substrate below the gate, a source doped region is formed in the substrate on one side of the gate, a drain doped region is formed in the substrate on the other side of the gate, a drift region is formed between the gate and the drain doped region, and the doping types of the source doped region and the drift region are both of a first conductivity type;
the shallow trench isolation structure is formed on at least one side of the drain electrode doping region and the drift region in parallel to the length direction of the conductive channel;
the flow blocking area is formed at the junction of the drain electrode doped area and the shallow groove isolation structure and extends to the junction of the drift area and the shallow groove isolation structure, and an interval is formed between the flow blocking area and the grid electrode.
In one embodiment, shallow trench isolation structures are formed around an active region composed of the source doped region, the conductive channel region, the drift region and the drain doped region, and the current blocking region further extends into the shallow trench isolation structure on one side of the drain doped region parallel to the width direction of the conductive channel.
In one embodiment, the ratio of the dimension of the drain doped region in the direction parallel to the width direction of the conductive channel to the dimension of the current blocking region in the direction parallel to the width direction of the conductive channel ranges from 100:1 to 1000:1, and the step after doping of the second conductive type impurity comprises: and forming a metal silicide blocking layer on the surface of the flow blocking area.
An LDMOS device is also proposed, comprising:
a substrate;
a gate formed on the substrate;
a conductive channel region in the substrate below the gate,
the source electrode doping area is positioned in the substrate on one side of the grid electrode;
the drain electrode doping area is positioned in the substrate on the other side of the grid electrode; at least one side of the drain electrode doped region, which is parallel to the length direction of the conductive channel, is provided with a shallow trench isolation structure, and the doping types of the source electrode doped region and the drain electrode doped region are first conductive types;
the drain electrode doping region is positioned on the shallow trench isolation structure, the drain electrode doping region is positioned on the drain electrode doping region, the shallow trench isolation structure is positioned on the drain electrode doping region, the drain electrode doping region is positioned on the shallow trench isolation structure, a gap is formed between the drain electrode doping region and the grid electrode, the drain electrode doping region is doped with second conduction type impurities, and the concentration of first conduction type impurities in the drain electrode doping region is larger than that of the first conduction type impurities in the drain electrode doping region.
In one embodiment, the LDMOS device further comprises a drift region located in the substrate between the gate and the drain doped region; the doping type of the drift region is a first conduction type;
the shallow trench isolation structure is formed on at least one side of the drain electrode doping region and the drift region in parallel to the length direction of the conductive channel;
the flow blocking region is located at the junction of the drain doped region and the shallow trench isolation structure and extends to the junction of the drift region and the shallow trench isolation structure, and the concentration of the first conductive type impurities in the drift region is greater than that of the first conductive type impurities in the flow blocking region.
In one embodiment, in a direction parallel to the width direction of the conductive channel, half of the current blocking region is formed in the shallow trench isolation structure, and the other half of the current blocking region is formed in the drain doped region and the drift region.
In one embodiment, shallow trench isolation structures are formed around an active region composed of the source doped region, the conductive channel region, the drift region and the drain doped region, and the current blocking region further extends into the shallow trench isolation structure on one side of the drain doped region parallel to the width direction of the conductive channel.
In one embodiment, the ratio of the dimension of the drain doped region in the direction parallel to the width direction of the conductive channel to the dimension of the current blocking region in the direction parallel to the width direction of the conductive channel ranges from 100:1 to 1000: 1.
In one embodiment, the size of the current blocking region in the direction parallel to the width direction of the conductive channel is 0.2 μm to 0.6 μm, the interval between the current blocking region and the gate is 0.1 μm to 0.3 μm, and the size of the current blocking region extending into the shallow trench isolation structure on one side of the drain doped region in the direction parallel to the width direction of the conductive channel is 0.1 μm to 0.3 μm.
In one embodiment, the LDMOS device further includes: and the metal silicide blocking layer is arranged on the surface of the flow blocking area.
The LDMOS device is positioned at the junction of the drain doped region and the shallow trench isolation structure along the direction of the conductive channel and serves as a current blocking region, and the current blocking region is doped with the second conductive type impurities, so that the concentration of the first conductive type impurities in the current blocking region is smaller than that of the first conductive type carriers in the drain doped region, namely the resistance at the junction is larger than that of the drain doped region. The carriers will preferentially flow to the low resistance region and the carrier path is altered but not blocked from flowing to the drain doped region. Therefore, after the LDMOS device is conducted, the carriers cannot flow to the junction, so that the carriers are prevented from being captured by dislocation lattices at the junction, the influence on linear region current is reduced, the degradation problem of the current in the linear region is effectively improved, and the service life of the hot carrier injection effect of the LDMOS device is prolonged.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for improving the lifetime of hot carrier injection effect of LDMOS devices according to an embodiment;
FIG. 2 is a schematic flow chart illustrating a method for improving the lifetime of hot carrier injection effect of LDMOS device according to another embodiment;
FIG. 3 is a schematic diagram illustrating a top view of a linear region current flow direction of an LDMOS device in one embodiment;
FIG. 4 is a schematic cross-sectional left view corresponding to FIG. 3 in one embodiment;
FIG. 5 is a schematic diagram illustrating a top view of an LDMOS device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a schematic flowchart illustrating a method for prolonging a lifetime of a hot carrier injection effect of an LDMOS device according to an embodiment of the present disclosure. The carriers comprise free electrons and holes, and for an N-type semiconductor, the carriers refer to the free electrons, and for a P-type semiconductor, the carriers refer to the holes, and the carriers can move directionally under the action of an electric field to form current. Furthermore, as can be seen from the theoretical knowledge of the current flowing direction of the semiconductor device and in conjunction with fig. 3 and 5, the direction in which the carriers move between the source and the drain in the LDMOS device is the longitudinal direction a of the conductive channel, and the direction perpendicular to the direction in which the carriers move between the source and the drain is the width direction B of the conductive channel.
Referring to fig. 1, the method for improving the lifetime of the hot carrier injection effect of the LDMOS device in the embodiment of the present application includes steps 102 and 104:
step 102, providing a substrate, wherein a drain doped region of the LDMOS device is formed in the substrate, a shallow trench isolation structure is formed on at least one side of the drain doped region parallel to the length direction a of the conductive channel, and the doping type of the drain doped region is the first conductivity type.
Specifically, the shallow trench isolation structure of the embodiment of the application can be used for isolation between different LDMOS devices, and can also be used for isolation between an LDMOS device and other types of semiconductor devices.
An active region is formed in a substrate of the LDMOS device, a grid electrode is formed on the substrate, a region where the grid electrode is overlapped with the active region is a conducting channel region, a source electrode doped region is formed in the substrate on one side of the grid electrode, a drain electrode doped region is formed in the substrate on the other side of the grid electrode, a drift region is formed in the substrate between the grid electrode and the drain electrode doped region, and the doping types of the source electrode doped region and the drift region are also first conducting type doped regions. The source doped region, the conductive channel region, the drift region and the drain doped region constitute the active region, and the shallow trench isolation structure can be formed around the active region.
Step 104, doping second conductive type impurities, and forming a current blocking area at least one junction of the drain doped area and the shallow trench isolation structure in the length direction A parallel to the conductive channel; the second conductivity type is opposite to the first conductivity type.
Specifically, the first conductive type impurity may be a heavily doped concentration of the first conductive type impurity. The second conductive type impurities may be second conductive type impurities of a heavily doped concentration. The first conductive type impurity can be an N-type impurity, the second conductive type impurity can be a P-type impurity, the LDMOS device is an NLDMOS device, and a carrier passage formed by a source electrode doped region and a drain electrode doped region in the NLDMOS device is an N-type carrier passage.
Specifically, the ratio of the dimension of the drain doped region in the direction parallel to the width direction B of the conductive channel to the dimension of the current blocking region in the direction parallel to the width direction B of the conductive channel ranges from 100:1 to 1000:1, that is, the current blocking region 312 is only formed at the edge region of the drain doped region 310, and the current path formed by the carriers is not blocked by the current blocking region 312. Particularly, for the condition that the LDMOS device is narrow in channel width, the advantage of improving the degradation problem of the current in the linear region is more obvious. In other embodiments, the dimension of the drain doped region in the direction parallel to the width direction B of the conducting channel is very large, ranging from 20 μm to 200 μm, while the dimension of the current blocking region in the direction parallel to the width direction B of the conducting channel is only 0.1 μm to 0.3 μm.
In this embodiment, a shallow trench isolation structure is formed on at least one side of the drain doped region parallel to the length direction a of the conductive channel, and after the doping of the second conductive type ions, a current blocking region is formed at least one boundary between the drain doped region and the shallow trench isolation structure. Furthermore, a shallow trench isolation structure is formed on at least one side of the drain doped region and the drift region parallel to the length direction A of the conductive channel, after the doping of the second conductive type ions is carried out, a current blocking region is formed at the junction of the drain doped region and the shallow trench isolation structure, the current blocking region also extends to the junction of the drift region and the shallow trench isolation structure, and an interval is formed between the current blocking region and the grid electrode. The size of the current blocking area in the direction A parallel to the length direction of the conducting channel is increased, more first conduction type impurities can be neutralized, the path of the carriers can be changed earlier, and the risk that the carriers are captured by dislocated lattices at the junction is further reduced. That is, the choke region may extend continuously toward the gate but not in contact therewith, and the safe distance defined between the choke region and the gate is 0.1 μm to 0.3 μm, and in other implementations, 0.2 μm.
Furthermore, the current-blocking region also extends into the shallow trench isolation structure on one side of the drain doped region parallel to the width direction B of the conductive channel. In this embodiment, the flow-blocking region can be ensured to completely cover the boundary between the drain doped region and the shallow trench isolation structure, and the risk of carrier capture by dislocation lattice at the boundary can be further reduced. Specifically, the size of the current-blocking region in the direction parallel to the width direction B of the conductive channel is 0.2 μm to 0.6 μm, the interval between the current-blocking region and the gate is 0.1 μm to 0.3 μm, and the size of the current-blocking region extending into the shallow trench isolation structure on the side of the drain doped region parallel to the width direction B of the conductive channel is 0.1 μm to 0.3 μm.
Specifically, the doping of the second conductive type impurity may be implemented by implanting the second conductive type impurity, and the boundary may be used as an implantation region, and the implantation dose of the second conductive type impurity may be 1014/cm2To 1016/cm2. In other embodiments, the second conductive type impurity is implanted at a dose of 1015/cm2. After the second conductive type impurities are injected, the first conductive type impurities at the junction can be neutralized, so that the on-resistance of the junction can be increased, and carriers can avoid the junction when flowing, namely, the carriers can avoid the edge regions of the drain doped region and the drift region when flowing.
Specifically, in the direction parallel to the width direction B of the conductive channel, half of the current blocking region is formed in the shallow trench isolation structure, and the other half of the current blocking region is formed in the drain doped region and the drift region. Because the shallow trench is generally filled with oxide, there is no first conductive type impurity, and the second conductive type impurity injected from the surface of the shallow trench isolation structure does not penetrate through the shallow trench isolation structure, the injected second conductive type impurity is only neutralized with the first conductive type impurity in the drain doped region and the drift region. The current blocking regions formed in the drain doped region and the drift region play a major role in the change of the carrier path.
In the case where a current blocking region is also present in the drift region, the dimension of the current blocking region in a direction parallel to the length direction a of the conductive channel varies with the change in the dimension of the drift region in a direction parallel to the length direction a of the conductive channel. For example, the higher the voltage, the longer the drift region, and the longer the length of the current blocking region.
In one embodiment, shallow trench isolation structures are formed on both sides of the drain doped region parallel to the length direction a of the conductive channel, and after the second conductive type doping is performed, a current blocking region is formed at the interface between the drain doped region and the adjacent shallow trench isolation structure, and the drain doped region still remains between the two current blocking regions.
According to the embodiment of the application, the current of the linear region of the LDMOS device can be detected, and then the service life of the hot carrier injection effect of the LDMOS device can be obtained according to the current of the linear region. Specifically, after the semiconductor switch is closed, the LDMOS device is turned on, stress with a certain magnitude is applied to the LDMOS device, and the change of the current of the linear region of the LDMOS device along with time is detected. If the linear region current of the LDMOS device is degraded along with time, which indicates that the current carriers extracted by the drain doped region of the LDMOS device are possibly captured by the dislocated crystal lattices at the boundary between the shallow trench isolation structure and the active region, the linear region current flowing from the source doped region to the drain doped region is difficult to reach saturation, and the service life of the hot carrier injection effect of the LDMOS device is influenced. If the current in the linear region of the LDMOS device is detected to be gradually stable along with the change of time and not to be reduced and finally to be saturated, the service life of the hot carrier injection effect of the LDMOS device obtained according to the current in the linear region is prolonged.
In one embodiment, referring to fig. 2, the step after doping the second conductive type impurity includes: in step 202, a metal silicide blocking layer is formed on the surface of the flow blocking region.
The metal silicide blocking layer can prevent the surface of the flow blocking area from forming metal silicide, so that the current carrier is blocked from flowing along the surface of the interface. Specifically, the metal silicide blocking layer covers the current blocking region, and the peripheral boundaries of the metal silicide blocking layer extend out of the current blocking region.
In one embodiment, the doped drain region has a plurality of metal holes, and cobalt (Co) silicide is formed on the silicon surface of the LDMOS device by PVD (Physical Vapor Deposition) process and RTA (Rapid Thermal Annealing) process in order to reduce the contact resistance of the metal holes. However, cobalt silicide is also formed in the region of the doped drain region except for the metal hole, including the current blocking region, which reduces the resistance of the surface of the current blocking region, and carriers are likely to flow to the surface of the current blocking region with low resistance. Therefore, the silicide blocking layer is formed on the surface of the flow blocking region, so that cobalt silicide can be prevented from being generated on the surface of the flow blocking region, and the contact resistance on the surface of the flow blocking region is increased. Thus, the carriers do not flow on the surface of the choked flow region, but flow from a region which is far away from the boundary and has low resistance. Therefore, carriers of the changed path are effectively prevented from flowing above the flow resisting region, and the risk that the carriers are captured by dislocation lattices at the junction between the shallow trench isolation structure and the active region is further reduced.
The metal silicide barrier layer may specifically be a silicon dioxide oxide layer. The silicon is widely used for semiconductor process, cobalt can easily react with silicon on the surface of a semiconductor device to form metal silicide under certain conditions, and the silicon dioxide oxide layer can prevent the metal cobalt from reacting with the silicon on the surface of the LDMOS device to form the metal silicide.
Cobalt is generally formed on the surface of the active region of the LDMOS device by sputtering, and specifically, a metal silicide barrier layer may be formed on the surface of the interface before the step of sputtering cobalt.
In an embodiment, referring to fig. 3, taking an NLDMOS device as an example, the drain doped region 310 is an N-type (N +) region with a heavy doping concentration, a P-type (P +) impurity with a heavy doping concentration is injected at a boundary between the drain doped region 310 and a shallow trench isolation structure (not labeled in fig. 3) in a direction parallel to a length direction a of a conductive channel to form a current blocking region 312 in fig. 3, the current blocking region 312 further extends to a boundary between the drift region 311 and the shallow trench isolation structure in the direction parallel to the length direction a of the conductive channel, and a gap is formed between the current blocking region 312 and the gate 313, so that the current blocking region and the gate 313 are not in direct contact. The current flowing through the drift region 311 bypasses the current blocking region 312 and flows along the lower resistance region to the drain doped region 310. The active region to the right of the dotted line in fig. 3 can be regarded as the drain doped region 310, the region from the left side of the dotted line to the gate 313 is the drift region 311, and the drift region 311 is an N + -type doped region. The length of the space between the current blocking region 312 and the gate 313 may be 0.2 μm.
Fig. 4 is a schematic structural view corresponding to the left-side cross section of fig. 3, with a section line at the dashed line in fig. 3. The arrows in fig. 4 indicate the current flowing from the source to the drain, and the current near the boundary changes its path to the choke region 312 and concentrates in the middle. In the actual implantation, a heavily doped P-type (P +) impurity is also implanted into the STI, but is not shown in fig. 4.
As shown in fig. 3 and 4, the silicide blocking layer 315 is located above the choke region 312 doped with P + impurities, and the silicide blocking layer 315 completely covers the choke region 312. In order to visually represent the structure of the choked region 312 doped with P + type impurities, the silicide blocking layer 315 shown in fig. 3 is a perspective structure.
According to the method for prolonging the service life of the hot carrier injection effect of the LDMOS device, the second conductive type impurities are doped at the junction between the drain doped region of the LDMOS device and the shallow trench isolation structure along the length direction of the conductive channel, and the second conductive type impurities are opposite to the first conductive type impurities at the junction in conductive type. The original first conductive type impurities at the junction are neutralized by the second conductive type impurities injected later, so that the on-resistance at the junction is increased. The carriers will flow to the drain doped region in a region with a low on-resistance, and the carrier path is altered but does not block the flow of carriers to the drain doped region. Therefore, the method can effectively avoid the carrier from being captured by the dislocated crystal lattice at the junction without adding extra complex process steps and high process cost, reduces the influence on linear region current, effectively improves the degradation problem of linear region current, and prolongs the service life of the hot carrier injection effect of the LDMOS device.
For the condition that the channel width of the LDMOS device is narrow, even if a part of a current path in the middle area of the current-blocking area is sacrificed, due to the existence of the current-blocking area, a current carrier can change a path, the phenomenon that the current carrier is captured by dislocated crystal lattices is avoided, and the degradation problem of current in the linear area can be effectively improved.
The embodiment of the application also provides the LDMOS device. Referring to fig. 5, the LDMOS device includes: a substrate (not labeled in fig. 5), a gate 313, a current blocking region 312, a conductive channel region (hidden by the gate in fig. 5, not shown) in the substrate below the gate 313, a source doped region 317 in the substrate on one side of the gate 313, and a drain doped region 310 in the substrate on the other side of the gate 313. The doping types of the source doped region 317 and the drain doped region 310 are both of the first conductivity type. The current-blocking region 312 is located at least one boundary between the drain doped region 310 and the shallow trench isolation structure 314 in the direction parallel to the length direction a of the conductive channel, the current-blocking region 312 is not in contact with the gate 313, a gap is formed between the current-blocking region 312 and the gate 313, and the current-blocking region 312 is doped with the second conductive type impurity. Because the second conductive type impurities are injected into the boundary to neutralize the first conductive type impurities at the boundary, the concentration of the first conductive type impurities in the drain doped region 310 is greater than that of the first conductive type impurities in the current blocking region 315, so that the on-resistance of the drain doped region 310 is smaller than that of the current blocking region 312, and carriers can preferentially flow to a region with small on-resistance, thereby realizing the change of the path of the carriers.
Specifically, the first conductive type impurity is an N-type impurity, and the second conductive type impurity is a P-type impurity.
Specifically, the ratio of the dimension of the drain doped region 310 in the direction parallel to the width direction B of the conductive channel to the dimension of the current blocking region 312 in the direction parallel to the width direction B of the conductive channel is in the range of 100:1 to 1000:1, that is, the current blocking region 312 is only formed in the edge region of the drain doped region 310, the current path formed by carriers is not blocked by the current blocking region 312, and particularly for the case of the LDMOS device with a narrow channel width, the advantage of improving the degradation problem of the current in the linear region is more obvious. In other embodiments, the dimension of the drain doped region in the direction parallel to the width direction B of the conducting channel is very large, ranging from 20 μm to 200 μm, while the dimension of the current blocking region in the direction parallel to the width direction B of the conducting channel is only 0.2 μm to 0.6 μm.
The interval between the current-blocking region and the grid is 0.1-0.3 μm, and the safety distance between the current-blocking region and the grid is 0.1-0.3 μm. In other embodiments, the spacing between the choke region 312 and the gate 313 may be 0.2 μm.
In other embodiments, referring to fig. 5, the LDMOS device further includes a drift region 311. The drift region 311 is located in the substrate between the gate 313 and the drain doped region 310, and the doping types of the drift region 311 and the drain doped region 310 are the same as the first conductivity type. At least one side of the drain doped region 310 and the drift region 311 parallel to the length direction a of the conductive channel is provided with a shallow trench isolation structure 314. The current blocking region 312 is located at a boundary between the drain doped region 310 and the shallow trench isolation structure 314, and extends to a boundary between the drift region 311 and the shallow trench isolation structure 314, and there is a gap between the current blocking region 312 and the gate 313, so that direct contact is not caused. Since the impurities of the first conductive type originally existing at the boundary where the current blocking region 312 is formed are neutralized by the impurities of the second conductive type which are subsequently implanted. Therefore, the concentration of the first conductive type impurity in the drain doped region 310 and the drift region 311 is greater than the concentration of the first conductive type impurity in the current blocking region 312, that is, the on-resistance of the drain doped region 310 and the drift region 311 is less than the on-resistance of the current blocking region 312, and the carriers avoid the current blocking region 312, and preferentially select the region with small on-resistance to change the path of the carriers.
The source doped region 317, the conductive channel region, the drift region 311, and the drain doped region 310, and the active region 316. The active region 316 is a complete rectangular or square area, and the portion of the rectangular or square area coinciding with the gate 313 is the conductive channel region. Shallow trench isolation structures 314 are formed around the active regions 316.
In other embodiments, the flow-blocking region 312 also extends into the shallow trench isolation structure 314 on a side of the drain doped region 310 parallel to the width direction B of the conductive channel. Specifically, the size of the current blocking region 312 in the direction parallel to the width direction B of the conductive channel is 0.2 μm to 0.6 μm, the interval between the current blocking region 312 and the gate 313 is 0.1 μm to 0.3 μm, and the size of the current blocking region 312 extending into the shallow trench isolation structure 314 on the side of the drain doped region 310 parallel to the width direction B of the conductive channel is 0.1 μm to 0.3 μm.
Specifically, in the direction parallel to the width direction B of the conductive channel, half of the blocking area is formed in the shallow trench isolation structure 314, and the other half of the blocking area is formed in the drain doped region 310 and the drift region 311. Because oxide is generally filled in the shallow trench, the shallow trench is not provided with first conductive type impurities, and second conductive type impurities injected from the surface of the shallow trench isolation structure cannot penetrate through the shallow trench isolation structure, the injected second conductive type impurities are only neutralized with the first conductive type impurities in the drain doped region and the drift region. The current blocking regions formed in the drain doped region and the drift region play a major role in the change of the carrier path.
In one embodiment, referring to fig. 3, fig. 4 and fig. 5, the LDMOS device further includes a metal silicide blocking layer 315 disposed on the surface of the current blocking region 312. Referring to fig. 3 and 5, the metal silicide blocking layer 315 completely covers the surface of the choke region 312 for preventing the formation of metal silicide on the surface of the choke region 312. The peripheral boundary of the metal silicide blocking layer 315 extends beyond the flow blocking region 312.
The formation of the metal silicide blocking layer 315 on the surface of the choke area 312 can prevent the generation of cobalt silicide on the surface of the choke area 312, and increase the contact resistance on the surface of the choke area 312. Thus, carriers do not flow at the surface of the choke region 312, but rather flow from a region away from the surface of the choke region 312 and having low resistance. Therefore, carriers of the changed path are effectively prevented from flowing over the flow blocking region 312, and the risk that the carriers are captured by dislocation lattices at the boundary between the shallow trench isolation structure and the active region is further reduced.
In one embodiment, referring to fig. 4 and fig. 5, shallow trench isolation structures 314 are disposed on both sides of the doped drain region 310 parallel to the length direction of the conductive channel, and a current blocking region 312 is formed at the boundary between the doped drain region 310 and the shallow trench isolation structures 314 on both sides. The concentration of the first conductive-type impurities of the drain doping regions 310 between the current blocking regions 312 is greater than the concentration of the first conductive-type impurities in the current blocking regions 312. During the operation of the device, carriers flow through the middle drain doped region 310 by bypassing the current blocking region 312, i.e., the path of the carriers is changed but the carriers are not blocked from flowing to the drain doped region 310.
In the LDMOS device, a current blocking region 312 is disposed at the boundary between the drain doped region 310 and the shallow trench isolation structure 314. The current blocking region 312 is doped with the second conductive type impurities, and the concentration of the first conductive type impurities in the current blocking region 312 is less than the concentration of the first conductive type carriers in the drain doped region 310, so that the resistance of the current blocking region 312 is greater than the resistance of the drain doped region 310. Carriers will preferentially flow to the low resistance region and the carrier path is altered but not blocked from flowing to the drain doped region 310. Therefore, after the LDMOS device is conducted, the current carrier cannot flow to the junction of the drain electrode doped region and the shallow groove isolation structure, so that the current carrier can be prevented from being captured by dislocation lattices at the junction, the influence on linear region current is reduced, the degradation problem of linear region current is effectively improved, and the service life of the hot carrier injection effect of the LDMOS device is prolonged.
For the situation that the channel width of the LDMOS device is narrow, even if a part of the current path in the middle region of the current blocking region 312 is sacrificed, due to the existence of the current blocking region 312, the path of the carriers can be changed, so as to avoid being captured by dislocation lattices, and thus, the degradation problem of the current in the linear region can be still effectively improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (11)

1. A method for prolonging the service life of a hot carrier injection effect of an LDMOS device is characterized by comprising the following steps:
providing a substrate, wherein a drain electrode doping region of the LDMOS device is formed in the substrate, a shallow trench isolation structure is formed on at least one side of the drain electrode doping region parallel to the length direction of a conductive channel, and the doping type of the drain electrode doping region is a first conductive type;
doping second conductive type impurities, and forming a current blocking area at least one junction of the drain doped area and the shallow trench isolation structure; the second conductivity type is opposite to the first conductivity type;
the grid electrode is formed on the substrate, the source electrode doped region is formed in the substrate on one side of the grid electrode, the drain electrode doped region is formed in the substrate on the other side of the grid electrode, an interval is formed between the current blocking region and the grid electrode, and the current blocking region is only formed in the edge region of the drain electrode doped region.
2. The method of claim 1, wherein a conductive channel region is formed in the substrate below the gate, a drift region is formed in the substrate between the gate and the drain doped region, and the source doped region and the drift region are both of a first conductivity type;
the shallow trench isolation structure is formed on at least one side of the drain electrode doping region and the drift region in parallel to the length direction of the conductive channel;
the flow blocking area is formed at the junction of the drain electrode doped area and the shallow trench isolation structure and extends to the junction of the drift area and the shallow trench isolation structure.
3. The method of claim 2, wherein the shallow trench isolation structures are formed around an active region composed of the source doped region, the conductive channel region, the drift region and the drain doped region, and the current blocking region further extends into the shallow trench isolation structure on one side of the drain doped region parallel to a width direction of the conductive channel.
4. The method of claim 3, wherein the ratio of the dimension of the drain doped region in the direction parallel to the width direction of the conductive channel to the dimension of the current blocking region in the direction parallel to the width direction of the conductive channel ranges from 100:1 to 1000:1, and the step after performing the doping of the second conductive type impurity comprises: and forming a metal silicide blocking layer on the surface of the flow blocking area.
5. An LDMOS device, comprising:
a substrate;
a gate formed on the substrate;
a conductive channel region in the substrate below the gate;
the source electrode doping area is positioned in the substrate on one side of the grid electrode;
the drain electrode doping area is positioned in the substrate on the other side of the grid electrode; at least one side of the drain electrode doped region, which is parallel to the length direction of the conductive channel, is provided with a shallow trench isolation structure, and the doping types of the source electrode doped region and the drain electrode doped region are first conductive types;
the drain electrode doping region is positioned on at least one junction of the shallow trench isolation structure and the drain electrode doping region, a gap is formed between the drain electrode doping region and the shallow trench isolation structure, the drain electrode doping region is doped with a second conductive type impurity, and the concentration of the first conductive type impurity in the drain electrode doping region is larger than that of the first conductive type impurity in the drain electrode doping region;
wherein, the current-blocking region is formed only at the edge region of the drain doped region.
6. The LDMOS device of claim 5, further comprising a drift region in the substrate between the gate and the drain doped region; the doping type of the drift region is a first conduction type;
the shallow trench isolation structure is formed on at least one side of the drain electrode doping region and the drift region in parallel to the length direction of the conductive channel;
the flow blocking region is located at the junction of the drain doped region and the shallow trench isolation structure and extends to the junction of the drift region and the shallow trench isolation structure, and the concentration of the first conductive type impurities in the drift region is greater than that of the first conductive type impurities in the flow blocking region.
7. The LDMOS device of claim 6, wherein half of the block region is formed in the shallow trench isolation structure and the other half of the block region is formed in the drain doping region and the drift region in a direction parallel to a width of the conductive channel.
8. The LDMOS device of claim 6 or 7, wherein a shallow trench isolation structure is formed around an active region formed by the source doped region, the conduction channel region, the drift region and the drain doped region, and the current blocking region further extends into the shallow trench isolation structure on one side of the drain doped region parallel to a width direction of the conduction channel.
9. The LDMOS device of claim 8, wherein a ratio of a dimension of the drain doped region in a direction parallel to a width direction of the conductive channel to a dimension of the current blocking region in the direction parallel to the width direction of the conductive channel ranges from 100:1 to 1000: 1.
10. The LDMOS device of claim 8, wherein a dimension of the current blocking region in a direction parallel to a width direction of the conductive channel is 0.2 μm to 0.6 μm, a spacing between the current blocking region and the gate is 0.1 μm to 0.3 μm, and a dimension of the current blocking region extending into the shallow trench isolation structure of the side of the drain doping region parallel to the width direction of the conductive channel is 0.1 μm to 0.3 μm.
11. The LDMOS device set forth in claim 8 further comprising: and the metal silicide blocking layer is arranged on the surface of the flow blocking area.
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