WO2020088591A1

WO2020088591A1 - Ldmos device and method for prolonging service life of hot carrier injection effect thereof

Info

Publication number: WO2020088591A1
Application number: PCT/CN2019/114700
Authority: WO
Inventors: 金宏峰
Original assignee: 无锡华润上华科技有限公司
Priority date: 2018-10-31
Filing date: 2019-10-31
Publication date: 2020-05-07
Also published as: CN111128729A; CN111128729B

Abstract

An LDMOS device and a method for prolonging the service life of hot carrier injection effect thereof. The method comprises: providing a substrate, a drain-doped region of the LDMOS device being formed in the substrate, at least one side of the drain-doped region parallel to a length direction of a conductive channel forming a shallow trench isolation structure, and the doped type of the drain-doped region being a first conduction type; and performing doping of impurity ions of a second conduction type, a flow blocking region being formed in at least one junction of the drain-doped region and the shallow trench isolation structure.

Description

LDMOS device and method for increasing its lifetime of hot carrier injection effect

Technical field

The invention relates to the technical field of LDMOS (Laterally Diffused Metal Oxide Semiconductor), in particular to an LDMOS device and a method for improving the life of its hot carrier injection (HCI).

Background technique

The hot carrier injection effect of LDMOS devices such as NLDMOS devices will cause the degradation of device parameters, which greatly reduces the reliability and working life of the device. Therefore, the hot carrier injection effect is an important indicator for evaluating the working life of LDMOS devices. Currently, the lifetime of the hot carrier injection effect of the LDMOS device is usually evaluated based on the degradation of the linear region current of the LDMOS device. Generally speaking, the lower the linear current degradation of the LDMOS device, the longer the lifetime of the hot carrier injection effect of the LDMOS device.

In the manufacturing process of LDMOS devices such as NLDMOS devices, 0.18um shallow trench isolation (STI) etching is performed using SIN (silicon nitride) as a hard mask, and then a furnace for forming a linear oxide layer is used Control process for lattice repair. However, at the junction between the shallow trench isolation structure and the active region, a misaligned lattice will still be generated. When assessing the lifetime of the hot carrier injection effect, after the LDMOS device is turned on, the carriers extracted by the drain doped region of the LDMOS device (for NLDMOS devices, the extracted carriers are electrons) are very likely to be The misaligned lattice capture makes the current in the linear region degrade and it is difficult to reach the saturation state, which ultimately seriously affects the life of the hot carrier injection effect of the LDMOS device.

Summary of the invention

Based on this, it is necessary to provide an LDMOS device and a method to increase the lifetime of its hot carrier injection effect

A method for improving the lifetime of the hot carrier injection effect of an LDMOS device, the method comprising:

A substrate is provided in which a drain doped region of the LDMOS device is formed, and a shallow trench isolation structure is formed on at least one side of the drain doped region parallel to the length direction of the conductive channel, the drain The doping type of the polar doped region is the first conductivity type;

Doping impurities of the second conductivity type to form a current blocking region at at least one boundary between the drain doped region and the shallow trench isolation structure; the second conductivity type is opposite to the first conductivity type.

An LDMOS device, including:

Substrate

The gate is formed on the substrate;

A conductive channel region, located in the substrate below the gate,

A source doped region located in the substrate on one side of the gate;

A drain doped region is located in the substrate on the other side of the gate; the drain doped region is provided with a shallow trench isolation structure on at least one side parallel to the length direction of the conductive channel, and the source The doping types of the pole doped region and the drain doped region are the first conductivity type;

The current blocking region is located at at least one junction between the drain doped region and the shallow trench isolation structure, there is a gap between the current blocking region and the gate, and the current blocking region is doped with a second For conductivity type impurities, the concentration of the first conductivity type impurity in the drain doped region is greater than the concentration of the first conductivity type impurity in the current blocking region.

The details of one or more embodiments of the application are set forth in the drawings and description below. Other features, objects, and advantages of this application will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION

For a better description and description of the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode currently understood of these inventions.

FIG. 1 is a schematic flowchart of a method for improving the lifetime of the hot carrier injection effect of an LDMOS device in an embodiment;

FIG. 2 is a schematic flowchart of a method for improving the life of the hot carrier injection effect of an LDMOS device in another embodiment;

FIG. 3 is a schematic top view illustrating the current flow direction of the linear region of the LDMOS device in an embodiment;

4 is a schematic cross-sectional view of the left side corresponding to FIG. 3 in an embodiment;

FIG. 5 is a schematic top view structure of an LDMOS device in an embodiment.

detailed description

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not intended to limit the present invention.

FIG. 1 is a schematic flowchart of a method for improving the life of the hot carrier injection effect of an LDMOS device in an embodiment of the present application. Carriers include free electrons and holes. For N-type semiconductors, carriers refer to free electrons. For P-type semiconductors, carriers refer to holes. They can make directional movement under the action of an electric field to form a current. In addition, according to the theoretical knowledge of the current flow direction of the semiconductor device in conjunction with FIGS. 3 and 5, it can be seen that the direction in which the carrier moves between the source and the drain in the LDMOS device is the length direction A of the conductive channel The direction perpendicular to the movement direction between the source and the drain is the width direction B of the conductive channel.

Referring to FIG. 1, the method for improving the lifetime of the hot carrier injection effect of the LDMOS device in the embodiment of the present application includes steps 102 and 104:

Step 102, providing a substrate in which a drain doped region of an LDMOS device is formed, and a shallow trench isolation structure is formed on at least one side of the drain doped region parallel to the length direction A of the conductive channel, and the drain is doped The doping type of the region is the first conductivity type.

Specifically, the shallow trench isolation structure of the embodiments of the present application can be used for isolation between different LDMOS devices, and can also be used for isolation between LDMOS devices and other types of semiconductor devices.

An active region is formed in the substrate of the LDMOS device, a gate is formed on the substrate, a region where the gate overlaps the active region is a conductive channel region, and a source doped region is formed in the substrate on one side of the gate, A drain doped region is formed in the substrate on the other side of the gate, and a drift region is formed in the substrate between the gate and the drain doped region. The doping types of the source doped region and the drift region are also the first A conductivity type doped region. The source doped region, the conductive channel region, the drift region, and the drain doped region constitute the active region, and a shallow trench isolation structure may be formed around the active region.

Step 104: Doping impurities of the second conductivity type to form a current blocking region at at least one junction between the drain doped region and the shallow trench isolation structure parallel to the length direction A of the conductive channel; the second conductivity type is The first conductivity type is opposite.

Specifically, the first conductivity type impurities may be heavily doped with the first conductivity type impurities. The second conductivity type impurity may be a second conductivity type impurity with a heavy doping concentration. The first conductivity type impurity may be an N-type impurity, and the second conductivity type impurity may be a P-type impurity. The LDMOS device is an NLDMOS device. The carrier path formed by the source doped region and the drain doped region in the NLDMOS device is N-type carrier path.

Specifically, the ratio of the size of the drain doped region parallel to the width direction B of the conductive channel and the size of the blocking region parallel to the width direction B of the conductive channel ranges from 100: 1 to 1000: 1, That is, the current blocking region 312 is only formed in the edge region of the drain doped region 310, and the current path formed by carriers will not be blocked by the current blocking region 312. Especially for the case where the channel width of the LDMOS device is narrow, the advantage of improving the degradation of the current in the linear region is more obvious. In other embodiments, the size of the drain doped region parallel to the width direction B of the conductive channel is 20 μm to 200 μm, while the size of the blocking region parallel to the width direction B of the conductive channel is only It is 0.1 μm to 0.3 μm.

In this embodiment, a shallow trench isolation structure is formed on at least one side of the drain doped region parallel to the longitudinal direction A of the conductive channel. After ion doping of the second conductivity type, the drain doped region is isolated from the shallow trench isolation structure At least one junction forms a choke zone. Further, a shallow trench isolation structure is formed on at least one side of the drain doped region and the drift region parallel to the length direction A of the conductive channel. After ion doping of the second conductivity type is performed, in the drain doped region A junction region is formed at the junction with the shallow trench isolation structure, and the junction region also extends to the junction between the drift region and the shallow trench isolation structure, and there is a gap between the junction region and the gate. The increase in the size of the blocking region in the direction A parallel to the length of the conductive channel will neutralize more impurities of the first conductivity type, and the carrier can change the path earlier, further reducing the misalignment of the carrier by the junction The risk of lattice capture. That is, the choke area can continue to extend toward the gate, but cannot be in contact with the gate. The safety distance defined between the choke area and the gate is 0.1 μm to 0.3 μm. In other implementations, the safety distance is 0.2 μm .

Furthermore, the current blocking region extends into the shallow trench isolation structure on the side of the drain doped region parallel to the width direction B of the conductive channel. This embodiment can ensure that the current blocking region completely covers the boundary between the drain doped region and the shallow trench isolation structure, and can further reduce the risk of carriers being trapped by the dislocation lattice at the boundary. Specifically, the size of the blocking region in the width direction B parallel to the conductive channel is 0.2 μm to 0.6 μm, the interval between the blocking region and the gate is 0.1 μm to 0.3 μm, and the blocking region extends to The size of the shallow trench isolation structure on the side of the drain doped region parallel to the width direction B of the conductive channel is 0.1 μm to 0.3 μm.

Specifically, the doping of the second conductivity type impurities can be achieved by implanting the second conductivity type impurities, and the junction is used as the implantation region, and the implantation dose of the second conductivity type impurities may be 10 ¹⁴ / cm ² to 10 ¹⁶ / cm ² . In other embodiments, the implantation dose of the second conductivity type impurity is 10 ¹⁵ / cm ² . After the impurities of the second conductivity type are injected, the impurities of the first conductivity type will be neutralized at the junction, which can increase the on-resistance of the junction and allow carriers to avoid the junction when flowing, that is, to make Carriers avoid the edge regions of the drain doped region and the drift region when flowing.

Specifically, in the width direction B parallel to the conductive channel, half of the current blocking region is formed in the shallow trench isolation structure, and the other half of the current blocking region is formed in the drain doped region and the drift region. Because the shallow trench is generally filled with oxide, there is no impurity of the first conductivity type, and the impurity of the second conductivity type implanted from the surface of the shallow trench isolation structure does not penetrate the shallow trench isolation structure, then the implanted second trench The conductivity type impurities are only neutralized with the first conductivity type impurities in the drain doped region and the drift region. Therefore, the current blocking region formed in the drain doped region and the drift region plays a major role in changing the carrier path.

For the case where there is also a blocking region in the drift region, the size of the blocking region in the direction A parallel to the length of the conductive channel will change as the size of the drift region in the direction A parallel to the length of the conductive channel changes. For example, the higher the voltage, the longer the drift region, and the length of the blocking region will also become longer.

In one embodiment, a shallow trench isolation structure is formed on both sides of the drain doped region parallel to the length direction A of the conductive channel. After the second conductivity type doping is performed, the drain doped region is adjacent to the drain doped region. The two junctions of the shallow trench isolation structure will form a blocking region, and the drain doped region remains between the two blocking regions.

In the embodiment of the present application, the current in the linear region of the LDMOS device can also be detected, and then the life of the hot carrier injection effect of the LDMOS device can be obtained according to the current in the linear region. Specifically, after the semiconductor switch is closed, the LDMOS device is turned on, a certain amount of stress is applied to the LDMOS device, and the change of the current in the linear region of the LDMOS device with time is detected. If it is detected that the current in the linear region of the LDMOS device is degraded over time, it means that the carriers extracted by the drain doped region of the LDMOS device may be misaligned at the junction between the shallow trench isolation structure and the active region. If it is trapped, then the linear region current flowing from the source doped region to the drain doped region is difficult to reach saturation, which will affect the hot carrier injection effect life of the LDMOS device. If it is detected that the current in the linear region of the LDMOS device changes gradually with time, no longer becomes smaller, and finally reaches saturation, the hot carrier injection effect life of the LDMOS device is also improved according to the current in the linear region.

In one of the embodiments, please refer to FIG. 2, the step after doping the second conductivity type impurities includes: Step 202, forming a silicided metal barrier layer on the surface of the current blocking region.

The silicided metal barrier layer can prevent the formation of silicided metal on the surface of the blocking region, thereby blocking the flow of carriers along the surface of the junction. Specifically, the silicided metal barrier layer covers the flow blocking area, and the surrounding boundaries of the silicided metal barrier layer all extend beyond the flow blocking area.

In a specific embodiment, there are several metal holes in the drain doped region. Cobalt (Co) silicide is obtained by PVD (Physical Vapor Deposition) process and RTA (Rapid Thermal Thermal Annealing). The process is generated on the silicon surface of the LDMOS device in order to reduce the contact resistance of these metal holes. However, cobalt silicide will also be formed in the drain doped region except the metal hole, including the current blocking region, which will reduce the resistance of the surface of the current blocking region, and the carriers may flow to the low resistance current blocking region surface. Therefore, forming a silicided metal barrier layer on the surface of the flow blocking area can prevent the generation of cobalt silicide on the surface of the flow blocking area and increase the contact resistance of the surface of the flow blocking area. In this way, the carriers will not circulate on the surface of the choke area, but circulate from the area with low resistance far from the junction. Thereby, the carriers whose paths are changed are effectively prevented from flowing above the blocking region, and the risk of carriers being trapped by the misaligned lattice at the boundary between the shallow trench isolation structure and the active region is further reduced.

The silicided metal barrier layer may specifically be a silicon oxide oxide layer. Silicon is widely used in semiconductor processes. Under certain conditions, cobalt can easily react with silicon on the surface of semiconductor devices to form metal silicides. The silicon oxide layer can prevent metal cobalt from reacting with silicon on the surface of LDMOS devices to form metal silicides.

Cobalt is generally formed on the surface of the active region of the LDMOS device by sputtering. Specifically, a silicided metal barrier layer can be formed on the surface of the boundary before the step of sputtering cobalt.

In a specific embodiment, please refer to FIG. 3, taking an NLDMOS device as an example, the drain doped region 310 is a heavily doped N-type (abbreviated as N +) region, and the drain doped region 310 and the shallow trench isolation structure (Unmarked in FIG. 3) P-type impurities (referred to as P +) are heavily implanted at the junction between the parallel conductive channels in the length direction A to form the blocking region 312 in FIG. 3, the blocking region 312 It also extends to the junction between the drift region 311 and the shallow trench isolation structure in the parallel conductive channel length direction A, and there is a gap between the current blocking region 312 and the gate 313 and will not directly contact. The circuit flowing through the drift region 311 bypasses the current blocking region 312 and flows to the drain doped region 310 along the region with lower resistance. The active region region on the right side of the dotted line in FIG. 3 can be regarded as the drain doped region 310, and the region from the left side of the dotted line to the gate 313 is the drift region 311, and the drift region 311 is an N + type doped region. The interval length between the blocking region 312 and the gate 313 may be 0.2 μm.

FIG. 4 is a schematic structural diagram corresponding to the left-side cross section of FIG. 3, the cross-sectional line is located at the dotted line in FIG. 3. The arrow in FIG. 4 indicates the current flowing from the source to the drain. When the current near the junction reaches the blocking region 312, the path changes to concentrate in the middle. In actual implantation, P-type (P +) impurities with heavy doping concentration will also be implanted into the STI, but they are not shown in FIG. 4.

As shown in FIGS. 3 and 4, the silicide blocking layer 315 is located above the blocking region 312 doped with P + impurities, and the silicide blocking layer 315 completely covers the blocking region 312. In order to visualize the structure of the current blocking region 312 doped with P + -type impurities, the silicide blocking layer 315 shown in FIG. 3 is a perspective structure.

The method for improving the lifetime of the hot carrier injection effect of the LDMOS device according to the embodiment of the present application is doped at the junction along the length of the conductive channel between the drain doped region of the LDMOS device and the shallow trench isolation structure The second conductivity type impurity is opposite to the conductivity type of the first conductivity type impurity at the boundary. The original impurities of the first conductivity type at the junction are neutralized by the impurities of the second conductivity type injected afterwards, thereby increasing the on-resistance at the junction. The carrier will select the region with a low on-resistance to flow to the drain doped region. The carrier path is changed but does not block the flow of carriers to the drain doped region. Therefore, the method of the present application does not need to add additional complicated process steps and high process cost, which can effectively avoid carriers from being trapped by the lattice dislocation at the junction, reduce the impact on the current in the linear region, and effectively improve the linear region The problem of current degradation improves the lifetime of the hot carrier injection effect of LDMOS devices.

For the case where the channel width of the LDMOS device is narrow, even if part of the current path in the middle region of the choke region is sacrificed, due to the existence of the choke region, the carrier will change the path and avoid being trapped by the misaligned lattice, which is still effective Improve the linear current degradation problem.

An embodiment of the present application further proposes an LDMOS device. Referring to FIG. 5, the LDMOS device includes: a substrate (substrate not marked in FIG. 5), a gate 313, a current blocking region 312, a conductive channel region (shielded by the gate in FIG. 5, not shown) located on the gate In the substrate below the electrode 313, the source doped region 317 is located in the substrate on one side of the gate 313, and the drain doped region 310 is located in the substrate on the other side of the gate 313. The doping types of the source doped region 317 and the drain doped region 310 are both the first conductivity type. The current blocking region 312 is located at at least one junction in the parallel conductive channel length direction A between the drain doped region 310 and the shallow trench isolation structure 314, the current blocking region 312 is not in contact with the gate 313, and the current blocking region There is a gap between 312 and the gate 313, and the blocking region 312 is doped with impurities of the second conductivity type. Because the second conductivity type impurities are implanted at the junction and neutralize the first conductivity type impurities at the junction, the concentration of the first conductivity type impurity in the drain doping region 310 is greater than that of the first conductivity type impurity in the blocking region 315 Concentration, the on-resistance of the drain doped region 310 is smaller than the on-resistance of the blocking region 312, and the carrier will preferentially select the region with a small on-resistance to change the path of the carrier.

Specifically, the first conductivity type impurities are N-type impurities, and the second conductivity type impurities are P-type impurities.

Specifically, the ratio of the size of the drain doped region 310 parallel to the width direction B of the conductive channel and the size of the blocking region 312 parallel to the width direction B of the conductive channel ranges from 100: 1 to 1000: 1. That is, the current blocking region 312 is only formed in the edge region of the drain doped region 310, and the current path formed by carriers will not be blocked by the current blocking region 312, especially for the case where the channel width of the LDMOS device is narrow, The advantage of improving the problem of linear current degradation is more obvious. In other embodiments, the size of the drain doped region parallel to the width direction B of the conductive channel is 20 μm to 200 μm, while the size of the blocking region parallel to the width direction B of the conductive channel is only It is 0.2 μm to 0.6 μm.

The interval between the blocking area and the gate is 0.1 μm to 0.3 μm, and the safety distance between the blocking area and the gate is 0.1 μm to 0.3 μm. In other embodiments, the spacing between the blocking region 312 and the gate 313 may be 0.2 μm.

In other embodiments, please refer to FIG. 5, the LDMOS device further includes a drift region 311. The drift region 311 is located in the substrate between the gate 313 and the drain doped region 310. The doping types of the drift region 311 and the drain doped region 310 are both the first conductivity type. A shallow trench isolation structure 314 is provided on at least one side of the drain doped region 310 and the drift region 311 parallel to the length direction A of the conductive channel. The blocking region 312 is located at the junction between the drain doped region 310 and the shallow trench isolation structure 314, and extends to the junction between the drift region 311 and the shallow trench isolation structure 314, and the blocking region 312 is There is a gap between the gate electrodes 313, and there is no direct contact. The original impurities of the first conductivity type at the junction forming the blocking region 312 are neutralized by the impurities of the second conductivity type that are subsequently implanted. Therefore, the concentration of the first conductivity type impurity in the drain doped region 310 and the drift region 311 will be greater than the concentration of the first conductivity type impurity in the blocking region 312, that is, the on resistance of the drain doped region 310 and the drift region 311 Less than the on-resistance of the blocking region 312, the carrier will avoid the blocking region 312, and the region with a small on-resistance is preferentially selected to realize the change of the carrier path.

The source doped region 317, the conductive channel region, the drift region 311, and the drain doped region 310 constitute an active region 316. The active region 316 is a complete rectangular or square region, and the portion of the rectangular or square region overlapping with the gate 313 is the conductive channel region. Shallow trench isolation structures 314 are formed around the active region 316.

In other embodiments, the blocking region 312 also extends into the shallow trench isolation structure 314 on the side of the drain doped region 310 parallel to the width direction B of the conductive channel. Specifically, the size of the blocking region 312 in the width direction B parallel to the conductive channel is 0.2 μm to 0.6 μm, the interval between the blocking region 312 and the gate 313 is 0.1 μm to 0.3 μm, and the blocking region 312 The size of the shallow trench isolation structure 314 extending to a side of the drain doped region 310 parallel to the width direction B of the conductive channel is 0.1 μm to 0.3 μm.

Specifically, in the direction B parallel to the width of the conductive channel, half of the current blocking region is formed in the shallow trench isolation structure 314, and the other half of the current blocking region is formed in the drain doped region 310 and the drift region 311. Since the shallow trench is generally filled with oxide, there is no impurity of the first conductivity type in the shallow trench, and the impurity of the second conductivity type implanted from the surface of the shallow trench isolation structure does not penetrate the shallow trench isolation structure, then The implanted second conductivity type impurities are only neutralized with the first conductivity type impurities in the drain doped region and the drift region. Therefore, the current blocking region formed in the drain doped region and the drift region plays a major role in changing the carrier path.

In one embodiment, please refer to FIGS. 3, 4 and 5. The LDMOS device further includes a silicided metal barrier layer 315 provided on the surface of the current blocking region 312. Referring to FIGS. 3 and 5, the metal silicide barrier layer 315 completely covers the surface of the flow blocking region 312 and is used to prevent the formation of metal silicide on the surface of the flow blocking region 312. The surrounding boundaries of the silicided metal barrier layer 315 all extend outside the blocking region 312.

Forming a metal silicide barrier layer 315 on the surface of the flow blocking area 312 can prevent the generation of cobalt silicide on the surface of the flow blocking area 312 and increase the contact resistance on the surface of the flow blocking area 312. In this way, the carriers do not flow on the surface of the flow blocking area 312, but flow from a region with a low resistance far away from the surface of the flow blocking area 312. This effectively prevents the changed paths of carriers from flowing above the blocking region 312, and further reduces the risk of carriers being captured by the misaligned lattice at the boundary between the shallow trench isolation structure and the active region.

In one embodiment, please refer to FIGS. 4 and 5, the drain doped region 310 is provided with shallow trench isolation structures 314 on both sides parallel to the length direction of the conductive channel, and the drain doped region 310 and the two At the junctions of the shallow trench isolation structures 314 with uniform sides, flow blocking regions 312 are formed. The concentration of the first conductivity type impurities in the drain doped region 310 between the blocking regions 312 is greater than the concentration of the first conductivity type impurities in the blocking region 312. When the device is operating, the secondary carrier will bypass the blocking region 312 and flow through the middle drain doped region 310, that is, the carrier path is changed but it will not block the flow of carriers to the drain doped region 310.

In the above LDMOS device, a current blocking region 312 is provided at the junction of the drain doped region 310 and the shallow trench isolation structure 314. The blocking region 312 is doped with impurities of the second conductivity type, and the concentration of the first conductivity type impurity in the blocking region 312 is less than the concentration of the first conductivity type carrier in the drain doping region 310, so that the blocking region The resistance of 312 is greater than that of the drain doped region 310. Carriers will preferentially flow to regions with low resistance. The carrier path is changed but does not block the flow of carriers to the drain doped region 310. Therefore, after the LDMOS device of the present application is turned on, since carriers will not flow to the junction of the drain doped region and the shallow trench isolation structure, it can prevent the carriers from being captured by the misaligned lattice at the junction, which reduces the The influence of the current in the linear region effectively improves the degradation of the current in the linear region and improves the lifetime of the hot carrier injection effect of the LDMOS device.

For the case where the channel width of the LDMOS device is narrow, even if a part of the current path in the middle region of the choke region 312 is sacrificed, due to the existence of the choke region 312, the carrier will change the path and avoid being trapped by the misaligned lattice, so it is still It can effectively improve the problem of linear current degradation.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To simplify the description, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, All should be considered within the scope of this description.

The above-mentioned embodiments only express several embodiments of the present invention, and their descriptions are more specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for a person of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all fall within the protection scope of the present invention. Therefore, the protection scope of the invention patent shall be subject to the appended claims.

Claims

A method for improving the lifetime of the hot carrier injection effect of an LDMOS device, the method comprising:

A substrate is provided in which a drain doped region of the LDMOS device is formed, and a shallow trench isolation structure is formed on at least one side of the drain doped region parallel to the length direction of the conductive channel, and the drain is doped The doping type of the impurity region is the first conductivity type;

Doping impurities of the second conductivity type to form a current blocking region at at least one boundary between the drain doped region and the shallow trench isolation structure; the second conductivity type is opposite to the first conductivity type.
The method according to claim 1, wherein a gate is formed on the substrate, a conductive channel region is formed in the substrate below the gate, and a source doping is formed in the substrate on one side of the gate A doped region, the drain doped region is formed in the substrate on the other side of the gate, a drift region is formed in the substrate between the gate and the drain doped region, and the source The doping types of the pole doped region and the drift region are the first conductivity type;

Forming the shallow trench isolation structure on at least one side of the drain doped region and the drift region parallel to the length direction of the conductive channel;

The current blocking region is formed at the junction of the drain doped region and the shallow trench isolation structure, and extends to the junction of the drift region and the shallow trench isolation structure, the current blocking region and the gate There is a gap between the poles.
The method according to claim 2, wherein the shallow trench is formed around the active region composed of the source doped region, the conductive channel region, the drift region and the drain doped region In the trench isolation structure, the current blocking region also extends into a shallow trench isolation structure on one side of the drain doped region parallel to the width direction of the conductive channel.
The method of claim 3, wherein the ratio of the size of the drain doped region parallel to the width direction of the conductive channel to the size of the current blocking region parallel to the width direction of the conductive channel The range is 100: 1 to 1000: 1, and the step after doping the second conductivity type impurities includes: forming a silicided metal barrier layer on the surface of the current blocking region.
The method according to claim 1, wherein in the step of doping the second conductivity type impurities, the implantation dose of the second conductivity type impurities is 10 14 / cm 2 to 10 16 / cm 2 .
An LDMOS device, including:

Substrate

The gate is formed on the substrate;

The conductive channel region is located in the substrate below the gate;

A source doped region located in the substrate on one side of the gate;

A drain doped region is located in the substrate on the other side of the gate; the drain doped region is provided with a shallow trench isolation structure on at least one side parallel to the length direction of the conductive channel, and the source The doping type of the polar doped region and the drain doped region is the first conductivity type; and

The current blocking region is located at at least one junction between the drain doped region and the shallow trench isolation structure, there is a gap between the current blocking region and the gate, and the current blocking region is doped with a second For conductivity type impurities, the concentration of the first conductivity type impurity in the drain doped region is greater than the concentration of the first conductivity type impurity in the current blocking region.
The LDMOS device according to claim 6, wherein the LDMOS device further comprises a drift region located in the substrate between the gate and the drain doped region; the doping type of the drift region is First conductivity type;

Forming the shallow trench isolation structure on at least one side of the drain doped region and the drift region parallel to the length direction of the conductive channel;

The current blocking region is located at the junction of the drain doped region and the shallow trench isolation structure, and extends to the junction of the drift region and the shallow trench isolation structure, and the first conductivity type impurity in the drift region The concentration of is greater than the concentration of impurities of the first conductivity type in the blocking region.
The LDMOS device according to claim 7, wherein half of the current blocking region is formed in the shallow trench isolation structure in the width direction parallel to the conductive channel, and the other half of the current blocking region is formed in the drain In the polar doped region and the drift region.
The LDMOS device according to claim 7 or 8, wherein the active region composed of the source doped region, the conductive channel region, the drift region and the drain doped region are all shallow In a trench isolation structure, the current blocking region also extends into a shallow trench isolation structure on one side of the drain doped region parallel to the width direction of the conductive channel.
The LDMOS device according to claim 9, wherein the size of the drain doped region parallel to the width direction of the conductive channel and the size of the current blocking region parallel to the width direction of the conductive channel The ratio ranges from 100: 1 to 1000: 1.
The LDMOS device according to claim 9, wherein the size of the current blocking region in the direction parallel to the width of the conductive channel is 0.2 μm to 0.6 μm, and the interval between the current blocking region and the gate It is 0.1 μm to 0.3 μm.
The LDMOS device according to claim 9, wherein the size of the current blocking region extending to a side of the drain doped region parallel to the width direction of the conductive channel in the shallow trench isolation structure is 0.1 μm To 0.3μm.
The LDMOS device according to claim 8, further comprising: a silicided metal barrier layer provided on the surface of the current blocking region.
The LDMOS device according to claim 13, wherein the silicided metal barrier layer completely covers the surface of the current blocking region.
The LDMOS device according to claim 13, wherein the silicide barrier layer is a silicon dioxide layer.