CN111128713A - Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell - Google Patents

Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell Download PDF

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CN111128713A
CN111128713A CN201911363060.9A CN201911363060A CN111128713A CN 111128713 A CN111128713 A CN 111128713A CN 201911363060 A CN201911363060 A CN 201911363060A CN 111128713 A CN111128713 A CN 111128713A
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word line
oxide layer
etching
boundary
silicon nitride
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CN111128713B (en
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张剑
熊伟
徐晓俊
陈华伦
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators

Abstract

The invention provides a method for improving the polycrystalline silicon residue of a word line at the boundary of an NORD flash unit, which comprises the following steps of depositing word line polycrystalline silicon on an STI (shallow trench isolation) area at the periphery of the unit; sequentially forming an oxide layer and a silicon nitride layer on the word line polysilicon; etching the unit periphery until part of the silicon nitride layer, the oxide layer and the word line polysilicon are etched until the STI region is exposed; depositing a thick gate oxide layer on the silicon nitride layer and the exposed STI region; etching the unit double gates, and removing the thick gate oxide layer on the silicon nitride layer at the periphery of the unit and the exposed thick gate oxide layer on the STI region; growing a thin gate oxide layer; depositing a grid polycrystalline silicon layer and a hard mask layer; etching the hard mask layer, the grid polycrystalline silicon, the thin grid oxide layer and the silicon nitride; etching the grid electrode to remove the oxide layer; the invention solves the problem of word line polysilicon residue by improving the etching step of the unit double gate and carrying out photoetching and etching of the double gate after the deposition of the thick oxygen gate.

Description

Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving polycrystalline silicon residue of a word line at the boundary of an NORD flash cell.
Background
In the traditional process, because the surface oxide of the word line poly is too thick, and the manufacturing process reasons of other devices such as logic and the like are considered, the polycrystalline silicon of the word line at the boundary of a cell (cell) cannot be completely removed, so that the performance of the flash cell (cell) is seriously influenced.
As shown in fig. 1a to 1h, fig. 1a to 1h are schematic structural diagrams of flash cell word line polysilicon removal process stages in the prior art, and the flash cell word line polysilicon removal process in the prior art has the following flows: word line polysilicon deposition; carrying out wet grinding and planarization on word line polysilicon; word line polysilicon ion implantation; forming an oxide layer on the Word Line (WL) polysilicon; word line silicon nitride deposition protection; photoetching and etching the periphery of a Memory Protection Layer (MPL) unit; thick gate oxygen deposition and growth; photoetching and ion implantation of an n well and a p well; double-gate photoetching and wet etching of a storage unit area; growing thin gate oxide; depositing grid polysilicon; photoetching a storage unit and etching grid polysilicon; removing the photoresist of the storage unit; wet etching the oxide layer and the silicon nitride; depositing polycrystalline silicon hard mask oxide; photoetching and etching the grid; CGCT (contact control gate) lithography and etching, polysilicon remains at the boundaries of the memory cells formed in fig. 1 h. Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the polysilicon residue on the boundary word line of an NORD flash cell, which is used to solve the problem that the polysilicon on the boundary word line of the memory cell cannot be completely removed in the process flow of the prior art, thereby seriously affecting the performance of the flash cell.
To achieve the above and other related objects, the present invention provides a method for improving poly residue in word lines at the boundary of NORD flash cells, the method at least comprising the following steps:
step one, providing an STI region at the periphery of a unit, and depositing word line polysilicon on the STI region;
step two, forming an oxide layer and a silicon nitride layer on the word line polysilicon in sequence;
etching the periphery of the unit until part of the silicon nitride layer, the oxide layer and the word line polysilicon are etched until the STI region is exposed;
fourthly, depositing a thick gate oxide layer on the silicon nitride layer and the exposed STI region;
etching the unit double gates, wherein the thick gate oxide layer on the silicon nitride layer on the periphery of the unit and the exposed thick gate oxide layer on the STI region are removed;
growing a thin gate oxide layer;
step seven, depositing the grid polysilicon and the hard mask layer;
eighthly, etching the hard mask layer, the grid polycrystalline silicon, the thin grid oxide layer and the silicon nitride;
step nine, grid etching is carried out, so that the oxide layer is removed;
step ten, etching the contact control gate to remove all word line polysilicon on the STI region at the periphery of the unit.
Preferably, the word line polysilicon in step one has a thickness of 2000 angstroms.
Preferably, in the first step, after the word line polysilicon deposition is performed, the word line polysilicon is sequentially subjected to wet grinding and ion implantation.
Preferably, the oxide layer formed on the word line polysilicon in step two is obtained by oxidizing the word line polysilicon.
Preferably, the thickness of the oxide layer formed in step two is 700 angstroms.
Preferably, the thickness of the silicon nitride layer formed in the second step is 540 angstroms, and the method for forming the silicon nitride layer is a deposition method.
Preferably, the etching window is defined by photolithography before etching the unit periphery in step three.
Preferably, the thickness of the thick gate oxide layer formed in step four is 180 angstroms.
Preferably, after depositing the thick gate oxide layer in the fourth step, forming an N-well and a P-well of the cell, and performing ion implantation of the N-well and the P-well.
Preferably, before the etching of the unit double-gate in the fifth step is performed, an etching window is defined by photolithography, and the etching in the fifth step is wet etching.
Preferably, the thickness of the thin gate oxide layer grown in step six is 26 angstroms.
Preferably, the gate polysilicon deposited in step seven is 1000 angstroms thick.
Preferably, the etching of the silicon nitride in the step eight is wet etching.
As described above, the method for improving the word line poly residue at the boundary of the NORD flash cell of the present invention has the following advantages: the invention solves the problem of word line polysilicon residue by improving the etching step of the unit double-gate and carrying out photoetching and etching of the double-gate after the thick oxygen gate is deposited.
Drawings
FIGS. 1a to 1h are schematic structural diagrams illustrating various process stages of removing polysilicon from a word line of a flash cell in the prior art;
FIGS. 2a to 2h are schematic structural diagrams of flash cell word line polysilicon removal process stages according to the present invention;
FIG. 3 is a schematic flow chart illustrating a method for improving word line poly residue at the boundary of a NORD flash cell according to the present invention;
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2a to fig. 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for improving polycrystalline silicon residue of a word line at the boundary of an NORD flash cell, as shown in FIG. 3, FIG. 3 is a schematic flow chart of the method for improving the polycrystalline silicon residue of the word line at the boundary of the NORD flash cell, and the method comprises the following steps:
step one, providing an STI region at the periphery of a unit, and depositing word line polysilicon on the STI region; as shown in fig. 2a, the word line polysilicon (i.e., WL polysilicon in fig. 2 a) is deposited on the upper surface of the STI region, which is the STI region at the periphery of the NORDflash cell.
Further, the word line polysilicon in step one has a thickness of 2000 angstroms. Furthermore, in the first step, after the word line polysilicon deposition is carried out, the word line polysilicon is sequentially subjected to wet grinding and ion implantation. And carrying out wet grinding on the WL polycrystalline silicon to planarize the surface of the WL polycrystalline silicon, and then carrying out ion implantation on the WL polycrystalline silicon.
Step two, forming an oxide layer and a silicon nitride layer on the word line polysilicon in sequence; as shown in fig. 2a, after WL polysilicon is formed on the STI region, the second step is to form an oxide layer on the WL polysilicon, and further, the oxide layer formed on the word line polysilicon in the second step is obtained by oxidizing the word line polysilicon. That is, the WL polysilicon itself is oxidized to form an oxide layer, and further, the thickness of the oxide layer formed in the second step is 700 angstroms. And forming a silicon nitride layer on the oxide layer after the oxide layer is formed, wherein the thickness of the silicon nitride layer formed in the second step is 540 angstroms, and the method for forming the silicon nitride layer is a deposition method. I.e., the silicon nitride layer is formed by depositing a layer of 540 angstroms of silicon nitride on the oxide layer.
Etching the periphery of the unit until part of the silicon nitride layer, the oxide layer and the word line polysilicon are etched until the STI region is exposed; as shown in fig. 2b, the structure shown in fig. 2b is a structure for forming the periphery of the NORD flash cell, and a giant step etches away a portion of the silicon nitride, the oxide layer and the WL polysilicon above the STI region during the etching process of the periphery of the cell, so as to form the structure shown in fig. 2b, wherein the portion that can be etched away exposes the upper surface of one side of the STI region. Furthermore, the etching window is defined by photoetching before the unit periphery is etched in the third step. That is, this step removes the silicon nitride, the oxide layer and the WL polysilicon in one side region on the STI region through a combination of photolithography and etching processes.
Fourthly, depositing a thick gate oxide layer on the silicon nitride layer and the exposed STI region; while forming a thick gate oxide layer for the NORD flash cell, a thick gate oxide layer is deposited simultaneously on the silicon nitride and the exposed upper surface of the STI region by etching as shown in FIG. 2 c. Further, the thickness of the thick gate oxide layer formed in the fourth step is 180 angstroms.
Furthermore, after the thick gate oxide layer is deposited in the fourth step, an N well and a P well of the cell are formed, and ion implantation of the N well and the P well is performed. That is, after the thick gate oxide layer is deposited in the fourth step, the unit is subjected to N-well and P-well fabrication by photolithography and etching, and after the N-well and the P-well are formed, ion implantation is performed in the N-well and the P-well, respectively.
Etching the unit double gates, wherein the thick gate oxide layer on the silicon nitride layer on the periphery of the unit and the exposed thick gate oxide layer on the STI region are removed; this step etches and forms the double gates of the NORD flash cell, and at the same time, the thick gate oxide layer on the silicon nitride layer at the periphery of the cell and the exposed thick gate oxide layer on the STI region are etched and removed, forming the structure as shown in FIG. 2 d.
Furthermore, before the etching of the unit double-grid in the step five, an etching window is defined by photoetching, and the etching in the step is wet etching. And fifthly, defining a double-gate window for etching the unit by adopting photoetching, then etching to form the double gates of the unit by adopting a wet etching method, and simultaneously removing the thick gate oxide layer on the silicon nitride layer at the periphery of the unit and the exposed thick gate oxide layer on the STI region by adopting wet etching.
Growing a thin gate oxide layer; this step grows a thin gate oxide layer on the silicon nitride layer, which is not shown in fig. 2d, and further according to the present invention, the thin gate oxide layer grown in step six has a thickness of 26 angstroms.
Step seven, depositing the grid polysilicon and the hard mask layer; the seventh step is to deposit and form the gate polysilicon and the hard mask layer of the cell, simultaneously form a layer of gate polysilicon on the thin gate oxide layer at the periphery of the cell, and then deposit a hard mask layer (i.e. the gate hard mask in fig. 2 e) on the gate polysilicon, and the formed structure is as shown in fig. 2e, further, the thickness of the gate polysilicon deposited in the seventh step is 1000 angstroms.
Eighthly, etching the hard mask layer, the grid polycrystalline silicon, the thin grid oxide layer and the silicon nitride; furthermore, the etching of the silicon nitride in the step eight is wet etching. That is, in this step, wet etching is used to remove the hard mask layer, the gate polysilicon and the silicon nitride layer, so as to form the structure shown in fig. 2 f.
Step nine, grid etching is carried out, so that the oxide layer is removed; this step performs a gate etch of the NORD flash cell while the oxide layer on the word line polysilicon is removed, resulting in the structure shown in fig. 2 g.
Step ten, etching the contact control gate to remove all word line polysilicon on the STI region at the periphery of the unit. The step is to etch the NORD flash cell contact control gate, and simultaneously, the word line polysilicon on the STI region at the periphery of the cell is completely removed. Resulting in the structure shown in figure 2 h.
In summary, the invention solves the problem of word line polysilicon residue by improving the etching step of the cell dual gate and performing the photolithography and etching of the dual gate after the deposition of the thick oxide gate. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (13)

1. A method for improving word line poly residue at the boundary of NORD flash cell, which comprises the following steps:
step one, providing an STI region at the periphery of a unit, and depositing word line polysilicon on the STI region;
step two, forming an oxide layer and a silicon nitride layer on the word line polysilicon in sequence;
etching the periphery of the unit until part of the silicon nitride layer, the oxide layer and the word line polysilicon are etched until the STI region is exposed;
fourthly, depositing a thick gate oxide layer on the silicon nitride layer and the exposed STI region;
etching the unit double gates, wherein the thick gate oxide layer on the silicon nitride layer on the periphery of the unit and the exposed thick gate oxide layer on the STI region are removed;
growing a thin gate oxide layer;
step seven, depositing the grid polysilicon and the hard mask layer;
eighthly, etching the hard mask layer, the grid polycrystalline silicon, the thin grid oxide layer and the silicon nitride;
step nine, grid etching is carried out, so that the oxide layer is removed;
step ten, etching the contact control gate to remove all word line polysilicon on the STI region at the periphery of the unit.
2. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: the thickness of the word line polysilicon in step one is 2000 angstroms.
3. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: and step one, after the word line polycrystalline silicon is deposited, carrying out wet grinding and ion implantation on the word line polycrystalline silicon in sequence.
4. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: and in the second step, the oxide layer formed on the word line polysilicon is obtained by oxidizing the word line polysilicon.
5. The method of claim 4 for improving word line poly residue at the boundary of NORD flash cells, wherein: the thickness of the oxide layer formed in the second step is 700 angstroms.
6. The method of claim 4 for improving word line poly residue at the boundary of NORD flash cells, wherein: the thickness of the silicon nitride layer formed in the second step is 540 angstroms, and the method for forming the silicon nitride layer is a deposition method.
7. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: and step three, defining an etching window by photoetching before etching the periphery of the unit.
8. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: the thickness of the thick gate oxide layer formed in step four is 180 angstroms.
9. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: and step four, after the thick gate oxide layer is deposited, forming an N well and a P well of the unit, and performing ion implantation of the N well and the P well.
10. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: and defining an etching window by adopting photoetching before the etching of the unit double-grid in the step five, wherein the etching in the step is wet etching.
11. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: the thickness of the thin gate oxide layer grown in the sixth step is 26 angstroms.
12. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: the thickness of the gate polysilicon deposited in step seven is 1000 angstroms.
13. The method of improving word line poly residue at the boundary of NORD flash cell of claim 1, wherein: and eighthly, etching the silicon nitride by a wet method.
CN201911363060.9A 2019-12-26 2019-12-26 Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell Active CN111128713B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112185972A (en) * 2020-09-23 2021-01-05 华虹半导体(无锡)有限公司 Method for manufacturing NORD flash memory device
CN112652626A (en) * 2020-12-18 2021-04-13 华虹半导体(无锡)有限公司 NORD flash manufacturing method, device and storage medium
CN113224072A (en) * 2021-04-25 2021-08-06 华虹半导体(无锡)有限公司 Method for improving damage of top oxide layer of word line in flash Cell area

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101192576A (en) * 2006-11-28 2008-06-04 中芯国际集成电路制造(上海)有限公司 SONOSSONOS Flash memory manufacture method
US20080135919A1 (en) * 2006-12-08 2008-06-12 Semiconductor Manufacturing International (Shanghai) Corporation Sonos flash memory and method for fabricationg the same
CN103107138A (en) * 2011-11-11 2013-05-15 中芯国际集成电路制造(上海)有限公司 Manufacturing method of separated grid type flash memory with peripheral circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101192576A (en) * 2006-11-28 2008-06-04 中芯国际集成电路制造(上海)有限公司 SONOSSONOS Flash memory manufacture method
US20080135919A1 (en) * 2006-12-08 2008-06-12 Semiconductor Manufacturing International (Shanghai) Corporation Sonos flash memory and method for fabricationg the same
CN103107138A (en) * 2011-11-11 2013-05-15 中芯国际集成电路制造(上海)有限公司 Manufacturing method of separated grid type flash memory with peripheral circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112185972A (en) * 2020-09-23 2021-01-05 华虹半导体(无锡)有限公司 Method for manufacturing NORD flash memory device
CN112185972B (en) * 2020-09-23 2022-10-04 华虹半导体(无锡)有限公司 Method for manufacturing NORD flash memory device
CN112652626A (en) * 2020-12-18 2021-04-13 华虹半导体(无锡)有限公司 NORD flash manufacturing method, device and storage medium
CN112652626B (en) * 2020-12-18 2022-09-30 华虹半导体(无锡)有限公司 NORD flash manufacturing method, device and storage medium
CN113224072A (en) * 2021-04-25 2021-08-06 华虹半导体(无锡)有限公司 Method for improving damage of top oxide layer of word line in flash Cell area

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