CN101192576A - SONOSSONOS Flash memory manufacture method - Google Patents
SONOSSONOS Flash memory manufacture method Download PDFInfo
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- CN101192576A CN101192576A CNA2007101265974A CN200710126597A CN101192576A CN 101192576 A CN101192576 A CN 101192576A CN A2007101265974 A CNA2007101265974 A CN A2007101265974A CN 200710126597 A CN200710126597 A CN 200710126597A CN 101192576 A CN101192576 A CN 101192576A
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Abstract
The invention discloses a method for manufacturing an SONOS flash memory, which includes the following steps: a silica substrate is provided and a silicon oxide - silicon nitride - silicon oxide layer, a first polysilicon layer and a first hard mask layer are arranged on a semiconductor substrate from the bottom to the top; the first hard mask layer is etched along the direction of a position line until the first polysilicon layer is exposed; the first hard mask layer is etched along the direction of a word line until the first polysilicon layer is exposed; and the first hard mask layer is used as a barrier layer and the first polysilicon layer and the silicon oxide - silicon nitride - silicon oxide layer are etched until the silica substrate is exposed so as to form a polysilicon gate structure array. By adopting the method, the polysilicon residue generated on a lateral wall of a dielectric layer and short circuit generated in different storage units can be avoided.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, relate in particular to the manufacture method of SONOS flash memory.
Background technology
Usually, the semiconductor memory that is used to store data is divided into volatile memory and nonvolatile memory, and volatile memory is easy to lose its data when power interruptions, even and nonvolatile memory still can the retention tab internal information after power supply is closed.Compare with other nonvolatile storage technologies (for example, disc driver), nonvolatile semiconductor memory has the advantages that cost is low, density is big.Therefore, nonvolatile memory has been widely used in every field, comprise embedded system, as PC and peripheral hardware, telecommunications switch, cell phone, network interconnection device, instrument and meter and automobile device, also comprise emerging voice, image, storage series products simultaneously, as digital camera, digital recorder and personal digital assistant.
Recently, propose to have the nonvolatile memory of silicon-oxide-nitride--oxide-silicon (SONOS) structure, comprised the SONOS flash memory.The nonvolatile memory of SONOS structure has very thin unit, and it is convenient to make and be bonded to easily in the outer peripheral areas and/or logic region of integrated circuit for example.
The patent No. comprises the steps for the United States Patent (USP) of US6797565 provides a kind of manufacture method of SONOS flash memory, shown in Figure 1A, at first, forms silica-silicon-nitride and silicon oxide layer (ONO) 102 on silicon substrate 100; On silica-silicon-nitride and silicon oxide layer 102, deposit first polysilicon layer 104 then; On first polysilicon layer 104, form first hard mask layer 106; Spin coating first photoresist layer 107 on first hard mask layer 106, through overexposure, developing process, form first opening figure 108 in first photoresist layer, 107 upper edge bit line direction, the position that needs to form source electrode and drain electrode on described first photoresist layer 107 in the position of first opening figure 108 and the silicon substrate 100 is corresponding.
Shown in Figure 1B, with first photoresist layer 107 is mask, to exposing silicon substrate 100, first polysilicon layer 104 after the etching and silica-silicon-nitride and silicon oxide layer 102 are as grid structure along first opening figure, 108 etchings, first hard mask layer 106, first polysilicon layer 104 and silica-silicon-nitride and silicon oxide layer 102; Remove first photoresist layer 107; With the grid structure is mask, carries out ion and inject in silicon substrate 100, forms source/drain 101.
Shown in Fig. 1 C, dielectric layer 110 on the silicon substrate 100 and first hard mask layer 106, the material of dielectric layer 110 is a cryogenic oxidation silicon, described low temperature is 200 ℃ to 500 ℃; Dielectric layer 110 is carried out planarization, until exposing first hard mask layer 106; Then, remove first hard mask layer 106, expose first polysilicon layer 104.
Shown in Fig. 1 D, deposition second polysilicon layer 112 on first polysilicon layer 104; Deposition second hard mask layer 114 on second polysilicon layer 112; Spin coating second photoresist layer 115 on second hard mask layer 114 through overexposure, developing process, forms second opening figure 116 at second photoresist layer, 115 upper edge word-line directions.
Shown in Fig. 1 E, be mask with second photoresist layer 115, along second opening figure, 116 etchings, second hard mask layer 114, second polysilicon layer 112 and first polysilicon layer 104 to exposing silica-silicon-nitride and silicon oxide layer 102; Remove second photoresist layer 115 and second hard mask layer 114 and couple together, form word line to exposing second polysilicon layer, 112, the second polysilicon layers 112 each grid structure with the SONOS flash memory.
The SONOS flash memory vertical view that Fig. 2 makes for prior art, wherein 110 is dielectric layers, 112 is second polysilicon layers.Fig. 2 A is a SONOS flash memory shown in Figure 2 cross section structure schematic diagram in the B-B direction, and B-B is the word-line direction of memory.As can be seen from Figure 2A, behind etching intact second hard mask layer 114, second polysilicon layer 112 and first polysilicon layer 104, owing between first polysilicon layer 104, be dielectric layer 110, first polysilicon layer 104 at dielectric layer 110 edges may be adsorbed by dielectric layer 110, therefore dielectric layer 110 sidewalls can form residual polysilicon 120, and residual polysilicon 120 can cause being short-circuited between the memory cell.
The existing SONOS flash memory of making, behind etching intact second hard mask layer, second polysilicon layer and first polysilicon layer, owing between first polysilicon layer, be dielectric layer, first polysilicon layer at the dielectric layer edge can be adsorbed by dielectric layer, therefore the dielectric layer sidewall can form residual polysilicon, and residual polysilicon can cause being short-circuited between the memory cell.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of SONOS flash memory, prevent behind etching intact second hard mask layer, second polysilicon layer and first polysilicon layer, owing between first polysilicon layer, be dielectric layer, first polysilicon layer at the dielectric layer edge may be adsorbed by dielectric layer, therefore the dielectric layer sidewall can form residual polysilicon, and residual polysilicon can cause being short-circuited between the memory cell.
For addressing the above problem, the invention provides a kind of manufacture method of SONOS flash memory, it is characterized in that, comprise the steps: to provide silicon substrate, comprise silica-silicon-nitride and silicon oxide layer, first polysilicon layer and first hard mask layer on the described Semiconductor substrate successively; Along bit line direction etching first hard mask layer to exposing first polysilicon layer; Along word-line direction etching first hard mask layer to exposing first polysilicon layer; With first hard mask layer is the barrier layer, and etching first polysilicon layer and silica-silicon-nitride and silicon oxide layer forms the polysilicon gate construction array to exposing silicon substrate; Deposition covers the dielectric layer of polysilicon gate construction array, and carries out planarization until exposing first hard mask layer; Remove first hard mask layer; Form second polysilicon layer and second hard mask layer successively at first polysilicon layer and dielectric layer surface; Along word-line direction etching second hard mask layer and second polysilicon layer to exposing dielectric layer; Remove second hard mask layer.
The method of etching first hard mask layer and second hard mask layer is the dry etching method, and the used gas of dry etching is CHF
3, O
2And Ar.
The material of described first hard mask layer and second hard mask layer is a silicon nitride layer.The thickness of described first hard mask layer is 400 dusts～500 dusts.The thickness of described second hard mask layer is 250 dusts～350 dusts.
Remove first hard mask layer and second hard mask layer with wet process.
Form dielectric layer with chemical vapour deposition technique, the material of described dielectric layer is a cryogenic oxidation silicon, and described low temperature is 200 ℃ to 500 ℃.
Compared with prior art, the present invention has the following advantages: the present invention is after bit line direction etching first hard mask layer, along word-line direction etching first hard mask layer once more, be barrier layer etch first polysilicon layer and silica-silicon-nitride and silicon oxide layer with first hard mask layer then, form the polysilicon gate array, recharge dielectric layer afterwards.Because first etching first polysilicon layer recharges dielectric layer, in the time of can not appearing at etching first polysilicon layer like this, because between first polysilicon layer, be dielectric layer, the phenomenon that may be adsorbed by dielectric layer at first polysilicon layer at dielectric layer edge, therefore can not produce residual polycrystalline silicon at the sidewall of dielectric layer, prevent to produce between the different memory cell phenomenon of short circuit, improved the performance of the SONOS flash memory that forms.
Description of drawings
Figure 1A to Fig. 1 E is the cross section structure schematic diagram that prior art forms SONOS flash memory technological process different step;
Fig. 2 is the SONOS flash memory vertical view that prior art forms;
Fig. 2 A is the cross section structure schematic diagram of SONOS flash memory shown in Figure 2 in the B-B direction;
Fig. 3 is the SONOS flash memory flow chart that the present invention forms;
Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A, Fig. 8 A, Fig. 9 A and Figure 10 A are the cross section structure schematic diagram of the SONOS flash memory of the present invention's making shown in Figure 11 along word line (A-A) direction;
Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B, Fig. 8 B, Fig. 9 B and Figure 10 B are the cross section structure schematic diagram of the SONOS flash memory of the present invention's making shown in Figure 11 along bit line (C-C) direction;
Figure 10 C is the cross section structure schematic diagram of the SONOS flash memory of the present invention's making shown in Figure 11 along word line (B-B) direction;
Figure 11 is the SONOS flash memory vertical view that the present invention forms.
Embodiment
The nonvolatile memory of SONOS structure has very thin unit, and it is convenient to make and be bonded to easily in the outer peripheral areas and/or logic region of integrated circuit for example.The existing SONOS flash memory of making, form in the process of word line at etching second hard mask layer, second polysilicon layer and first polysilicon layer, can between dielectric layer sidewall and dielectric layer, form residual polycrystalline silicon, thereby can cause producing between the different memory cell phenomenon of short circuit.The present invention is after bit line direction etching first hard mask layer, along word-line direction etching first hard mask layer once more, be barrier layer etch first polysilicon layer and silica-silicon-nitride and silicon oxide layer with first hard mask layer then, form the polysilicon gate array, recharge dielectric layer afterwards.Because first etching first polysilicon layer recharges dielectric layer, in the time of can not appearing at etching first polysilicon layer like this, because between first polysilicon layer, be dielectric layer, the phenomenon that can be adsorbed by dielectric layer at first polysilicon layer at dielectric layer edge, therefore can not produce residual polycrystalline silicon at the sidewall of dielectric layer, prevent to produce between the different memory cell phenomenon of short circuit, improved the performance of the SONOS flash memory that forms.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 3 is the flow chart that the present invention forms the SONOS flash memory.As shown in Figure 3, execution in step S101 provides silicon substrate, comprises silica-silicon-nitride and silicon oxide layer, first polysilicon layer and first hard mask layer on the described Semiconductor substrate successively; Execution in step S102, along bit line direction etching first hard mask layer to exposing first polysilicon layer; Execution in step S103, along word-line direction etching first hard mask layer to exposing first polysilicon layer; Execution in step S104 is the barrier layer with first hard mask layer, and etching first polysilicon layer and silica-silicon-nitride and silicon oxide layer forms the polysilicon gate construction array to exposing silicon substrate; Execution in step S105 forms the dielectric layer that covers the polysilicon gate construction array, and carries out planarization until exposing first hard mask layer; Execution in step S106 removes first hard mask layer; Execution in step S107 forms second polysilicon layer and second hard mask layer successively at first polysilicon layer and dielectric layer surface; Execution in step S108, along word-line direction etching second hard mask layer and second polysilicon layer to exposing dielectric layer; Execution in step S109 removes second hard mask layer.
In the present embodiment, execution in step S102 and execution in step S103 can exchange, that is to say, earlier along word-line direction etching first hard mask layer to exposing first polysilicon layer; And then along bit line direction etching first hard mask layer to exposing first polysilicon layer.
The present invention makes the method for SONOS flash memory, comprises the following steps, shown in Fig. 4 A and 4B, at first, forms silica-silicon-nitride and silicon oxide layer (ONO) 202 on silicon substrate 200; On silica-silicon-nitride and silicon oxide layer 202, form first polysilicon layer 204 with chemical vapour deposition technique then; On first polysilicon layer 204, form first hard mask layer 206 with chemical vapour deposition technique; Spin coating first photoresist layer 207 on first hard mask layer 206, through overexposure, developing process, form first opening figure 208 on first photoresist layer 207, the position that needs to form source electrode and drain electrode on described first photoresist layer 207 in the position of first opening figure 208 and the silicon substrate 200 is corresponding; With first photoresist layer 207 is mask, with the dry etching method along first opening figure, 208 etchings, first hard mask layer 206 to exposing first polysilicon layer 204.
In the present embodiment, the method that forms silica-silicon-nitride and silicon oxide layer (ONO) 202 is a prior art, for example chemical vapour deposition technique and oxidizing process.The thickness of first silicon oxide layer in silica-silicon-nitride and silicon oxide layer (ONO) 202 on silicon substrate 200 is 30 dusts～50 dusts, and concrete example is as 30 dusts, 35 dusts, 40 dusts, 45 dusts or 50 dusts, preferred 40 dusts of present embodiment; The thickness of silicon nitride layer is 50 dusts～70 dusts, and concrete example is as 50 dusts, 55 dusts, 60 dusts, 65 dusts or 70 dusts, preferred 60 dusts of present embodiment; The thickness that is positioned at second silicon oxide layer on the silicon nitride layer is 100 dusts～140 dusts, and concrete example is as 100 dusts, 110 dusts, 120 dusts, 130 dusts or 140 dusts, and present embodiment adopts 120 dusts.
The thickness of first polysilicon layer 204 is 600 dusts～800 dusts, and concrete thickness is 600 dusts, 650 dusts, 700 dusts, 750 dusts or 800 dusts for example, preferred 700 dusts of present embodiment.
The material of first hard mask layer 206 is a silicon nitride; The thickness of first hard mask layer 206 is 400 dusts～500 dusts, and concrete example is as 400 dusts, 450 dusts, 500 dusts, preferred 450 dusts of present embodiment.
In the present embodiment, dry etching first hard mask layer 206 used gases are CHF
3, O
2And Ar.
The SONOS flash memory that Fig. 5 A makes for the present invention is along the cross section structure schematic diagram of word-line direction; The SONOS flash memory that Fig. 5 B makes for the present invention is along the cross section structure schematic diagram of bit line direction.Shown in Fig. 5 A and Fig. 5 B, remove first photoresist layer 207 with ashing and wet process; On first hard mask layer 206 and first polysilicon layer 204, form second photoresist layer 209 with spin-coating method then,, on second photoresist layer 209, form second opening figure 210 along word-line direction through overexposure, developing process; With second photoresist layer 209 is mask, with the dry etching method along second opening figure, 210 etchings, first hard mask layer 206 until exposing first polysilicon layer 204.
The SONOS flash memory that Fig. 6 A makes for the present invention is along the cross section structure schematic diagram of word-line direction; The SONOS flash memory that Fig. 6 B makes for the present invention is along the cross section structure schematic diagram of bit line direction.Shown in Fig. 6 A and Fig. 6 B, remove second photoresist layer 209 with ashing and wet process; Then, be the barrier layer with first hard mask layer 206, to exposing silicon substrate 200, form the polysilicon gate construction array with dry etching method etching first polysilicon layer 204 and silica-silicon-nitride and silicon oxide layer 202.
The SONOS flash memory that Fig. 7 A makes for the present invention is along the cross section structure schematic diagram of word-line direction; The SONOS flash memory that Fig. 7 B makes for the present invention is along the cross section structure schematic diagram of bit line direction.Shown in Fig. 7 A and Fig. 7 B, on first hard mask layer 206 and silicon substrate 200, form the 3rd photoresist layer 211, exposure, formation the 3rd opening figure 212 of developing, the position of described the 3rd opening figure 212 is corresponding with the position that needs formation source region and drain region; With the 3rd photoresist layer 211 is mask, carries out ion along the 3rd opening figure 212 in silicon substrate 200 and injects, and forms source/drain 214.
In the present embodiment, the degree of depth that ion injects is a prior art, can require to adjust energy and the dosage that ion injects according to the different injection degree of depth, and the dosage that injects ion in the present embodiment is 1.0E15/cm
2～2.0E15/cm
2, concrete dosage is 1.0E15/cm
2, 1.5E15/cm
2Or 2.0E15/cm
2, present embodiment adopts 1.5E15/cm
2It is 15KeV～25KeV that ion injects institute's energy requirement, concrete example such as 15KeV, 20KeV or 25KeV, the preferred 20KeV of present embodiment.
The technology that forms source/drain 214 is prior art, and in one embodiment of the invention, backing material is selected P type silicon for use, and source electrode and drain electrode are carried out the injection of n type dopant ion, injects ion such as arsenic ion, phosphonium ion etc.
After ion injects, also can carry out the technology of thermal annealing, the ion of injection is better disperseed, the degree of depth that just makes the ion of injection enter silicon substrate 200 increases.
The SONOS flash memory that Fig. 8 A makes for the present invention is along the cross section structure schematic diagram of word-line direction; The SONOS flash memory that Fig. 8 B makes for the present invention is along the cross section structure schematic diagram of bit line direction.Shown in Fig. 8 A and 8B, remove the 3rd photoresist layer 211 with ashing and wet process; With chemical vapour deposition technique on silicon substrate 200 and the surface of first hard mask layer 206 form to cover the dielectric layer 216 of polysilicon gate construction array; Afterwards, adopt CMP (Chemical Mechanical Polishing) process planarization dielectric layer 216, until exposing first hard mask layer, 206 surfaces fully.
In the present embodiment, the material of dielectric layer 216 is silica, silicon oxynitride etc., and the present invention is most preferred to be cryogenic oxidation silicon (temperature is 200 ℃ to 500 ℃), and the using plasma chemical vapour deposition technique forms.
The SONOS flash memory that Fig. 9 A makes for the present invention is along the cross section structure schematic diagram of word-line direction; The SONOS flash memory that Fig. 9 B makes for the present invention is along the cross section structure schematic diagram of bit line direction.Shown in Fig. 9 A and Fig. 9 B, remove first hard mask layer 206 with wet process; The thickness that forms second polysilicon layer, 218, the second polysilicon layers 218 with chemical vapour deposition technique on first polysilicon layer 204 and dielectric layer 216 is 1000 dusts～1500 dusts, should cover dielectric layer 216 fully; Then, on second polysilicon layer 218, form second hard mask layer 220 with chemical vapour deposition technique; Spin coating the 4th photoresist layer 222 on second hard mask layer 220 through overexposure, developing process, forms the 4th opening figure 223 along word-line direction on the 4th photoresist layer 222.
In the present embodiment, the thickness concrete example of second polysilicon layer 218 is as 1000 dusts, 1100 dusts, 1200 dusts, 1300 dusts, 1400 dusts or 1500 dusts, preferred 1200 dusts of present embodiment.The thickness of second hard mask layer 220 is 250 dusts～350 dusts, and concrete example is as 250 dusts, 300 dusts or 350 dusts, and present embodiment adopts 300 dusts.
The SONOS flash memory that Figure 10 A and Figure 10 C make for the present invention is along the cross section structure schematic diagram of word-line direction; The SONOS flash memory that Figure 10 B makes for the present invention is along the cross section structure schematic diagram of bit line direction.Shown in Figure 10 A, Figure 10 B and Figure 10 C, be mask with the 4th photoresist layer 222, with the dry etching method along the 4th opening figure 223 etchings, second hard mask layer 220 and second polysilicon layer 218 to exposing dielectric layer 216; Remove the 4th photoresist layer 222 and second hard mask layer, 220, the second polysilicon layers 218 each grid structure of SONOS flash memory is coupled together, form word line.
The SONOS flash memory vertical view that Figure 11 makes for the present invention, wherein 216 is dielectric layers, 218 is second polysilicon layers.The SONOS flash memory that the present invention that Figure 10 A, 10B and 10C are respectively shown in Figure 11 makes is at the cross section structure schematic diagram of A-A, C-C, B-B direction.Wherein C-C is the bit line direction of memory, A-A, B-B and be the word-line direction of memory.From Figure 10 A to Figure 10 C as can be seen, after bit line direction etching first hard mask layer 206, along word-line direction etching first hard mask layer 206 once more, be barrier layer etch first polysilicon layer 204 and silica-silicon-nitride and silicon oxide layer 202 with first hard mask layer 206 then, form the polysilicon gate construction array; And etching second polysilicon layer 218, being etched to dielectric layer 216 when forming word line stops, therefore can between the sidewall of dielectric layer 216 and dielectric layer 216, not produce residual polycrystalline silicon, also just avoided having residual polycrystalline silicon between the different grid structure, prevent to produce between the different memory cell phenomenon of short circuit, improved the performance of the SONOS flash memory that forms.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the manufacture method of a SONOS flash memory is characterized in that, comprises the steps:
Silicon substrate is provided, comprises silica-silicon-nitride and silicon oxide layer, first polysilicon layer and first hard mask layer on the described Semiconductor substrate successively;
Along bit line direction etching first hard mask layer to exposing first polysilicon layer;
Along word-line direction etching first hard mask layer to exposing first polysilicon layer;
With first hard mask layer is the barrier layer, and etching first polysilicon layer and silica-silicon-nitride and silicon oxide layer forms the polysilicon gate construction array to exposing silicon substrate;
Deposition covers the dielectric layer of polysilicon gate construction array, and carries out planarization until exposing first hard mask layer;
Remove first hard mask layer;
Form second polysilicon layer and second hard mask layer successively at first polysilicon layer and dielectric layer surface;
Along word-line direction etching second hard mask layer and second polysilicon layer to exposing dielectric layer;
Remove second hard mask layer.
2. the manufacture method of SONOS flash memory according to claim 1 is characterized in that: the method for etching first hard mask layer and second hard mask layer is the dry etching method.
3. the manufacture method of SONOS flash memory according to claim 2 is characterized in that: the used gas of dry etching is CHF
3, O
2And Ar.
4. the manufacture method of SONOS flash memory according to claim 3 is characterized in that: the material of described first hard mask layer and second hard mask layer is a silicon nitride layer.
5. the manufacture method of SONOS flash memory according to claim 4 is characterized in that: the thickness of described first hard mask layer is 400 dusts～500 dusts.
6. the manufacture method of SONOS flash memory according to claim 4 is characterized in that: the thickness of described second hard mask layer is 250 dusts～350 dusts.
7. according to the manufacture method of each described SONOS flash memory of claim 1 to 6, it is characterized in that: remove first hard mask layer and second hard mask layer with wet process.
8. the manufacture method of the manufacture method of SONOS flash memory according to claim 1 is characterized in that: form dielectric layer with chemical vapour deposition technique.
9. the manufacture method of the manufacture method of SONOS flash memory according to claim 8 is characterized in that: the material of described dielectric layer is a cryogenic oxidation silicon.
10. the manufacture method of the manufacture method of SONOS flash memory according to claim 9 is characterized in that: described low temperature is 200 ℃ to 500 ℃.
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| CNB2007101265974A CN100517657C (en) | 2006-11-28 | 2007-06-22 | SONOS Flash memory manufacture method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496566A (en) * | 2011-11-29 | 2012-06-13 | 无锡中微晶园电子有限公司 | Storage-tube polycrystalline etching method in batch-production process of SONOS (Silicon Oxide Nitride Oxide Semiconductor) storage chips |
| CN111128713A (en) * | 2019-12-26 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell |
-
2007
- 2007-06-22 CN CNB2007101265974A patent/CN100517657C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496566A (en) * | 2011-11-29 | 2012-06-13 | 无锡中微晶园电子有限公司 | Storage-tube polycrystalline etching method in batch-production process of SONOS (Silicon Oxide Nitride Oxide Semiconductor) storage chips |
| CN102496566B (en) * | 2011-11-29 | 2014-08-06 | 无锡中微晶园电子有限公司 | Storage-tube polycrystalline etching method in batch-production process of SONOS (Silicon Oxide Nitride Oxide Semiconductor) storage chips |
| CN111128713A (en) * | 2019-12-26 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell |
| CN111128713B (en) * | 2019-12-26 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Method for improving polycrystalline silicon residue of boundary word line of NORD flash cell |
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