CN111128270A - On-chip termination resistance precision adjusting circuit and memory - Google Patents
On-chip termination resistance precision adjusting circuit and memory Download PDFInfo
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- CN111128270A CN111128270A CN201811290045.1A CN201811290045A CN111128270A CN 111128270 A CN111128270 A CN 111128270A CN 201811290045 A CN201811290045 A CN 201811290045A CN 111128270 A CN111128270 A CN 111128270A
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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Abstract
The utility model relates to an on-chip termination resistance precision adjustment circuit and memory, the on-chip termination resistance precision adjustment circuit that this disclosed embodiment provided mainly includes: the device comprises a pull-up unit, a pull-down unit and a control unit; the pull-up unit comprises a first resistance adjusting circuit, a first fixed resistor and a first resistor selecting circuit, the pull-down unit comprises a second resistor adjusting circuit, a second fixed resistor and a second resistor selecting circuit, and the control unit is used for sending control signals to the pull-up unit and the pull-down unit. In the on-die termination resistor precision adjusting circuit provided by the exemplary embodiment of the disclosure, by controlling the gating states of the first resistor selecting circuit and the second resistor selecting circuit, the controllable adjustment of the resistance value of the on-die termination resistor precision adjusting circuit can be optimized, especially the linearity and accuracy of the resistance value adjustment can be improved, and further the resistance value matching effect of the on-die termination resistor is improved.
Description
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to an on-chip termination resistance precision adjusting circuit and a memory.
Background
With the rapid development of semiconductor technology, the rise time of signals is shorter and shorter, which leads to the problem of signal integrity becoming more and more prominent, in the process of transmitting high-speed signals, in order to better improve the signal integrity of data lines, DDR2 can have a proper Termination resistance built in according to its own characteristics to ensure the integrity of transmission signals, but in the design of DDR3 and DDR4, an On Die Termination (ODT) resistance is separately added, that is, an ODT resistance is used to perform impedance matching On transmission lines, so that the energy loss and reflection of signals in the transmission process are reduced, and the correctness and integrity of signals received by a receiving end are ensured.
The accuracy of the ODT resistor is an important parameter for improving the correctness and integrity of a signal, and due to the influence of chip production, test and packaging technologies, the actual resistance value of the ODT resistor often has a certain error. And because of the reasons of error and regulation precision, the regulation linearity of the ODT resistor in the related technology is poor, so that the required standard design resistance value cannot be accurately obtained, and the matching degree with the transmission line resistance is also poor.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to an on-chip termination resistance precision adjusting circuit and a memory, and further, to overcome technical problems, such as an error in ODT resistance and poor adjustment linearity, caused by limitations of related technologies, at least to a certain extent.
According to one aspect of the present disclosure, an on-chip termination resistance precision adjusting circuit is provided, which is characterized by comprising: the device comprises a pull-up unit, a pull-down unit and a control unit;
wherein the pull-up unit includes:
a first end of the first resistance adjusting circuit is connected with the data node, and a second end of the first resistance adjusting circuit is connected with a first voltage end;
a first fixed resistor, a first end of the first fixed resistor being connected to the data node;
a first resistor selection circuit, a first end of the first resistor selection circuit being connected to a second end of the first fixed resistor, a second end of the first resistor selection circuit being connected to the first voltage terminal;
the pull-down unit includes:
a first end of the second resistance adjusting circuit is connected with the data node, and a second end of the second resistance adjusting circuit is connected with a second voltage end;
a second fixed resistor, a first end of the second fixed resistor being connected to the data node;
a first end of the second resistor selection circuit is connected with a second end of the second fixed resistor, and a second end of the second resistor selection circuit is connected with the second voltage end;
the control unit is used for sending control signals to the pull-up unit and the pull-down unit.
In an exemplary embodiment of the present disclosure, the first resistance selection circuit includes a plurality of first selectable circuits, a first end of the first selectable circuits is connected to the second end of the first fixed resistance, and a second end of the first selectable circuits is connected to the first voltage end;
the second resistor selection circuit comprises a plurality of second selectable circuits, a first end of each second selectable circuit is connected with a second end of the second fixed resistor, and a second end of each second selectable circuit is connected with the second voltage end.
In an exemplary embodiment of the present disclosure, the first optional circuit includes:
the first on-resistance has a fixed resistance value, and a first end of the first on-resistance is connected with the first voltage end;
and a first end of the pull-up switch element is connected with a second end of the first on-resistor, and a second end of the pull-up switch element is connected with a second end of the first fixed resistor.
In an exemplary embodiment of the present disclosure, the first on-resistance is an equivalent resistance of a PMOS transistor.
In an exemplary embodiment of the present disclosure, the pull-up switching element is a PMOS transistor.
In an exemplary embodiment of the present disclosure, the second optional circuit includes:
the second on-resistance has a fixed resistance value, and the first end of the second on-resistance is connected with the second voltage end;
and a first end of the pull-down switch element is connected with a second end of the second on-resistor, and a second end of the pull-down switch element is connected with a second end of the second fixed resistor.
In an exemplary embodiment of the present disclosure, the second on-resistance is an equivalent resistance of an NMOS transistor.
In an exemplary embodiment of the present disclosure, the pull-down switching element is an NMOS transistor.
In an exemplary embodiment of the present disclosure, each of the first selectable circuits has a different equivalent resistance value, and each of the second selectable circuits has a different equivalent resistance value.
In an exemplary embodiment of the present disclosure, the first resistance adjustment circuit includes:
a third fixed resistor, a first end of the third fixed resistor being connected to the data node;
and the first ends of the first regulating circuits are connected with the second ends of the third fixed resistors, and the second ends of the first regulating circuits are connected with the first voltage end.
In an exemplary embodiment of the present disclosure, the first adjusting circuit includes:
a first end of the first adjusting resistor is connected with the first voltage end;
and a first end of the first switching element is connected with the second end of the first adjusting resistor, and a second end of the first switching element is connected with the second end of the third fixed resistor.
In an exemplary embodiment of the present disclosure, the first adjustment resistance is an equivalent resistance of a PMOS transistor.
In an exemplary embodiment of the present disclosure, the first switching element is a PMOS transistor.
In an exemplary embodiment of the present disclosure, the second resistance adjustment circuit includes:
a fourth fixed resistor, a first end of the fourth fixed resistor being connected to the data node;
and a first end of the second regulating circuit is connected with a second end of the fourth fixed resistor, and a second end of the second regulating circuit is connected with the second voltage end.
In an exemplary embodiment of the present disclosure, the second adjusting circuit includes:
a first end of the second adjusting resistor is connected with the second voltage end;
and a first end of the second switching element is connected with a second end of the second adjusting resistor, and a second end of the second switching element is connected with a second end of the fourth fixed resistor.
In an exemplary embodiment of the present disclosure, the second adjustment resistance is an equivalent resistance of an NMOS transistor.
In an exemplary embodiment of the present disclosure, the second switching element is an NMOS transistor.
According to an aspect of the present disclosure, there is provided a memory characterized by including an on-die termination resistance precision adjustment circuit as in any of the above exemplary embodiments.
In the on-die termination resistor precision adjusting circuit provided by the exemplary embodiment of the disclosure, by controlling the gating states of the first resistor selecting circuit and the second resistor selecting circuit, the controllable adjustment of the resistance value of the on-die termination resistor precision adjusting circuit can be optimized, especially the linearity and accuracy of the resistance value adjustment can be improved, and further the resistance value matching effect of the on-die termination resistor is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic circuit diagram of an on-chip termination resistance precision adjustment circuit according to an exemplary embodiment of the disclosure.
Fig. 2 is a schematic circuit diagram of an on-chip termination resistance precision adjustment circuit according to another exemplary embodiment of the disclosure.
Fig. 3 is a schematic circuit diagram of an on-die termination resistance precision adjustment circuit according to another exemplary embodiment of the disclosure.
The reference numerals are explained below:
110-a pull-up unit;
120-a pull-down unit;
130-data node;
140-a first voltage terminal;
150-a second voltage terminal;
111-a first resistance adjustment circuit;
112-a first fixed resistance;
113-a first resistance selection circuit;
121-a second resistance adjustment circuit;
122-a second fixed resistance;
123-a second resistance selection circuit;
210-a first optional circuit;
220-a second optional circuit;
211 — first on resistance;
212-pull-up switching element;
221-a second on-resistance;
222-a pull-down switching element;
310-a third fixed resistance;
320-a first regulating circuit;
321-a first regulating resistor;
322-a first switching element;
330-fourth fixed resistance;
340-a second regulating circuit;
341-second regulating resistance;
342-a second switching element.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
In an exemplary embodiment of the present disclosure, an on-die termination resistance precision adjusting circuit is first provided, and the on-die termination resistance precision adjusting circuit may be applied to a Memory, for example, an output pin driving circuit of the Memory, where the Memory may include a Dynamic Random Access Memory (DRAM).
As shown in fig. 1, the on-die termination resistance precision adjusting circuit provided in the present exemplary embodiment may mainly include a pull-up unit 110, a pull-down unit 120, and a control unit (not shown in the figure).
The pull-up unit 110 is connected between a data node 130 and a first voltage terminal 140, wherein the data node 130 may be connected to an I/O pin DQ in the output pin driving circuit, and the first voltage terminal may be a power supply voltage VDDQ.
The circuit structure of the pull-up unit 110 may specifically include: a first resistance adjusting circuit 111, a first fixed resistance 112, and a first resistance selecting circuit 113.
The first end of the first resistance adjusting circuit 111 is connected to the data node 130, the second end of the first resistance adjusting circuit 111 is connected to the first voltage end 140, and the first resistance adjusting circuit 111 may be equivalent to a resistor whose resistance value can be controllably adjusted within a certain value range.
A first terminal of the first fixed resistor 112 is connected to the data node 130, a second terminal of the first fixed resistor 112 is connected to a first terminal of the first resistor selection circuit 113, and a second terminal of the first resistor selection circuit 113 is connected to the first voltage terminal 140. The first fixed resistor 112 has a fixed resistance, and the resistance of the equivalent resistor formed by connecting the first fixed resistor 112 and the first resistor selection circuit 113 in series can be changed by controlling the first resistor selection circuit 113.
The pull-down unit 120 is connected between the data node 130 and a second voltage terminal 150, and the second voltage terminal 150 may be a ground voltage VSSQ.
The circuit structure of the pull-down unit 120 may specifically include: a second resistance adjusting circuit 121, a second fixed resistance 122, and a second resistance selecting circuit 123.
The first end of the second resistance adjusting circuit 121 is connected to the data node 130, the second end of the second resistance adjusting circuit 121 is connected to the second voltage terminal 150, and the second resistance adjusting circuit 121 may be equivalent to a resistor whose resistance value can be controllably adjusted within a certain value range.
A first terminal of the second fixed resistor 122 is connected to the data node 130, a second terminal of the second fixed resistor 122 is connected to a first terminal of the second resistor selection circuit 123, and a second terminal of the second resistor selection circuit 123 is connected to the second voltage terminal 150. The second fixed resistor 122 has a fixed resistance, and the resistance of the equivalent resistor formed by connecting the second fixed resistor 122 and the second resistor selection circuit 123 in series can be changed by controlling the second resistor selection circuit 123.
The control unit is used to send control signals to the pull-up unit 110 and the pull-down unit 120.
In the on-die termination resistance precision adjusting circuit provided by the exemplary embodiment, by controlling the first resistance selection circuit 113 and the second resistance selection circuit 123, controllable adjustment of the equivalent resistance value of the on-die termination resistance precision adjusting circuit can be optimized, and especially, linearity and accuracy of resistance value adjustment can be improved, so that a resistance value matching effect of the on-die termination resistance precision adjusting circuit is improved.
As shown in fig. 2, in another exemplary embodiment of the present disclosure, the first resistance selection circuit 113 includes a plurality of first selectable circuits 210, a first terminal of the first selectable circuit 210 is connected to the second terminal of the first fixed resistance 112, and a second terminal of the first selectable circuit 210 is connected to the first voltage terminal 140.
The second resistor selection circuit 123 includes a plurality of second selectable circuits 220, a first terminal of the second selectable circuits is connected to the second terminal of the second fixed resistor 122, and a second terminal of the second selectable circuits 220 is connected to the second voltage terminal 150.
The first optional circuit 210 includes a first on-resistance 211 and a pull-up switching element 212. The first on-resistor 211 has a fixed resistance, a first end of the first on-resistor 211 is connected to the first voltage terminal 140, a second end of the first on-resistor 211 is connected to a first end of the pull-up switching element 212, and a second end of the pull-up switching element 212 is connected to a second end of the first fixed resistor 112. In the present exemplary embodiment, the first on-resistance 211 may be an equivalent resistance of a PMOS transistor, and the pull-up switching element 212 may be a PMOS transistor.
The second optional circuit 220 includes a second on-resistance 221 and a pull-down switching element 222. The second on-resistor 221 has a fixed resistance, a first end of the second on-resistor 221 is connected to the second voltage terminal 150, a second end of the second on-resistor 221 is connected to a first end of the pull-down switch element 222, and a second end of the pull-down switch element 222 is connected to a second end of the second fixed resistor 122. In the present exemplary embodiment, the second on-resistance 221 may be an equivalent resistance of an NMOS transistor, and the pull-down switching element 222 may be an NMOS transistor.
With continued reference to fig. 2, in the present exemplary embodiment, the number of the first optional circuits 210 may be three, three PMOS transistors as the first on-resistors 211 may respectively receive the same control signal Main _ P [3] from their respective gates, and three PMOS transistors as the pull-up switching elements 212 may respectively receive the three-way control signals TMP00, TMP01 and TMP10 from their respective gates. The three control signals of the TMP00, the TMP01 and the TMP10 are obtained by encoding two Test signals Test0 and Test1 sent by the control unit. The three control signals TMP00, TMP01 and TMP10 are used to adjust the on or off states of the first selectable circuits 210, and the first selectable circuits 210 have different equivalent resistance values in the on state. For example, when one of the first selectable circuits 210 is gated by the TMP00, the series resistance of the equivalent resistor in the path and the first fixed resistor 112 is 360 × 0.95 ohms, that is, 342 ohms; when the TMP01 is used to gate the second path of the first selectable circuit 210, the series resistance of the equivalent resistor on the path and the first fixed resistor 112 is 360 × 1.05 ohms, that is, 378 ohms; when the third optional circuit 210 is gated by the TMP10, the series resistance of the equivalent resistor of the path and the first fixed resistor 112 is 360 ohms.
For example, the on-die termination resistance precision adjusting circuit needs to match a target resistance value of 240 ohms, and the equivalent resistance value of the first resistance adjusting circuit 111 is 720 ohms, then ideally, the first selectable circuit 210 with a series resistance value of 360 ohms can be gated by the control signal TMP 10. However, due to an error, the equivalent resistance value of the first resistance adjusting circuit 111 may deviate from 720 ohms, and the series resistance value of the currently turned on first selectable circuit 210 and the first fixed resistor 112 may also deviate from 360 ohms. Therefore, the three first optional circuits 210 may be tested first, so that the on-die termination resistance precision adjustment circuit may more accurately match the target resistance. In the normal operation mode, the first optional circuit 210 capable of accurately matching the target resistance may be gated according to the test result.
In the exemplary embodiment, the number of the second optional circuits 220 may also be three, three NMOS transistors as the second on-resistors 221 may be respectively connected to the control signals Main _ N [3] by respective gates, and three NMOS transistors as the pull-down switching elements 222 may be respectively connected to the control signals TMN00, TMN01, and TMN10 by respective gates. The three control signals of TMN00, TMN01 and TMN10 are encoded by two Test signals Test2 and Test3 sent by the control unit. The on or off state of each of the second selectable circuits 220 can be adjusted using the three-way control signals TMN00, TMN01, and TMN10, and each of the second selectable circuits 220 has a different equivalent resistance value in the on state. For example, when one of the second selectable circuits 220 is gated by TMN00, the series resistance of the equivalent resistor in the path and the second fixed resistor 122 is 360 × 0.95 ohms, that is, 342 ohms; when the TMN01 is used to gate the second optional circuit 220, the series resistance of the equivalent resistor in the second optional circuit and the second fixed resistor 122 is 360 × 1.05 ohms, that is, 378 ohms; when the third optional circuit 220 is gated by TMN10, the series resistance of the equivalent resistor of the third optional circuit and the second fixed resistor 122 is 360 ohms. The control and resistance matching manner of the three second selectable circuits 220 in the pull-down unit is similar to that of the pull-up unit, and is not described herein again.
As shown in fig. 3, on the basis of the above exemplary embodiment, the first resistance adjusting circuit 111 may mainly include a third fixed resistance 310 and a plurality of first adjusting circuits 320.
The first terminal of the third fixed resistor 310 is connected to the data node 130, and the third fixed resistor 310 has a fixed resistance.
A first terminal of each first regulating circuit 320 is connected to the second terminal of the third fixed resistor 310, and a second terminal of the first regulating circuit 320 is connected to the first voltage terminal 140.
The first adjusting circuit 320 includes a first adjusting resistor 321 and a first switching element 322. A first terminal of the first adjusting resistor 321 is connected to the first voltage terminal 140, a second terminal of the first adjusting resistor 321 is connected to a first terminal of the first switching element 322, and a second terminal of the first switching element 322 is connected to a second terminal of the third fixed resistor 310. In the present exemplary embodiment, the first adjusting resistor 321 may be an equivalent resistor of a PMOS transistor, and the first switching element 322 may be a PMOS transistor.
The second resistance adjusting circuit 121 includes a fourth fixed resistance 330 and a plurality of second adjusting circuits 340.
The first terminal of the fourth fixed resistor 330 is connected to the data node 130, and the fourth fixed resistor 330 has a fixed resistance.
A first terminal of each second adjusting circuit 340 is connected to the second terminal of the fourth fixed resistor 330, and a second terminal of the second adjusting circuit 340 is connected to the second voltage terminal 150.
The second adjusting circuit 340 includes a second adjusting resistor 341 and a second switching element 342. A first terminal of the second adjusting resistor 341 is connected to the second voltage terminal 150, a second terminal of the second adjusting resistor 341 is connected to a first terminal of the second switching element 342, and a second terminal of the second switching element 342 is connected to a second terminal of the fourth fixed resistor 330. In the present exemplary embodiment, the second adjusting resistor 341 may be an equivalent resistance of an NMOS transistor, and the second switching element 342 may be an NMOS transistor.
With continued reference to fig. 3, in the present exemplary embodiment, the number of the first adjusting circuits 320 may be five, five PMOS transistors as the first adjusting resistors 321 may be respectively connected to five different control signals ZQ _ P [0], ZQ _ P [1], ZQ _ P [2], ZQ _ P [3], and ZQ _ P [4] by respective gates, and five PMOS transistors as the first switching elements 322 may be respectively connected to the enable signal EN by respective gates.
In the present exemplary embodiment, the number of the second adjusting circuits 340 may also be five, five NMOS transistors as the second adjusting resistors 341 may be respectively connected to five different control signals ZQ _ N [0], ZQ _ N [1], ZQ _ N [2], ZQ _ N [3], and ZQ _ N [4] through their respective gates, and five NMOS transistors as the second switching elements 342 may be respectively connected to the enable signal EN through their respective gates.
In an exemplary embodiment of the present disclosure, there is also provided a memory including the on-die termination resistance precision adjustment circuit as described in any of the above exemplary embodiments. The on-die termination resistance precision adjusting circuit part of the memory has been described in detail in the above exemplary embodiment, and therefore, the details are not described herein again.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (18)
1. An on-chip termination resistance precision adjustment circuit, comprising: the device comprises a pull-up unit, a pull-down unit and a control unit;
wherein the pull-up unit includes:
a first end of the first resistance adjusting circuit is connected with the data node, and a second end of the first resistance adjusting circuit is connected with a first voltage end;
a first fixed resistor, a first end of the first fixed resistor being connected to the data node;
a first resistor selection circuit, a first end of the first resistor selection circuit being connected to a second end of the first fixed resistor, a second end of the first resistor selection circuit being connected to the first voltage terminal;
the pull-down unit includes:
a first end of the second resistance adjusting circuit is connected with the data node, and a second end of the second resistance adjusting circuit is connected with a second voltage end;
a second fixed resistor, a first end of the second fixed resistor being connected to the data node;
a first end of the second resistor selection circuit is connected with a second end of the second fixed resistor, and a second end of the second resistor selection circuit is connected with the second voltage end;
the control unit is used for sending control signals to the pull-up unit and the pull-down unit.
2. The on-die termination resistance trimming circuit of claim 1, wherein the first resistance selection circuit comprises a plurality of first selectable circuits, a first end of the first selectable circuits being connected to a second end of the first fixed resistance, a second end of the first selectable circuits being connected to the first voltage terminal;
the second resistor selection circuit comprises a plurality of second selectable circuits, a first end of each second selectable circuit is connected with a second end of the second fixed resistor, and a second end of each second selectable circuit is connected with the second voltage end.
3. The on-die termination resistance accuracy adjustment circuit of claim 2, wherein the first selectable circuit comprises:
the first on-resistance has a fixed resistance value, and a first end of the first on-resistance is connected with the first voltage end;
and a first end of the pull-up switch element is connected with a second end of the first on-resistor, and a second end of the pull-up switch element is connected with a second end of the first fixed resistor.
4. The on-die termination resistance trimming circuit of claim 3, wherein the first on-resistance is an equivalent resistance of a PMOS transistor.
5. The on-die termination resistance accuracy adjustment circuit of claim 3, wherein the pull-up switching element is a PMOS transistor.
6. The on-die termination resistance accuracy adjustment circuit of claim 2, wherein the second selectable circuit comprises:
the second on-resistance has a fixed resistance value, and the first end of the second on-resistance is connected with the second voltage end;
and a first end of the pull-down switch element is connected with a second end of the second on-resistor, and a second end of the pull-down switch element is connected with a second end of the second fixed resistor.
7. The on-die termination resistance accuracy adjustment circuit of claim 6, wherein the second on-resistance is an equivalent resistance of an NMOS transistor.
8. The on-die termination resistance accuracy adjustment circuit of claim 6, wherein the pull-down switching element is an NMOS transistor.
9. The on-die termination resistance trimming circuit of claim 2, wherein each of the first selectable circuits has a different equivalent resistance value and each of the second selectable circuits has a different equivalent resistance value.
10. The on-die termination resistance trimming circuit according to any of claims 1 to 9, wherein the first resistance adjusting circuit comprises:
a third fixed resistor, a first end of the third fixed resistor being connected to the data node;
and the first ends of the first regulating circuits are connected with the second ends of the third fixed resistors, and the second ends of the first regulating circuits are connected with the first voltage end.
11. The on-die termination resistance trimming circuit of claim 10, wherein the first adjusting circuit comprises:
a first end of the first adjusting resistor is connected with the first voltage end;
and a first end of the first switching element is connected with the second end of the first adjusting resistor, and a second end of the first switching element is connected with the second end of the third fixed resistor.
12. The on-die termination resistance trimming circuit of claim 11, wherein the first tuning resistance is an equivalent resistance of a PMOS transistor.
13. The on-die termination resistance trimming circuit of claim 11, wherein the first switching element is a PMOS transistor.
14. The on-die termination resistance trimming circuit according to any of claims 1 to 9, wherein the second resistance adjusting circuit comprises:
a fourth fixed resistor, a first end of the fourth fixed resistor being connected to the data node;
and a first end of the second regulating circuit is connected with a second end of the fourth fixed resistor, and a second end of the second regulating circuit is connected with the second voltage end.
15. The on-die termination resistance trimming circuit of claim 14, wherein the second regulating circuit comprises:
a first end of the second adjusting resistor is connected with the second voltage end;
and a first end of the second switching element is connected with a second end of the second adjusting resistor, and a second end of the second switching element is connected with a second end of the fourth fixed resistor.
16. The on-die termination resistance trimming circuit of claim 14, wherein the second tuning resistance is an equivalent resistance of an NMOS transistor.
17. The on-die termination resistance accuracy adjustment circuit of claim 14, wherein the second switching element is an NMOS transistor.
18. A memory comprising the on-die termination resistance trimming circuit of any one of claims 1-17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811290045.1A CN111128270A (en) | 2018-10-31 | 2018-10-31 | On-chip termination resistance precision adjusting circuit and memory |
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| Application Number | Priority Date | Filing Date | Title |
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