KR20120005345A

KR20120005345A - Semiconductor memory device

Info

Publication number: KR20120005345A
Application number: KR1020100066045A
Authority: KR
Inventors: 양지연; 이동욱
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-07-08
Filing date: 2010-07-08
Publication date: 2012-01-16

Abstract

The semiconductor memory device may include an enable signal generation unit configured to selectively output ODT information or a fuse signal as an enable signal in response to the selection signal; And a first ODT connected to a first line through which an address or command is transmitted and activated in response to the enable signal.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device capable of smoothly transferring commands and addresses.

Synchronous memory devices capable of operating in synchronization with a clock have been introduced to improve operation speed in semiconductor memory devices. The first synchronous memory device was a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one cycle of a clock at one data pin in synchronization with a rising edge of the clock. However, since the SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high speed operation, a double data rate (DDR) synchronous memory device, which processes two data in a clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high speed operation.

Meanwhile, a termination resistor having a resistance value equal to the characteristic impedance of the transmission channel is connected to the receiving terminal or the transmitting terminal of the semiconductor device. The termination resistor matches the impedance of the receiving end or the transmitting end with the characteristic impedance of the transmitting channel to suppress reflection of signals transmitted through the transmitting channel. Conventional termination resistors have been installed outside of semiconductor chips, but recently, ODT circuits in which termination resistors are installed inside semiconductor chips have been mainly used. Since the ODT circuit includes a switching circuit for controlling the current flowing inside by the on / off operation, the power consumption is smaller than the termination resistor installed outside the chip.

Since the resistance value of the ODT circuit changes according to the process, voltage, and temperature (PVT) changes, the ZDT calibration circuit is applied prior to use to calibrate the resistance value of the ODT circuit. That is, the ODT circuit uses the pull-up code (PCODE) and pull-down code (NCODE) generated by the external resistance (ZQ) irrespective of the PVT change in the ZQ Calivration circuit. Correct it.

The present invention discloses a semiconductor memory device capable of smoothly transferring a command and an address by implementing an ODT circuit operating by using information or fuse cutting stored in a mode register.

To this end, the present invention comprises an enable signal generation unit for selectively outputting the ODT information or fuse signal as an enable signal in response to the selection signal; And a first ODT unit connected to a first line through which an address or command is transmitted and activated in response to the enable signal.

1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a fuse included in the semiconductor memory device shown in FIG. 1.
FIG. 3 is a circuit diagram of a multiplexer included in the semiconductor memory device shown in FIG. 1.
FIG. 4 is a circuit diagram of a first ODT unit included in the semiconductor memory device shown in FIG. 1.
FIG. 5 is a circuit diagram of a second ODT unit included in the semiconductor memory device shown in FIG. 1.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor memory device of this embodiment includes an enable signal generation unit 1, a first ODT unit 2, a second ODT unit 3, a command input buffer 4, and an address input buffer. (5) is included. The enable signal generation unit 1 includes a mode register 11, a fuse unit 12, and a multiplexer 13.

The mode register 11 stores and outputs the ODT information MRSODT set by the mode register setting.

The fuse unit 12 includes a fuse and outputs a fuse signal FUSE whose level is adjusted according to whether the fuse is cut. As shown in FIG. 2, the fuse part 12 of the present embodiment is turned on in response to the power supply signal VWRUP and the fuse F1 connected between the power supply voltage VDD and the node nd1 and the node nd1. NMOS transistor N1 for pull-down driving) and inverter IV1 for inverting and buffering the signal of node n1 to output fuse signal IV1. The fuse unit 12 having the above configuration drives the node n1 to a logic low level by a power-up signal PWRUP having a logic high level in the power-up section. Therefore, the fuse signal FUSE output from the fuse unit 12 is generated at a logic high level when the fuse F1 is cut, and is generated at a logic low level when the fuse F1 is not cut.

As shown in FIG. 3, the multiplexer 13 is turned on when the selection signal SEL is at a logic high level to transmit the ODT information MRSODT as the enable signal ODTEN, and to select the multiplexer 13. When the signal SEL is at the logic low level, the signal gate 107 is turned on to output the fuse signal FUSE as the enable signal ODTEN.

As shown in FIG. 4, the first ODT unit 2 includes a pull-up unit 21 including PMOS transistors P21 to P2N and resistor elements R21 to R2N, and NMOS transistors N21 to N2N. ) And a switch for supplying the power supply voltage VDD to the pull-up unit 21 when the pull-down unit 22 including the resistor elements R201 to R20N and the enable signal ODTEN having a logic high level are input. A PMOS transistor P201, which is a device, and an NMOS transistor N201, which is a switch device that is turned on to supply the ground voltage VSS to the pull-down unit 22 when the logic high level enable signal ODTEN is input. . The resistance value of the pull-up unit 21 is applied to the PMOS transistors P21 to P2N selectively turned on in response to the first to Nth pull-up codes PCODE <1: N> generated by the impedance calibration circuit (not shown). Is adjusted by The resistance value of the pull-down unit 22 is applied to the NMOS transistors N21 to N2N selectively turned on in response to the first to Nth pull-down codes NCODE <1: N> generated by the impedance calibration circuit (not shown). Is adjusted by The first ODT unit 2 configured as described above is activated when the enable signal ODTEN of the logic high level is input. In addition, the resistance values of the pull-up unit 21 and the pull-down unit 22 of the first ODT unit 2 may include first to Nth pull-up codes PCODE <1: N> and first to N-th pull-down codes NCODE. <1: N> to prevent reflection waves from occurring through the first line INL1 through which the command CMD is transmitted.

As shown in FIG. 5, the second ODT unit 3 includes a pull-up unit 31 including PMOS transistors P31 to P3N and resistor elements R31 to R3N, and NMOS transistors N31 to N3N. And a switch device configured to supply a power supply voltage VDD to the pull-up unit 31 when the pull-down unit 32 including resistance elements R301 to R30N and the enable signal ODTEN having a logic high level are input. When the PMOS transistor P301 and the logic high level enable signal ODTEN are input, the PMOS transistor P301 is turned on to supply the ground voltage VSS to the pull-down unit 32. The resistance value of the pull-up unit 31 is applied to the PMOS transistors P31 to P3N selectively turned on in response to the first to Nth pull-up codes PCODE <1: N> generated by the impedance calibration circuit (not shown). Is adjusted by The resistance value of the pull-down unit 32 is applied to the NMOS transistors N31 to N3N selectively turned on in response to the first to Nth pull-down codes NCODE <1: N> generated by the impedance calibration circuit (not shown). Is adjusted by The second ODT unit 3 configured as described above is activated when the logic high level enable signal ODTEN is input. In addition, the resistance values of the pull-up unit 31 and the pull-down unit 32 of the second ODT unit 3 include first to Nth pull-up codes PCODE <1: N> and first to N-th pull-down codes NCODE. <1: N> to prevent reflection waves from occurring through the second line INL2 through which the address ADD is transmitted.

The command input buffer 4 receives the command CMD transmitted through the first line INL1 and buffers the command CMD in response to the first reference voltage VREF1 to generate the internal command ICMD. The command input buffer 4 can be implemented with an input buffer circuit including a differential amplifier.

The address input buffer 5 receives the address ADD transmitted through the second line INL2 and buffers the second input voltage VREF2 to generate the internal address IADD. The address input buffer 5 may be implemented as an input buffer circuit including a differential amplifier.

The operation of the semiconductor memory device having the above-described configuration will be described. When the selection signal SEL is at the logic high level while the ODT information MRSODT and the fuse signal FUSE are at the logic low level, the selection signal SEL is logic. The low level is divided into the following.

When the selection signal SEL is at the logic high level, the transfer gate T10 of the multiplexer 13 is turned on and the ODT information MRSODT of the logic high level is output as the enable signal ODTEN. When the enable signal ODTEN is output at a logic high level, the first ODT unit 2 is activated, and the resistance value of the first ODT unit 2 is first to Nth pull-up codes PCODE <1: N>. And reflected wave generation through the first line INL1 through which the command CMD is transmitted by being adjusted by the first to Nth pull-down codes NCODE <1: N>. In addition, the second ODT unit 3 is activated by the enable signal ODTEN of the logic high level, and the resistance value of the second ODT unit 3 is the first to Nth pull-up codes PCODE <1: N>. ) And the first to Nth pull-down codes NCODE <1: N> to prevent the generation of reflected waves through the second line INL2 through which the address ADD is transmitted.

On the other hand, when the selection signal SEL is at the logic low level, the transfer gate T11 of the multiplexer 13 is turned on to output the fuse signal FUSE at the logic low level as the enable signal ODTEN. When the enable signal ODTEN is output at a logic low level, the first ODT unit 2 and the second ODT unit 3 are not activated.

As described above, the semiconductor memory device of the present embodiment connects the first ODT unit 2 to the first line INL1 to which the command CMD is transmitted, and the second line INL2 to which the address ADD is transmitted. The second ODT unit 3 is connected to the second ODT unit 3 so that a command and an address can be transmitted smoothly through the first line INL1 and the second line INL2 without a reflected wave. In addition, the semiconductor memory device of the present embodiment selectively transmits the ODT information MRSODT or the fuse signal FUSE by the selection signal SEL to activate the first ODT unit 2 and the second ODT unit 3. Adjust. Therefore, in the state where the command and the address are transmitted smoothly, the first ODT unit 2 and the second ODT unit 3 can be prevented from being activated, thereby preventing unnecessary current consumption.

1: Enable signal generator 11: Mode register
12: fuse unit 13: multiplexer
2: first ODT part 3: second ODT part
4: Command input buffer 5: Address input buffer

Claims

An enable signal generation unit for selectively outputting ODT information or a fuse signal as an enable signal in response to the selection signal; And
And a first ODT unit connected to a first line through which a command is transmitted and activated in response to the enable signal.

The method of claim 1, wherein the enable signal generation unit
A mode register for outputting the stored ODT information when the mode register is set;
A fuse unit generating the fuse signal in response to fuse cutting; And
And a multiplexer for selectively outputting the ODT information or the fuse signal as the enable signal in response to the selection signal.

The method of claim 1, wherein the first ODT unit
A pull-up unit configured to adjust the resistance in response to the pull-up code generated by the impedance calibration circuit to pull up the first line;
A pull-down unit configured to adjust the resistance in response to the pull-down code generated by the impedance calibration circuit to pull down the first line; And
And a switch configured to control whether power is supplied to the pull-up unit and the pull-down unit in response to the enable signal.

The semiconductor memory device of claim 1, further comprising a command input buffer configured to generate an internal command by buffering the command transmitted from the first line in response to a reference voltage.

The method of claim 1,
And a second ODT connected to a second line through which an address is transmitted, the second ODT being activated in response to the enable signal.

The semiconductor memory device of claim 5, wherein the first and second ODT units are simultaneously activated in response to the enable signal.

The method of claim 5, wherein the second ODT unit
A pull-up unit configured to adjust the resistance value in response to the pull-up code generated by the impedance calibration circuit to pull up the second line;
A pull-down unit configured to pull down the second line by adjusting a resistance value in response to the pull-down code generated by the impedance calibration circuit; And
And a switch configured to control whether power is supplied to the pull-up unit and the pull-down unit in response to the enable signal.

The semiconductor memory device of claim 5, further comprising an address input buffer configured to generate an internal address by buffering the address transmitted from the second line in response to a reference voltage.