KR20110046775A - Circuit and method for data transferring - Google Patents

Circuit and method for data transferring Download PDF

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Publication number
KR20110046775A
KR20110046775A KR1020090103424A KR20090103424A KR20110046775A KR 20110046775 A KR20110046775 A KR 20110046775A KR 1020090103424 A KR1020090103424 A KR 1020090103424A KR 20090103424 A KR20090103424 A KR 20090103424A KR 20110046775 A KR20110046775 A KR 20110046775A
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KR
South Korea
Prior art keywords
data
emphasis
unit
pull
node
Prior art date
Application number
KR1020090103424A
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Korean (ko)
Inventor
이근일
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090103424A priority Critical patent/KR20110046775A/en
Publication of KR20110046775A publication Critical patent/KR20110046775A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

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  • Dram (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)

Abstract

The present invention relates to a data transmission method and a data transmission method, and a data transmission circuit according to the present invention includes a transmission unit for driving data to an A node; A de-emphasis unit for driving inverted data of the data to the A node; And a control unit for activating the de-emphasis unit when the data has the same value over a preset interval.

Data Transfer, Output Driver, De-emphasis

Description

Data transmission circuit and transmission method {CIRCUIT AND METHOD FOR DATA TRANSFERRING}

The present invention relates to a data transmission circuit and a transmission method, and more particularly, to a de-emphasis operation of the data transmission circuit.

1 illustrates a portion of a data transfer circuit applied to a semiconductor memory device.

As shown in FIG. 1, the data transmission circuit includes a transmission unit 110 and a de-emphasis unit 120.

The transmitter 110 is an output driver that transmits data to the outside of the chip through the data pad DQ, and may include a pull-up driver 111 and a pull-down driver 112. The pull-up driver 111 is turned on when the data P_DATA is 'high' level to drive the data pad DQ. When the pull-up driver 111 pulls up the data pad DQ, the level of the data pad DQ becomes a 'high' level, and 'high' data is output to the outside of the chip. The pull-down driver 112 is turned on when the data N_DATA is 'low' level to pull down the data pad DQ. When the pull-down driver 112 pulls down the data pad DQ, the level of the data pad DQ becomes a 'low' level, and 'low' data is output to the outside of the chip. The impedance control codes PCODE <0: 5> and NCODE <0: 5> input to the pull-up driver 111 and the pull-down driver 112 adjust the resistance values of the pull-up driver 111 and the pull-down driver 112. This code is intended to be used, and this code (PCODE <0: 5>, NCODE <0: N>) is made in a ZQ calibration circuit located near the ZQ pad. In summary, whether the pull-up driver 111 of the transmitter 110 is turned on or the pull-down driver 112 is turned on is determined according to the logic values of the data P_DATA and N_DATA. Which resistance value the pull-down driver 112 has is determined according to the impedance control codes PCODE <0: N> and NCODE <0: N>. For reference, in the current graphic memory device, the target resistance of the pull-up driver 111 is 40 Ω.

The de-emphasis unit 120 operates the de-emphasis 120 to reduce the driving force of the output data P_DATA and N_DATA. Reducing the driving force means that the 'high' data makes the lower level 'high' level and the 'low' data makes the higher level 'low' level. The de-emphasis unit 120 includes a pull-up driver 121 and a pull-down driver 122 similarly to the transmitter 110. However, the de-emphasis unit 120 drives the data pad DQ with the data P_DATAB and N_DATAB inverted by the data driven by the transmitter 110. Therefore, when the pull-up driver 111 of the transmitter 110 is turned on, the pull-down driver 122 of the de-emphasis unit 120 is turned on, and when the pull-down driver 112 of the transmitter 110 is turned on, the de-amp is turned on. The pull-up driver 121 of the sheath portion is turned on. Codes PPRE <0: 2> and NPRE <0: 2> input to the de-emphasis unit 120 are codes for setting resistance values of the de-emphasis unit 120. It is set by the setting (MRS: Mode Registor Setting). The de-emphasis unit 120 is not intended to change the logic value itself of the data pad DQ, but rather to reduce the driving force of the data driven by the data pad DQ. The driving force of is designed to be weaker than the driving force of the transmission unit 110.

Although the de-emphasis operation is performed to prevent the logic level of the data pad DQ from being too high or low, the de-emphasis operation consumes too much current. For example, when 'high' data is output to the data pad DQ, the pull-up driver 111 of the transmitter 110 is turned on, and at the same time, the pull-down driver 122 of the de-emphasis unit 120 is turned on. As a result, a current path is formed between the power supply voltage VDD and the ground voltage VSS, and the current consumption rapidly increases. Therefore, a technique for reducing the current consumption by the de-emphasis operation is required.

The present invention has been proposed to solve the above problems of the prior art, and to provide a data transmission circuit that consumes a small current while performing a de-emphasis operation.

A data transmission circuit according to the present invention for achieving the above object, the transmission unit for driving data to the A node; A de-emphasis unit for driving inverted data of the data to the A node; And a control unit for activating the de-emphasis unit when the data has the same value over a preset interval.

The controller may include: a storage unit dividing and storing the data into rising data and polling data; And a comparator configured to compare the rising data and the polling data to generate a de-emphasis signal for activating the de-emphasis unit.

The comparison unit may activate the de-emphasis signal when the rising data and the falling data are the same.

The node A may be a node connected to a data pad, and the transmitter may be an output driver.

A data transmission method according to the present invention for achieving the above object, the first step of driving data to the A node; And a second step of driving the inverted data of the data to the A node with a driving force weaker than the first step, wherein the second step operation is activated when the data has the same value over a predetermined interval. It features.

The activation control of the second step may include: storing rising data synchronized with a rising clock among the data; Storing polling data synchronized with a polling clock among the data; And comparing the rising data with the polling data and activating the second step operation when the two data are the same.

In the present invention described above, the de-emphasis operation is performed only when the data to be transmitted continuously has the same value. On the other hand, the de-emphasis operation is not performed in a section in which data is output in the form of a toggle so that the logic level of the data is not excessively high or low.

Therefore, while achieving the goal of the original de-emphasis operation, there is an advantage that can reduce the current consumption according to the de-emphasis operation.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a data transmission circuit according to an embodiment of the present invention.

As shown in FIG. 2, the data transmission circuit according to the present invention includes a transmitter 210, a de-emphasis unit 220, and a controller 230.

The transmitter 210 transmits data to the outside of the chip through the data pad DQ, and may include a pull-up driver 211 and a pull-down driver 212. The pull-up driver 211 is turned on when the data P_DATA is 'high' level to drive the data pad DQ. When the pull-up driver 211 pulls up the data pad DQ, the level of the data pad DQ becomes a 'high' level, and 'high' data is output to the outside of the chip. The pull-down driver 212 is turned on when the data N_DATA is 'low' level to pull down the data pad DQ. When the pull-down driver 212 pulls down the data pad DQ, the level of the data pad DQ becomes a 'low' level, and 'low' data is output to the outside of the chip. The impedance adjustment codes PCODE <0: N> and NCODE <0: N> input to the pull-up driver 211 and the pull-down driver 212 adjust the resistance values of the pull-up driver 211 and the pull-down driver 212. The code for this code (PCODE <0: N>, NCODE <0: N>) can be made in a ZQ calibration circuit located near the ZQ pad. In summary, whether the pull-up driver 211 of the transmitter 210 is turned on or the pull-down driver 212 is turned on is determined according to the logic values of the data P_DATA and N_DATA. Which resistance value the and pull-down drivers 212 have is determined according to the impedance control codes PCODE <0: N> and NCODE <0: N>. P_DATA and N_DATA have the same level while the transmitter is operating. However, when both the pull-up driver 211 and the pull-down driver 212 of the transmitter 210 need to be turned off (for example, when the data pad needs to be floated), P_DATA = 'low' and N_DATA = 'high'level are set. .

The de-emphasis unit 220 performs a de-emphasis operation to reduce the driving force of the output data. Reducing the driving force means that the 'high' data makes the lower level 'high' level and the 'low' data makes the higher level 'low' level. The de-emphasis unit 220 includes a pull-up driver 221 and a pull-down driver 222 similarly to the transmitter 210. However, the de-emphasis unit 210 drives the data pad DQ with data P_DATAB and N_DATAB inverted by the data driven by the transmitter. Therefore, when the pull-up driver 211 of the transmitter 210 is turned on, the pull-down driver 222 of the de-emphasis unit 220 is turned on, and the de-amper when the pull-down driver 212 of the transmitter 210 is turned on. The pull-up driver 221 of the sheath portion 220 is turned on. The codes PPRE <0: 2> and NPRE <0: 2> input to the de-emphasis unit 220 are codes for setting resistance values of the de-emphasis unit 220. It is set by the setting (MRS). The de-emphasis unit 220 is not intended to change the logic value itself of the data pad DQ from 'high' to 'low' or from 'low' to 'high', but is driven by the data pad DQ. Since it is a configuration for reducing the driving force of, the driving force of the de-emphasis unit 220 is designed to be weaker than the driving force of the transmission unit 210. The de-emphasis signal DE_EN input to the de-emphasis unit 220 is a signal for activating or deactivating the de-emphasis unit 220. When the de-emphasis signal DE_EN is activated, the de-emphasis unit 220 performs the de-emphasis operation. When the de-emphasis signal DE_EN is deactivated, the de-emphasis unit 220 does not perform the de-emphasis operation. Do not. That is, when the de-emphasis signal ED_EN is deactivated, both the pull-up driver 221 and the pull-down driver 222 are turned off regardless of the logic values of the data P_DATAB and N_DATAB.

The controller 230 activates the de-emphasis unit 220 when the data P_DATA and N_DATA driven through the transmitter 210 have the same value over a preset interval, and otherwise de-emphasis. Deactivate the unit 220. When the data P_DATA and N_DATA are outputted continuously in the same manner, the level of the data pad DQ is too high (when 'high' data is continuously output) or the level of the data pad DQ is too low ( 'Low' data is output continuously). In this case, therefore, the de-emphasis operation is further required. However, when the data P_DATA, N_DATA is toggled (such as 'high', 'low', 'high' or 'low'), the level of the data pad DQ may be excessively high or low. There is no need for de-emphasis operation. The control unit 230 deactivates the de-emphasis signal DE_EN to prevent the de-emphasis operation in the section where the data P_DATA and N_DATA are toggled, and de-emphasis when the data P_DATA and N_DATA are continuously output identically. The sheath signal DE_EN is activated to control the level of the data pad DQ from being too high or low through the de-emphasis operation. Through such control of the controller 230, the current consumption can be reduced while achieving the purpose of the original de-emphasis operation.

Although FIG. 2 illustrates that the transmitter 210 and the de-emphasis unit 220 drive the data pad DQ, the transmitter 210 and the de-emphasis unit 220 may be any data transmission node in the chip. Naturally, the embodiment for driving (node A) is also possible. This is because data is transferred from place to place as well as between chips.

3 is a diagram illustrating an embodiment of the pull-up driver 221 and the pull-down driver 212 of the de-emphasis unit 220 of FIG. 2.

As shown in FIG. 3, the pull-up driver 221 of the de-emphasis unit 220 includes NAND gates 311 to 313, PMOS transistors 321 to 323, and resistors 331 to 333. do. In operation, when the inverted data P_DATAB and the de-emphasis signal DE_EN are 'high', the PMOS transistors 321 to 323 are turned on according to the code PPRE <0: 2> and the data pad ( DQ) is pulled up. When the de-emphasis signal DE_EN is 'low' or the inverted data P_DATAB is 'low', all the PMOS transistors 321 to 323 are off.

The pull-down driver 222 of the de-emphasis unit 220 includes inverters 341 to 343, noah gates 351 to 353, NMOS transistors 361 to 363, and resistors 371 to 373. In operation, when the inverted data N_DATAB is 'low' and the de-emphasis signal DE_EN is 'high', the NMOS transistors 361 to 363 turn on according to the code NPRE <0: 2>. The data pad DQ is pulled down. When the de-emphasis signal DE_EN is 'low' or the inverted data N_DATAB is 'high', all the NMOS transistors 361 to 363 are turned off.

4 is a configuration diagram of an embodiment of the controller 230 of FIG. 2.

As shown in FIG. 4, the controller 230 polls the data (which may be input because P_DATA = N_DATA when the P_DATA or N_DATA data transmission circuit is operating, and hereinafter referred to as P_DATA) with the rising data R_DATA. A storage unit 410 for dividing and storing the data F_DATA, and a comparison for generating the de-emphasis signal DE_EN for activating the de-emphasis unit 220 by comparing the rising data R_DATA and the falling data F_DATA. It is configured to include a portion 430. Here, the rising data R_DATA refers to the data P_DATA input during the 'high' period of the clock CLK, and the falling data F_DATA refers to the data P_DATA input during the 'low' period of the clock CLK. Say.

The storage unit 410 is turned on in the high section of the clock CLK to receive the data P_DATA, and is turned on in the low section of the clock CLK to store the data P_DATA. Outputs the second passgate 416, the first latches 417 and 418 that store the output data of the first passgate 415 as the rising data R_DATA, and the output data of the second passgate 416. And second latches 419 and 420 that store the polling data F_DATA. Briefly, the first passgate 415 is turned on in the 'high' section of the clock CLK so that the rising data R_DATA of the data P_DATA is stored in the first latches 417 and 418. The second pass gate 416 is turned on in the 'low' section of the CLK, and the polling data F_DATA_ among the data P_DATA is stored in the second latches 419 and 420.

The comparator 430 compares whether the rising data R_DATA and the polling data F_DATA stored in the storage unit 410 are the same using the noah gate 431, and the two data R_DATA and F_DATA are the same. In this case, the de-emphasis signal DE_EN is activated and output.

The NAND gates 411, 413, and 432 of FIG. 4 receive an enable signal ENABLE to activate / deactivate the controller 430. The enable signal ENABLE is a signal that activates / deactivates the de-emphasis operation itself. The enable signal ENABLE is a signal that is activated 'high' during the operation period of the controller 430. When the enable signal ENABLE is deactivated to 'low', the de-emphasis operation is not performed in any case.

5 is a view showing the overall operation of the data transmission circuit according to the present invention.

Referring to FIG. 5, data synchronized to the 'high' section of the clock CLK among the data P_DATA and N_DATA is stored as the rising data R_DATA, and 'low' of the clock CLK among the data P_DATA and N_DATA. The data synchronized to the section is stored as polling data F_DATA. The de-emphasis signal DE_EN is activated 'high' in the same section of the rising data R_DATA and the falling data F_DATA.

The de-emphasis operation occurs in the section where the de-emphasis signal DE_EN is activated 'high', and the de-emphasis operation does not occur in the section in which the de-emphasis signal DE_EN is deactivated to 'low'. In the section in which the data P_DATA and N_DATA toggle, the deemphasis signal DE_EN remains inactivated, and in the case where the data P_DATA and N_DATA have the same level two or more times in succession, the deemphasis is performed. It can be seen from the drawing that the signal DE_EN remains activated.

Looking at the output of the data transmission circuit (the output of the OUTPUT and the DQ pad), it can be seen that the driving force of the data is weakly adjusted by the de-emphasis operation when the same data P_DATA and N_DATA are output two or more times. . In the figure, the part where the de-emphasis operation occurs is indicated by a dotted line.

Referring back to Figures 2 to 5 will be described with respect to the data transmission method according to the present invention.

A data transmission method according to the present invention includes a first step of driving data (P_DATA, N_DATA) to an A node; And a second step of driving the inverted data P_DATAb and N_DATAB of the data to the A node with a driving force weaker than the first step. The second operation may be controlled to be activated when the data P_DATA and N_DATA have the same value over a predetermined interval.

In addition, the activation control of the second step may include: storing data R_DATA synchronized to the rising clock among the data P_DATA and N_DATA; Storing data F_DATA synchronized to a polling clock among the data; And comparing the rising data R_DATA and the falling data F_DATA to activate the second operation when the two data R_DATA and F_DATA are the same.

The first step may be understood with reference to the operation of the transmitter 210, and the second step may be understood with reference to the operation of the de-emphasis unit 220. In addition, the control of the second step to be activated may be understood with reference to the operation of the controller 230.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

1 illustrates a portion of a data transfer circuit applied to a semiconductor memory device.

2 is a block diagram of a data transmission circuit according to an embodiment of the present invention.

3 is a diagram illustrating an embodiment of a pull-up driver 221 and a pull-down driver 212 of the de-emphasis unit 220 of FIG. 2.

4 is a diagram illustrating an embodiment of the control unit 230 of FIG. 2.

5 illustrates the overall operation of a data transfer circuit in accordance with the present invention.

Claims (13)

A transmission unit for driving data to the A node; A de-emphasis unit for driving inverted data of the data to the A node; And Control unit for activating the de-emphasis unit when the data has the same value for a predetermined interval or more Data transmission circuit comprising a. The method of claim 1, The control unit, A storage unit dividing and storing the data into rising data and polling data; And A comparator for comparing the rising data and the polling data to generate a de-emphasis signal for activating the de-emphasis unit Data transmission circuit comprising a. 3. The method of claim 2, The storage unit, A first passgate turned on in a high section of a clock to receive the data; A second pass gate turned on in a low section of a clock to receive the data; A first latch configured to store output data of the first passgate as the rising data; And And a second latch for storing output data of the second passgate as the polling data. 3. The method of claim 2, Wherein, And an exclusive NOR gate for comparing the rising data and the falling data. 3. The method of claim 2, Wherein, And if the rising data and the falling data are identical to each other, activating the de-emphasis signal. The method of claim 1, The A node is a node connected to the data pad, And the transmission unit is an output driver. The method of claim 6, The pull-up resistance value and the pull-down resistance value of the output driver, A data transmission circuit, characterized in that determined by the impedance control code. The method of claim 6, Pull-up resistance value and pull-down resistance value of the de-emphasis unit, A data transfer circuit, characterized by the mode register setting. The method of claim 1, The de-emphasis unit, And a driving force weaker than that of the transmitting unit. A first step of driving data to the A node; And A second step of driving the inversion data of the data to the node A with a driving force weaker than the first step, The second step operation is controlled to be activated when the data has the same value for more than a predetermined interval. The method of claim 10, The activation control of the second step, Storing rising data synchronized with a rising clock among the data; Storing polling data synchronized with a polling clock among the data; And Comparing the rising data with the polling data and activating the second operation when the two data are the same Data transmission method comprising a. The method of claim 10, The A node, And a node connected to the data pad. The method of claim 10, The data transmission method, Setting a driving force of the first step in response to an impedance control code; And Setting the driving force of the second step in response to a mode register setting value Data transmission method further comprises.
KR1020090103424A 2009-10-29 2009-10-29 Circuit and method for data transferring KR20110046775A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941411B2 (en) 2012-12-20 2015-01-27 SK Hynix Inc. Signal transmission circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941411B2 (en) 2012-12-20 2015-01-27 SK Hynix Inc. Signal transmission circuit

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