CN111092056B - Integrated circuit and chip - Google Patents
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- CN111092056B CN111092056B CN201911368955.1A CN201911368955A CN111092056B CN 111092056 B CN111092056 B CN 111092056B CN 201911368955 A CN201911368955 A CN 201911368955A CN 111092056 B CN111092056 B CN 111092056B
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Abstract
The embodiment of the invention provides an integrated circuit and a chip, wherein the integrated circuit comprises a control signal generation module, a strobe output unit and a control signal output unit, wherein the control signal generation module is used for generating a control signal and inputting the control signal to the strobe output unit through a control end; the first functional circuit is used for acquiring first data, processing the first data to obtain processed first data and outputting the processed first data to the first input end; the second functional circuit is used for acquiring second data, processing the second data to obtain processed second data and outputting the processed second data to a second input end; and the gating output unit is used for gating the first input end and the second input end according to the control signal so as to selectively output at least one part of the processed first data and/or at least one part of the processed second data. The embodiment of the invention effectively prevents the integrated circuit from being analyzed by reverse engineering, thereby preventing the internal logic function of the integrated circuit from being cracked.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuit design, in particular to an integrated circuit and a chip.
Background
In the design of a chip in the existing industrial production, a design mode of an Integrated Circuit (IC for short) is usually adopted to realize the Circuit function, and the design mode of the Integrated Circuit has the advantages of small volume, low power consumption, low cost and high integration level, so that the requirement of chip miniaturization is easier to meet.
Conventional image forming systems, such as printers, copiers, and facsimile machines, are used to form images of information to be formed on an image forming medium, such as paper, using an image forming material, such as toner or ink. An image forming system generally includes an image forming apparatus and at least one image forming cartridge detachably mounted to the image forming apparatus. In order to better record the state of the imaging material in the imaging box and complete the matching verification of the imaging box and the imaging device, a chip is usually mounted on the imaging box and used for storing information related to the imaging box, such as rewritable information like residual imaging material information and the like, and identification and authentication information of the imaging box. However, since the complexity of the circuit arrangement of the chip on the printed circuit board is not high, the internal circuit of the chip can be easily disassembled and extracted for reverse analysis, and the logic function of the internal circuit can be analyzed by performing hierarchical arrangement on the internal circuit, so that the chips with similar functions can be imitated.
A conventional technique for preventing an integrated circuit from being analyzed reversely is based on the principle shown in fig. 1, in which a plurality of metal interconnects are encapsulated in an insulating region between a metal layer n and a metal layer n +1, the plurality of metal interconnects include a metal interconnect net1 that enables at least a part of a circuit of the metal layer n to be correctly connected to at least a part of a circuit of the metal layer n +1, and a metal interconnect net2 that enables at least a part of a circuit of the metal layer n to be incorrectly connected to at least a part of a circuit of the metal layer n +1, and when there are n places between the metal layer n and the metal layer n +1 where a true and false metal interconnect needs to be determined, 2n kinds of possibilities may occur in the circuit. Through the design of the true and false metal interconnection lines, the design of the PCB layout of the chip is more complex, and the logic function of the internal circuit is difficult to analyze and crack.
However, the above prior art starts with increasing the structural difficulty of the PCB layout circuit design of the chip to reduce the risk of the integrated circuit being analyzed reversely, but if the chip is longitudinally dissected, it is still possible to determine which is the correct metal interconnection line, and break the logic function of the internal circuit. On the other hand, because the standard process for manufacturing the chip does not support the true and false metal interconnection lines, if the chip is manufactured by adopting the prior art, a special process is needed to realize, and the cost for manufacturing the chip is greatly increased. Therefore, there is a need for a technology that can effectively prevent the logic function of the internal circuit of the chip from being cracked, and can manufacture the chip with low cost and high efficiency.
Disclosure of Invention
The embodiment of the invention provides an integrated circuit and a chip, which are used for effectively preventing the integrated circuit and the chip from being analyzed by reverse engineering so as to avoid stealing of related data stored in the integrated circuit and the chip.
In a first aspect, an embodiment of the present invention provides an integrated circuit, disposed on a chip, including: the system comprises at least one gating output unit, a control signal generation module and at least two functional circuits; the at least two functional circuits include a first functional circuit and a second functional circuit;
the gating output unit comprises at least one control end and at least two input ends; the control end is connected with the control signal generation module, the at least two input ends comprise a first input end and a second input end, the first input end is connected with the first functional circuit, and the second input end is connected with the second functional circuit;
the control signal generation module is used for generating a control signal and inputting the control signal to the gating output unit through the control end;
the first functional circuit is used for acquiring first data, processing the first data to obtain processed first data, and outputting the processed first data to the first input end;
the second functional circuit is configured to acquire second data, process the second data to obtain processed second data, and output the processed second data to the second input terminal;
and the gating output unit is used for gating the first input end and the second input end according to the control signal so as to select and output at least one part of the processed first data and/or at least one part of the processed second data.
In a possible design, the control signal generating module is specifically configured to receive instruction information and generate the control signal according to the instruction information;
alternatively, the first and second electrodes may be,
generating the control signal according to a predetermined setting before receiving the instruction information.
In one possible design, the control signal generation module includes: at least two fixed circuits and a selection circuit;
the selection circuit is arranged between the at least two fixed circuits and the control end of the gating output unit and used for generating selection signals, selecting the at least two fixed circuits according to the selection signals, generating the control signals according to the set number generated by the selected fixed circuits and sending the control signals to the control end of the gating output unit.
In one possible design, the control signal generation module includes: at least one random circuit;
the random circuit is connected with the control end of the gating output unit and used for generating a random number and sending the random number to the control end of the gating output unit as the control signal.
In one possible design, the control signal generation module further includes: a volatile register unit;
and one end of the volatile register unit is connected with the selection circuit or the random circuit, and the other end of the volatile register unit is connected with the control end of the gating output unit, and the volatile register unit is used for registering data generated by the selection circuit or the random circuit, generating a control signal according to the data and sending the control signal to the control end of the gating output unit.
In one possible design, the control signal generation module further includes: a nonvolatile memory cell and a data loading circuit;
one end of the nonvolatile storage unit is connected with the selection circuit or the random circuit, the other end of the nonvolatile storage unit is connected with one end of the data loading circuit, the other end of the data loading circuit is connected with the volatile register unit, the nonvolatile storage unit is used for storing data generated by the selection circuit or the random circuit and sending the data to the volatile register unit through the data loading circuit for registering, so that the volatile register unit generates a control signal according to the data and sends the control signal to the control end of the strobe output unit.
In one possible design, the control signal generation module includes: a nonvolatile memory cell and a data loading circuit;
the nonvolatile storage unit is connected with one end of the data loading circuit and is used for storing at least one set number or set data, and the set number or set data is written and stored by a manufacturer when a chip is manufactured;
and the other end of the data loading circuit is connected with the control end of the strobe output unit and is used for selecting the set number or the set data in the nonvolatile storage unit, generating the control signal according to the set number or the set data and sending the control signal to the control end of the strobe output unit.
In one possible design, the control signal generation module further includes: a data write circuit;
the data writing circuit is connected with the nonvolatile storage unit and used for writing the at least one set number or set data into the nonvolatile storage unit when the chip is manufactured.
In one possible design, the non-volatile memory cell is configured to support only write operations and not read operations.
In one possible design, the control signal generation module further includes: a volatile register unit;
the volatile register unit is arranged between the data loading circuit and the control end of the strobe output unit and is used for receiving and registering the at least one set number or set data sent by the nonvolatile storage unit through the data loading circuit, generating the control signal according to the at least one set number or set data and sending the control signal to the control end of the strobe output unit.
In one possible design, the control signal is generated by the control signal generation module according to a predetermined setting before receiving the instruction information;
the control signal generating module is further configured to send the control signal to the at least two functional circuits, so that the at least two functional circuits perform data processing according to the control signal.
In one possible design, the non-volatile memory cell includes a data signal output circuit;
the metal wiring of the data signal output circuit is designed to include a lower layer connection wiring and a higher layer protection wiring overlying the lower layer wiring.
In a second aspect, an embodiment of the present invention provides a chip provided with the integrated circuit according to the first aspect and various possible designs of the first aspect.
In a third aspect, an embodiment of the present invention provides an imaging cartridge, where the imaging cartridge is detachably mounted on an imaging device, and the imaging cartridge is provided with the chip of the second aspect.
The integrated circuit provided by the embodiment processes the received data respectively through the first functional circuit and the second functional circuit, and outputs the processed data to the strobe output unit. The control signal generation module generates a control signal according to the received instruction information or preset settings, and controls the gating output unit so that the gating output unit selectively outputs the processed data generated by the circuits with different functions. The integrated circuit is effectively prevented from being analyzed by reverse engineering, and further the internal logic function of the integrated circuit is prevented from being cracked.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art process for preventing reverse analysis;
FIG. 2 is an architectural diagram of an imaging system provided in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of an integrated circuit according to yet another embodiment of the present invention;
FIG. 4 is a schematic diagram of an integrated circuit according to yet another embodiment of the present invention;
FIG. 5 is a schematic diagram of an integrated circuit according to yet another embodiment of the present invention;
FIG. 6 is a schematic diagram of an integrated circuit according to yet another embodiment of the present invention;
fig. 7 is a schematic structural diagram of an integrated circuit according to yet another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solutions of the present invention are described in detail below with reference to the accompanying drawings and embodiments, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. In order to simplify the description process and make the technical solution appear clearly, the following only takes the case that the integrated circuit is disposed on the chip of the imaging box as an example, but the solution of the following embodiment describes that the integrated circuit is also applicable to other types of chips.
Fig. 2 is an architecture diagram of an imaging system according to an embodiment of the present invention. As shown in fig. 2, the image forming system includes an image forming cartridge 101 and an image forming apparatus 102; the imaging cartridge 101 may be detachably mounted on the imaging apparatus 102, and the imaging cartridge 101 may be loaded with an imaging cartridge chip 1011, the imaging cartridge chip 1011 is configured to record imaging data (including raw data and usage data, such as production date, model number, remaining amount information of imaging material, number of imaging pages, and number of rotations of the rotating unit of the imaging cartridge) of imaging material in the imaging cartridge, and is configured to verify whether the imaging cartridge is fitted to the imaging apparatus based on the stored identification authentication information of the imaging cartridge.
In a specific implementation process, the imaging box chip 1011 is installed in the imaging box 101, and then the imaging box 101 with the imaging box chip 1011 installed is installed in the imaging device, so that pins of the imaging box chip 1011 are in contact with contact pins on the imaging device side and are electrically connected, and data communication with the imaging device is realized. After the imaging device powers on the imaging box chip 1011, the imaging box identification authentication information stored in the imaging box chip 1011 can be read for validity verification, and the imaging data stored in the imaging box chip 1011 can also be acquired, so that the imaging device performs imaging operation according to the imaging data.
Therefore, the logic function of the integrated circuit of the imaging box chip 1011 is particularly important in the process, and if the imaging box chip 1011 is cracked by reverse engineering to analyze the logic function of the integrated circuit, the imaging data stored in the imaging box chip 1011 can be read out, so that a chip with similar functions can be imitated. However, in the prior art, a redundant metal connection line is usually added in the chip preparation process to confuse reverse engineering implementers, and the method needs a special process with higher cost and has a poor protection effect. Based on this, the embodiment of the present invention provides an integrated circuit, which is disposed on the imaging box chip 1011 and can effectively prevent the imaging box chip 1011 from being analyzed by reverse engineering, thereby preventing the logic function inside the chip from being cracked.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 3 is a schematic structural diagram of an integrated circuit 10111 according to another embodiment of the invention. As shown in fig. 3, the integrated circuit 10111, which may be disposed on the imaging cartridge chip 1011, includes: at least one strobe output unit 13, a control signal generation block 14 and at least two functional circuits; the at least two functional circuits comprise a first functional circuit 11 and a second functional circuit 12;
the gating output unit 13 comprises at least one control end, at least one output end and at least two input ends; the control end is connected with the control signal generation module, the at least two input ends include a first input end and a second input end, the first input end is connected with the first functional circuit 11, and the second input end is connected with the second functional circuit 12;
the control signal generating module 14 is configured to generate a control signal, and input the control signal to the gated output unit 13 through the control terminal;
the first functional circuit 11 is configured to acquire first imaging data, process the first imaging data to obtain processed first imaging data, and output the processed first imaging data to the first input end;
the second functional circuit 12 is configured to acquire second imaging data, process the second imaging data to obtain processed second imaging data, and output the processed second imaging data to the second input end;
the gating output unit 13 is configured to gate the first input end and the second input end according to the control signal, so as to selectively output the processed first imaging data and the processed second imaging data.
The imaging data storage unit 10 is used for storing imaging data related to the imaging box.
Specifically, the first functional circuit 11 acquires the first imaging data from the imaging data storage unit 10, processes the first imaging data, and sends the processed first imaging data to the gate output unit 13. The second functional circuit 12 acquires second imaging data from the imaging data storage unit 10, processes the second imaging data, and sends the second imaging data to the gate output unit 13. The control signal generating module 14 generates a control signal, and inputs the control signal to the gate output unit 13 through the control terminal.
Optionally, the control signal generating module 14 may generate the control signal in various ways, and may receive instruction information sent by the imaging apparatus, and generate the control signal according to the instruction information, or may prestore an instruction in the integrated circuit for a default program executed after power-on, so that the control signal generating module 14 may also generate the control signal according to the prestored instruction before receiving the instruction information, or an internal circuit of the control signal generating module 14 automatically generates the control signal after power-on before receiving the instruction information.
The gating output unit 13 is connected to the control signal generation module 14, and configured to receive the control signal sent by the control signal generation module 14, select the processed first imaging data and the processed second imaging data under the control of the control signal, obtain third imaging data, where the third imaging data is composed of at least a part of the processed first imaging data and/or at least a part of the processed second imaging data, and send the third imaging data to the imaging device through an output end.
In this embodiment, the first functional circuit 11 and the second functional circuit 12 are independent from each other and do not affect each other, and the first imaging data processed by the first functional circuit 11 and the second imaging data processed by the second functional circuit 12 may be the same data in the imaging memory unit or different data. The processed first imaging data and the processed second imaging data are respectively sent to different input terminals of the connectivity output unit 13. Among them, the image formation data stored in the image formation storage unit may be information related to the image formation cartridge, such as image formation material initial amount information, image formation material color information, and the like.
It should be noted that the first functional circuit 11 and the second functional circuit 12 may respectively implement multiple logic functions, wherein the first functional circuit 11 and the second functional circuit 12 may be logic circuits with the same function, for example, both implement combinational logic operation or sequential logic operation on input data, and the first functional circuit 11 and the second functional circuit 12 may also be logic circuits with different functions. For example, a forward logic circuit and a reverse-prevention logic circuit, respectively. Optionally, the integrated circuit 10111 may comprise a plurality of first functional circuits 11, and/or a plurality of second functional circuits 12.
The gated output unit 13 includes an output terminal 131, a control terminal 132, and a plurality of input terminals. The strobe output unit 13 selects the data obtained from each input end according to the control signal obtained from the control end 132, and selects one of the data to transmit to the output end 131.
Specifically, the operation of the gated output unit 13 will be described by taking as an example two input terminals, namely the first input terminal 133 and the second input terminal 134: the gate output unit 13 is connected to the control signal generating module 14 through the control terminal 132, connected to the first functional circuit 11 through the first input terminal 133, and connected to the second functional circuit 12 through the second input terminal 134; the way of implementing data selection by the strobe data unit 13 is: the control terminal 132 receives a control signal sent by the control signal generating module 14, and the control signal is used to control the gate output unit 13 to select whether to acquire the processed first imaging data output by the first functional circuit 11 or the processed second imaging data output by the second functional circuit 12, and output the acquired third imaging data to the imaging device through the output terminal 131.
It should be noted that, in order to meet the requirement, the number of the input terminals of the gated output unit 13 is expanded, and the gated output unit 13 may be composed of a plurality of selectors with fewer input terminals. For example, if the gated output unit 13 needs to have 4 input terminals, it can be implemented by using a plurality of two-input selectors. Specifically, the first two-input selector is used for connecting the first input end and the second input end; the second two-input selector is used for connecting the third input end and the fourth input end; the first input terminal of the third two-input selector is connected to the output terminal of the first two-input selector, the second input terminal is connected to the output terminal of the second two-input selector, and the output terminal is connected to the output terminal 131 of the gate output unit 13.
The control signal generating module 14 receives and analyzes the instruction information sent by the imaging device, generates a corresponding control signal according to the analysis result, and sends the corresponding control signal to the control terminal 132, or generates control information in the imaging device before receiving the instruction information sent by the imaging device, directly generates a corresponding control signal according to the generated control information when receiving the instruction information sent by the imaging device, and sends the corresponding control signal to the control terminal 132, the gating output unit 13 selects the first functional circuit 11 or the second functional circuit 12 according to the control signal of the control terminal 132, the selected functional circuit outputs the processed correct imaging data to the gating output unit 13, and the gating output unit 13 sends the acquired imaging data to the imaging device. The control signal generated by the control signal generating module 14 may be in various forms, for example, the control signal may be a periodically continuous level signal or a non-periodically continuous level signal.
In the integrated circuit 10111 provided in this embodiment of the present invention, the control signal generating module 14 generates a corresponding control signal according to instruction information or a predetermined setting sent by the imaging device, the strobe output unit 13 selects a corresponding input terminal according to the control signal to strobe the first functional circuit to output correct data (processed first imaging data) or the second functional circuit to output correct data (processed second imaging data), and outputs the selected data, and if the data is not selected according to the control signal generated by the control signal generating module 14, the data output to the imaging device by the strobe output unit is incorrect data, so that the imaging device cannot operate normally. Based on the chip of the embodiment, even if the chip is subjected to destructive research and the structure of the internal circuit is analyzed reversely, the method for reading out the correct imaging data cannot be decoded because the generation rule of the control signal cannot be obtained, and the purpose of protecting the logic function of the chip circuit from being decoded is achieved.
In practical applications, there are various ways for the control generation module to generate the control signal, and the control signal generation process is described below with reference to fig. 4 to 7.
Fig. 4 is a schematic structural diagram of an integrated circuit 10111 according to another embodiment of the present invention, as shown in fig. 4, a detailed description is made on a generation process of a control signal based on the above-mentioned embodiment, for example, based on the embodiment shown in fig. 3, and specifically, the control signal generation module 14 includes: a first fixed circuit 144, a second fixed circuit 145 and a selection circuit 146.
The first fixed circuit 144 is configured to generate first fixed data.
The second fixed circuit 145 is configured to generate second fixed data.
The selection circuit 146 is connected to the first fixed circuit 144 and the second fixed circuit 145, and configured to generate a selection signal, selectively output the first fixed data and the second fixed data according to the selection signal, generate the control signal according to the selectively output data, and send the control signal to the gate output unit 13.
In practical applications, when the control signal is a level signal that is periodically continuous, the control signal may be generated according to a set number, that is, the fixed data is a set number, the set number may be binary data, and the number of bits may be one or more bits.
Specifically, there are various ways to generate the control signal according to the set number, wherein in an implementation manner, the control signal is written by a manufacturer and stored in a storage unit (e.g., a nonvolatile storage unit) in the control signal generation module 14 at the time of chip manufacturing, and the detailed description of the implementation manner refers to the embodiment shown in fig. 7 below.
In an implementation manner, the set number may be generated by at least two fixed circuits (e.g., the first fixed circuit 144 and the second fixed circuit 145) in the control signal generation module 14, each corresponding to one type of instruction information. The control signal generation module 14 receives the instruction information transmitted by the imaging device, analyzes the instruction information, selects a corresponding fixed circuit from the first fixed circuit 144 and the second fixed circuit 145 through the selection circuit 146 according to the analysis result, selectively outputs the number of settings generated by the corresponding fixed circuit, generates a control signal according to the number of settings selectively output, and outputs the control signal to the control terminal 132 of the gate output unit 13.
Specifically, taking the example that the setting number is a two-digit binary number, the control signal generation module 14 is provided with four fixed circuits, the fixed circuit 1 can generate the setting number "00", the fixed circuit 2 can generate the setting number "01", the fixed circuit 3 can generate the setting number "10", and the fixed circuit 4 can generate the setting number "11", the address of the first functional circuit 11 is "0", and the address of the second functional circuit 12 is "1". The control signal generating module 14 receives the instruction information corresponding to the fixed circuit 1, if the fixed circuit 1 is selected to output the set number "00", the periodic level signal with the signal "00" is continuously input through the control terminal 132, the strobe output unit 13 continuously selects the first functional circuit 11 with the address "0" as the circuit for inputting data according to the input signal "00", receives the data of the first functional circuit 11 and outputs the data through the output terminal 131; when the fixed circuit 2 is selected to output the set number "01", the control terminal 132 continuously inputs the periodic level signal of which the signal is "01", and the strobe output unit 13 selects the first functional circuit 11 having the address "0" as the circuit to which data is input, and then selects the second functional circuit 12 having the address "1" as the circuit to which data is input, according to the input signal "01", so that the first functional circuit 11 and the second functional circuit 12 are continuously and alternately selected to receive data and output the data through the output terminal 131.
In another implementation manner, at least two fixed circuits are provided in the control signal generation module 14, before the chip 1 receives the instruction information sent by the imaging device, the selection circuit 146 generates a selection signal, selects a fixed circuit to generate a set number, generates a control signal according to the set number selected and output, and outputs the control signal to a plurality of functional circuits (a first functional circuit and a second functional circuit in this embodiment) and the control terminal 132 of the strobe output unit 13, respectively, so that the plurality of functional circuits know the control signal that can output correct data, and when the control signal generation module 14 receives the instruction information sent by the imaging device, the strobe output unit 13 strobes the plurality of functional circuits to obtain correct data according to the control signal received at the control terminal 132.
The integrated circuit 10111 provided by the embodiment of the present invention generates a corresponding set number by setting a plurality of fixed circuits, and generates a control signal according to the set number, so that the selection output unit continuously or alternatively gates a certain functional circuit according to the control signal, thereby enhancing the complexity of the circuit structure, and even if the circuit is reversely cracked, it is difficult to analyze the generation rule of the set number, and the method for reading out the correct imaging data cannot be cracked, thereby achieving the purpose of protecting the logic function of the chip circuit from being cracked.
Fig. 5 is a schematic structural diagram of an integrated circuit 10111 according to another embodiment of the present invention, as shown in fig. 5, a detailed description is made on a generation process of a control signal based on the above-mentioned embodiment, for example, based on the embodiment shown in fig. 3, and specifically, the control signal generation module 14 includes: at least one random circuit 147.
The random circuit 147 is connected to the gate output unit 13, and configured to generate a random number and send the random number to the gate output unit 13 as a control signal.
In practical applications, when the control signal is a non-periodic continuous level signal, the control signal may be generated according to a random number, which may be a multi-bit binary data.
In an implementation manner, the random circuit 147 in the control signal generation module 14 may generate random numbers without regularity or according to a certain numerical rule, and the random circuit 147 may include a plurality of sub-random circuits 147, each sub-random circuit 147 having corresponding instruction information. The control signal generation module 14 receives the instruction information from the imaging device, analyzes the instruction information, selects the corresponding sub-random circuit 147 according to the analysis result, and generates a continuous level signal according to the random number generated by the sub-random circuit 147 and outputs the continuous level signal to the control end of the gate output unit 13.
Specifically, taking the example that the random number is a multi-bit binary number, the control signal generating module 14 is provided with a random circuit 147, the random circuit 147 can generate an irregular random number, a random number conforming to an odd check rule, a random number conforming to an even check rule, or the like, the address of the first functional circuit 11 is "1", and the address of the second functional circuit 12 is "0". The control signal generating module 14 receives an instruction to generate a random number conforming to the odd parity rule, the random circuit 147 outputs the random number conforming to the odd parity rule, for example, the generated random number is "1100100101", a level signal of "1100100101" is input through the control terminal 132, when a signal input through the control terminal is "1", the first functional circuit 11 with an address of "1" is selected as a circuit to which data is input, when a signal input through the control terminal is "0", the second functional circuit 12 with an address of "0" is selected as a circuit to which data is input, and the required functional circuits are alternately selected according to the control signal, and data is output through the output terminal 131.
In another implementation manner, at least one random circuit 147 is disposed in the control signal generation module 14, before the chip 1 receives the instruction information sent by the imaging device, the random circuit 147 randomly generates a random number, generates a control signal according to the random number, and outputs the control signal to the plurality of functional circuits (the first functional circuit and the second functional circuit in this embodiment) and the control terminal 132 of the strobe output unit 13 respectively, so that the plurality of functional circuits know the control signal that can output correct data, and when the control signal generation module 14 receives the instruction information sent by the imaging device, the strobe output unit 13 strobes the plurality of functional circuits to obtain correct data according to the control signal received at the control terminal 132.
The integrated circuit 10111 provided in the embodiment of the present invention generates the corresponding random number by setting the random circuit 147, and generates the control signal according to the random number, so that the selected output unit continuously gates the same functional circuit or different functional circuits according to the control signal, and compared with a method in which a fixed circuit is used to generate a set number, the random number generated by the random circuit makes the control signal more complicated, and even if the circuit is reversely cracked, the random number is read, but since the random numbers corresponding to the same instruction information may be different, the rule between the random numbers is more difficult to find, it is difficult to analyze the corresponding relationship between the random number and the instruction information, and it is impossible to crack the method for reading the correct imaging data, thereby better protecting the logic function of the chip circuit from being cracked.
The difference between the control signal generated by the set number and the control signal generated by the random number in the above-mentioned embodiment of fig. 4 and the embodiment of fig. 5 is that: the control signal is generated by the setting number, if the setting number is generated by the fixed circuit, because the setting number generated by the fixed circuit is fixed, a plurality of fixed circuits are required to be arranged when different control signals are required to be generated; the random number is generated by a random circuit by a random number generation control signal, and since data generated by the random circuit is not fixed, the above function can be achieved by only providing one random circuit 147.
Fig. 6 is a schematic structural diagram of an integrated circuit 10111 according to another embodiment of the invention, as shown in fig. 6, the embodiment is obtained by combining the embodiments shown in fig. 4 and fig. 5. In the present embodiment, the control signal may be generated by a fixed circuit to generate a set number, or may be generated by a random circuit 147 to generate a random number. For a specific generation principle, reference may be made to the embodiments shown in fig. 4 and fig. 5, which are not described herein again.
The present embodiment can respond to various kinds of instruction information by providing the fixed circuit and the random circuit 147 at the same time. The application range of the integrated circuit 10111 is expanded.
Fig. 7 is a schematic structural diagram of an integrated circuit 10111 according to yet another embodiment of the present invention, as shown in fig. 7, on the basis of the foregoing embodiment, for example, on the basis of fig. 4, a generation process of a control signal in this embodiment is described as an example, specifically, the control signal generation module 14 includes: a non-volatile memory unit 142 and a data loading circuit 143.
The nonvolatile memory unit 142 is connected to the data loading circuit 143, and is configured to store the control data and send the control data to the data loading circuit 143. The nonvolatile memory unit 142 stores at least one set number or at least one set data of the control data for generating the control signal, is set to have a write port, is not set to have a read port, i.e., is set to support only a data write operation, does not support a read operation, further improves confidentiality of data, so that the data stored therein is not easily read by an external device (a data read device for reverse engineering). The control data is written and stored by the manufacturer when the chip is manufactured, the setting number can be binary data of at least one bit, and the setting data can be multi-bit binary data.
And a data loading circuit 143, connected to the strobe output unit 13, for selecting a corresponding set number in the nonvolatile memory unit 142 to generate a periodic control signal, or selecting a corresponding set data to generate a corresponding control signal, and sending the control signal to the strobe output unit 13.
In an implementation manner, the nonvolatile storage unit 142 stores a plurality of setting numbers or setting data corresponding to the instruction information of the imaging device, and the data loading circuit 143, upon receiving the instruction information of the imaging device, selects the corresponding setting numbers or setting data according to the instruction information to generate a control signal and sends the control signal to the control terminal 132 of the strobe output unit 13.
Specifically, the setting numbers are stored in the nonvolatile memory unit 142, the setting numbers "01" and "11" are stored in the nonvolatile memory unit 142 of the control signal generation module 14, the address of the first functional circuit 11 is "1", the address of the second functional circuit 12 is "0", the data load circuit 143 selects the setting number "01" in the nonvolatile memory unit 142 upon receiving the instruction corresponding to the setting number "01", the control terminal 132 continuously inputs a periodic level signal with a signal of "01", and the gate output unit 13 selects the second functional circuit 12 with an address of "0" as a circuit to which data is input, and then selects the first functional circuit 11 with an address of "1" as a circuit to which data is input, according to the input periodic signal of "01", alternately selects and receives data of the first functional circuit 11 and the second functional circuit 12, and outputs the data through the output terminal 131.
Specifically, the setting data "01101110" and "10011000" are stored in the nonvolatile memory unit 142 of the control signal generation module 14, the address of the first functional circuit 11 is "1", the address of the second functional circuit 12 is "0", the data loading circuit 143 selects the setting data "10011000" in the nonvolatile memory unit 142 upon receiving an instruction corresponding to the setting number "10011000", the gate output unit 13 sequentially selects functional circuits having addresses of "1", "0", "1", "0" and "0" as circuits to which data is input, based on the input signal "10011000", as a level signal whose signal is "10011000" is input through the control terminal 132, thus, the data of the first functional circuit 11 and the second functional circuit 12 are alternately selected and received and the data is output through the output terminal 131.
In another implementation manner, the nonvolatile storage unit 142 stores a plurality of setting numbers or a plurality of setting data, the data loading circuit 143 selects the setting numbers or the setting data stored in the nonvolatile storage unit 142 and generates a control signal before receiving the instruction information of the imaging device, outputs the control signal to the plurality of functional circuits (the first functional circuit and the second functional circuit in this embodiment) and the control terminal 132 of the strobe output unit 13, respectively, makes the plurality of functional circuits know the control signal that can output the correct data, and when the data loading circuit 143 receives the instruction information transmitted by the imaging device, the strobe output unit 13 strobes the plurality of functional circuits to acquire the correct data according to the control signal received at the control terminal 132.
Optionally, the control signal generating module 14 further includes: and a data writing circuit. The data writing circuit is connected to the nonvolatile memory unit 142, and is configured to write a set number or set data to the nonvolatile memory unit 142 during chip manufacturing.
The integrated circuit 10111 according to the embodiment of the present invention selects the setting number or the setting data stored in the nonvolatile memory unit 142 in advance to generate the control signal, so that the selection output unit sequentially gates the same functional circuit or different functional circuits according to the control signal. Compared with the above-mentioned generation of the set number by the fixed circuit or the generation of the random number by the random circuit, the nonvolatile memory cell of the present embodiment stores the set number and is set to write only the unreadable data, and the data for generating the control information can be protected better.
As shown in fig. 4-7, on the basis of the above embodiments, in order to increase the data reading speed in this embodiment, a volatile register unit 141 is further provided, specifically: the control signal generation block 14 includes a volatile register unit 141.
The volatile register unit 141 has one end connected to the data loading circuit 143, the selection circuit 146, or the random circuit 147, and the other end connected to the strobe output unit 13, and is configured to buffer the control signal output by the data loading circuit 143 and send the buffered control signal to the strobe output unit 13.
Based on the volatile register unit 141, the operation of the integrated circuit 10111 is as follows: the control signal generation module 14 receives the instruction information sent by the imaging device, analyzes the instruction information to obtain the type of the instruction information, and selects and generates a random number or a set number according to the instruction information, or the control signal generation module 14 generates the random number or the set number before receiving the instruction information sent by the imaging device; the random number or the setting number is stored in the volatile register unit 141, and the control signal generation module 14 generates a continuous level signal based on the random number or the setting number in the volatile register unit 141 and inputs the continuous level signal to the control terminal 132 of the strobe output unit 13; finally, the gate output unit 13 selects the functional circuit connected to each input terminal according to the level signal, and outputs the imaging data input to the corresponding input terminal by the selected functional circuit to the imaging device through the output terminal 131.
It should be noted that the instruction information sent by the image forming apparatus corresponds to different operations of the image forming apparatus, for example, the first instruction information sent may correspond to a printing operation, and the second instruction information sent may correspond to an image forming cartridge verifying operation. After the imaging device is started up and before the imaging device is shut down, the imaging box chip 1011 can execute the operation corresponding to a certain instruction for multiple times, or the imaging box chip 1011 can execute the operation corresponding to a certain instruction only once. When the imaging apparatus needs to repeatedly execute the operation of the same instruction, data needs to be regenerated each time the instruction is received, and the data is stored in the volatile register unit 141, that is, the data used each time the same instruction is executed is not necessarily the same; or because the volatile register unit 141 stores the corresponding random number or the set number generated by executing the instruction for the first time, the data stored in the volatile register unit 141 can be directly acquired when the instruction is executed each time, the instruction does not need to be analyzed again to regenerate the data, and the time required for executing the operation each time is reduced.
The integrated circuit 10111 provided by the embodiment of the present invention is configured with the volatile register unit 141 in the control signal generation module 14, and buffers the generated control signal in the volatile register unit 141, and because the volatile register unit has a performance of fast reading speed, the speed of reading the control signal from the control signal generation module 14 by the selection output unit can be increased, and for an operation that needs to execute the same instruction for multiple times, the response time of the imaging cartridge chip 1011 to the instruction information sent by the imaging device can be reduced, and the user experience is improved. In addition, when the imaging device is powered off, the power supply to the chip is stopped, and the data in the volatile register unit 141 can be erased when the chip is powered off, so that the data confidentiality is improved.
The embodiments based on fig. 4-6 each have a nonvolatile memory cell 142 and a data loading circuit 143 on the basis of the volatile register unit 141, and the nonvolatile memory cell 142 and the data loading circuit 143 are located between the selection circuit 146 and the volatile register unit 141 or between the random circuit 147 and the volatile register unit 141.
Therefore, the working process of the integrated circuit 10111 provided in fig. 4-7 in this embodiment is as follows: the control signal generation module 14 receives the instruction information sent by the imaging device, analyzes the instruction information to obtain the type of the instruction information, and selects and generates a random number or a set number according to the instruction information, or the control signal generation module 14 generates the random number or the set number before receiving the instruction information sent by the imaging device; then, writing the setting number or random number generated by the internal circuit into the nonvolatile memory unit 142, preferably, the nonvolatile memory unit 142 outputs data in parallel, and the output data width is at least 32 bits, the data loading circuit 143 receives the data in the nonvolatile memory unit 142 and loads the data into the volatile register unit 141, the control signal generating module 14 generates a continuous level signal based on the data in the volatile register unit 141, and inputs the continuous level signal into the strobe output unit 13 through the control terminal 132; finally, the gate output unit 13 selects a corresponding functional circuit from the input terminal according to the level signal, acquires data in the functional circuit, and outputs the acquired data through the output terminal 131.
If the integrated circuit 10111 is first installed in the printing apparatus and powered on (i.e., power is supplied to the chip) until the end of the life of the chip, the set number or the random number used in each subsequent operation is the same, a set number or a random number may be generated and stored in the nonvolatile storage unit 142 when the control signal generation module 14 first receives instruction information corresponding to the operation, or generates a set number or a random number according to a predetermined setting and stores in the nonvolatile storage unit 142 before the control signal generation module 14 receives the instruction information, since the nonvolatile memory cell 142 does not erase data stored therein even if power is off, therefore, the data stored in the nonvolatile memory unit 142 can be directly acquired when the instruction operation is executed each time, the instruction does not need to be analyzed again to regenerate the data, and the time required for executing the operation each time is reduced.
The integrated circuit 10111 according to the embodiment of the present invention generates a corresponding setting number or random number by instruction information or a predetermined setting, stores the setting number or random number in the nonvolatile memory unit, loads the setting number or random number in the volatile register unit 141 by the data loading circuit 143, and generates a control signal based on data in the volatile register unit 141, thereby implementing a data selection function of the strobe output unit 13. According to the embodiment, on the basis of protecting the logic function of the chip circuit from being broken and improving the operation efficiency, the nonvolatile storage unit is added, and due to the existence of the nonvolatile storage unit, once a problem occurs in the operation executing process, an interrupt request can be sent immediately, and the nonvolatile storage unit can be used for analyzing the reason of operation errors.
The embodiment of the present invention further provides an integrated circuit, wherein the control signal generating module 14 includes a nonvolatile storage unit 142 and a plurality of fixed circuits, a plurality of setting data are stored in the nonvolatile storage unit 142, one setting data corresponds to one fixed circuit, the fixed circuit is selected by selecting the setting data, and the fixed circuit inputs the generated control signal to the input end 132 of the strobe output unit 13.
The embodiment of the present invention further provides an imaging cartridge chip 1011, which includes the integrated circuit 10111 provided in any one of the above embodiments. Optionally, when the PCB layout of the chip is designed, the metal wiring of the data signal output circuit of the nonvolatile memory unit 142 is designed to be located at the bottom layer, and meanwhile, a high-level metal is covered on the data signal output circuit as a protective layer, so that the output circuit is more concealed, the structural difficulty of the PCB layout circuit design of the chip is increased, even if the chip is subjected to destructive research, it is difficult to analyze and clearly identify the internal circuit of the chip, and the logic function of the chip circuit is further protected from being cracked.
The embodiment of the invention also provides an imaging box, which comprises the imaging box chip 1011 provided by any one of the embodiments. The imaging box that this embodiment provided is through setting up this imaging box chip 1011, effectively prevents that imaging box chip 1011 from being analyzed out the internal circuit logic by reverse engineering, can realize encrypting imaging data, and then avoids imaging box relevant data to be stolen.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced or combined; and the replacement or combination does not make the essence of the corresponding technical solution depart from the scope of the technical solution of the embodiments of the present invention.
Claims (14)
1. An integrated circuit disposed on a chip, comprising: the system comprises at least one gating output unit, a control signal generation module and at least two functional circuits; the at least two functional circuits include a first functional circuit and a second functional circuit;
the gating output unit comprises at least one control end, at least one output end and at least two input ends; the control end is connected with the control signal generation module, the at least two input ends comprise a first input end and a second input end, the first input end is connected with the first functional circuit, and the second input end is connected with the second functional circuit;
the control signal generation module is used for generating a control signal and inputting the control signal to the gating output unit through the control end;
the first functional circuit is configured to acquire first imaging data, process the first imaging data to acquire processed first imaging data, and output the processed first imaging data to the first input end;
the second functional circuit is configured to acquire second imaging data, process the second imaging data to obtain processed second imaging data, and output the processed second imaging data to the second input end;
and the gating output unit is used for receiving the control signal, selecting the processed first imaging data and the processed second imaging data under the control of the control signal, obtaining third imaging data, wherein the third imaging data is composed of at least one part of the processed first imaging data and at least one part of the processed second imaging data, and sending the third imaging data to the imaging device through the output end.
2. The integrated circuit of claim 1,
the control signal generation module is specifically used for receiving instruction information and generating the control signal according to the instruction information;
alternatively, the control signal is generated according to a predetermined setting before the instruction information is received.
3. The integrated circuit of claim 2, wherein the control signal generation module comprises: at least two fixed circuits and a selection circuit;
the selection circuit is arranged between the at least two fixed circuits and the control end of the gating output unit and used for generating selection signals, selecting the at least two fixed circuits according to the selection signals, generating the control signals according to the set number generated by the selected fixed circuits and sending the control signals to the control end of the gating output unit.
4. The integrated circuit of claim 2, wherein the control signal generation module comprises: at least one random circuit;
the random circuit is connected with the control end of the gating output unit and used for generating a random number and sending the random number to the control end of the gating output unit as the control signal.
5. The integrated circuit of claim 3 or 4, wherein the control signal generation module further comprises: a volatile register unit;
and one end of the volatile register unit is connected with the selection circuit or the random circuit, and the other end of the volatile register unit is connected with the control end of the gating output unit, and the volatile register unit is used for registering data generated by the selection circuit or the random circuit, generating a control signal according to the data and sending the control signal to the control end of the gating output unit.
6. The integrated circuit of claim 5, wherein the control signal generation module further comprises: a nonvolatile memory cell and a data loading circuit;
one end of the nonvolatile storage unit is connected with the selection circuit or the random circuit, the other end of the nonvolatile storage unit is connected with one end of the data loading circuit, the other end of the data loading circuit is connected with the volatile register unit, the nonvolatile storage unit is used for storing data generated by the selection circuit or the random circuit and sending the data to the volatile register unit through the data loading circuit for registering, so that the volatile register unit generates a control signal according to the data and sends the control signal to the control end of the strobe output unit.
7. The integrated circuit of claim 2, wherein the control signal generation module comprises: a nonvolatile memory cell and a data loading circuit;
the nonvolatile storage unit is connected with one end of the data loading circuit and is used for storing at least one set number or set data, and the set number or set data is written and stored by a manufacturer when a chip is manufactured;
and the other end of the data loading circuit is connected with the control end of the strobe output unit and is used for selecting the set number or set data in the nonvolatile storage unit, generating the control signal according to the set number or set data and sending the control signal to the control end of the strobe output unit.
8. The integrated circuit of claim 7, wherein the control signal generation module further comprises: a data write circuit;
the data writing circuit is connected with the nonvolatile storage unit and used for writing the at least one set number or set data into the nonvolatile storage unit when the chip is manufactured.
9. The integrated circuit of claim 8, wherein the non-volatile memory cells are configured to support only write operations and not read operations.
10. The integrated circuit of claim 9, wherein the control signal generation module further comprises: a volatile register unit;
the volatile register unit is arranged between the data loading circuit and the control end of the strobe output unit and is used for receiving and registering the at least one set number or set data sent by the nonvolatile storage unit through the data loading circuit, generating the control signal according to the at least one set number or set data and sending the control signal to the control end of the strobe output unit.
11. The integrated circuit of claim 3, 4 or 7, wherein the control signal is generated by the control signal generation module according to a predetermined setting before receiving instruction information;
the control signal generating module is further configured to send the control signal to the at least two functional circuits, so that the at least two functional circuits perform data processing according to the control signal.
12. The integrated circuit according to claim 6 or 7, wherein the nonvolatile memory cell includes a data signal output circuit;
the metal wiring of the data signal output circuit is designed to include a lower layer connection wiring and a higher layer protection wiring overlying the lower layer wiring.
13. A chip provided with an integrated circuit as claimed in any one of claims 1 to 12.
14. An imaging cartridge detachably mountable to an imaging apparatus, wherein said imaging cartridge is provided with the chip of claim 13.
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Address after: 519060 building 01, 83 Guangwan street, Xiangzhou District, Zhuhai City, Guangdong Province Patentee after: Jihai Microelectronics Co.,Ltd. Address before: 519060 building 01, 83 Guangwan street, Xiangzhou District, Zhuhai City, Guangdong Province Patentee before: APEX MICROELECTRONICS Co.,Ltd. |