CN206147606U - Interface circuit - Google Patents
Interface circuit Download PDFInfo
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- CN206147606U CN206147606U CN201620853193.XU CN201620853193U CN206147606U CN 206147606 U CN206147606 U CN 206147606U CN 201620853193 U CN201620853193 U CN 201620853193U CN 206147606 U CN206147606 U CN 206147606U
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Abstract
The utility model provides an interface circuit, including gate, input circuit and output circuit, input circuit includes an input circuit and the 2nd input circuit, and the gate is connected respectively with an input circuit and the 2nd input circuit, and an input circuit or the 2nd input circuit and output circuit intercommunication are selected to the gate under a controlling means's control. The the first signal that controlling means sent was received to the gate, was connected with a communication mode communication according to a first signal gating input circuit and output circuit. When the second signal that controlling means sent was received to the gate, according to the 2nd input circuit of second signal gating and output circuit with second newsletter mode communication connection. The embodiment of the utility model provides an interface circuit has solved the complicated problem of interface converting among the prior art.
Description
Technical field
The utility model is related to circuit field, in particular to a kind of interface circuit.
Background technology
Interface circuit is between computer, between computer and ancillary equipment, connection to be played between computer-internal part and is made
Logic circuit.Interface circuit is the bridge that CPU and external equipment carry out information exchange.It is typically only capable to realize a kind of communication side
The transmission of formula, when interface circuit needs to carry out different communications, when must change corresponding interface, troublesome poeration, it has not been convenient to use.
Utility model content
The purpose of this utility model be provide it is a kind of supports difference communication modes interface circuit.
A kind of interface circuit that the utility model is provided, including gating circuit, input circuit and output circuit, the input
Circuit includes the first input circuit and the second input circuit, and the gating circuit selects described the under the control of a control device
One input circuit or the second input circuit are connected；
When the gating circuit receives the first signal that institute's control device sends, according to first signal gating
First input circuit is communicated to connect with the output circuit with the first communication modes；
When the gating circuit receives the secondary signal that the control device sends, institute is gated according to the secondary signal
State the second input circuit to communicate to connect with the second communication modes with the output circuit.
Optionally, the output circuit includes the first output circuit and the second output circuit, and the gating circuit includes one
Level gating circuit and two grades of gating circuits；
The control device is connected with the one-level gating circuit, the one-level gating circuit and first input circuit
Connection and first output circuit connect respectively；
Two grades of gating circuits are connected with the one-level gating circuit, and two grades of gating circuits and described second are input into
Circuit and second output circuit connect respectively；
First input circuit is connected with first output circuit, and second input circuit and described second is exported
Circuit connects；
The one-level gating circuit when first signal that the control device sends is received, according to described first
First input circuit described in signal gating is communicated to connect with first output circuit with first communication modes；
The one-level gating circuit when receiving the control device and sending secondary signal, according to the secondary signal to
Two grades of gating circuits send the 3rd signal, two grades of gating circuits, second input according to the 3rd signal gating
Circuit is communicated to connect with second output circuit with second communication modes.
Optionally, first input circuit includes HDMI, and second input circuit includes logical
Asynchronous receiving-transmitting coffret, first output circuit and second output circuit is used to include HDMI.
Optionally, first input circuit also includes the first data input circuit and the first signal input circuit, described
Second input circuit also includes the second data input circuit and secondary signal input circuit；
First output circuit also includes the first data output circuit and the first signal output apparatus, second output
Circuit also includes the second data output circuit and secondary signal output circuit；
First data input circuit is connected with first data output circuit, first signal input circuit with
First signal output apparatus are connected, first data input circuit, the first signal input circuit, the first data output electricity
Road and the first signal output apparatus are connected with the one-level gating circuit；
Second data input circuit is connected with second data output circuit, the secondary signal input circuit with
The secondary signal output circuit is connected, second data input circuit, secondary signal input circuit, the output of the second new data
Circuit and secondary signal output circuit are connected with two grades of gating circuits.
Optionally, the one-level gating circuit includes the first triode, the first FET and the second FET；
The base stage of first triode is connected with the control device, colelctor electrode is connected with the first external power supply, launches
Pole is grounded；
The grid of first FET is connected with first external power supply, drains and first data input electricity
Road connection, source electrode are connected with first data output circuit；
The grid of second FET is connected with first external power supply, drains and first signal input electricity
Road connection, source electrode are connected with first signal output apparatus.
Optionally, the one-level gating circuit also includes first resistor, second resistance and 3rd resistor, the second resistance
It is connected between the base stage of first triode and the control device, described first resistor one end connects with the 3rd external power supply
Connect, the other end is connected between the second resistance and the control device, it is external that the 3rd resistor is connected to described first
Between the grid of power supply and first FET.
Optionally, first input circuit also includes the 4th resistance and the 5th resistance, and the 4th resistance is connected to institute
State between the drain electrode of the first FET and the first data input port, the 5th resistance is connected to second FET
Between drain electrode and the first signal input.
Optionally, two grades of gating circuits include the second triode, the 3rd FET and the 4th FET, described
The base stage of the second triode is connected with the colelctor electrode of first triode, colelctor electrode is connected with the second external power supply, emitter stage
Ground connection.
The grid of the 3rd FET is connected with second external power supply, drains and second data input electricity
Road connection, source electrode are connected with second data output circuit.
The grid of the 4th FET is connected with second external power supply, drains and secondary signal input electricity
Road connection, source electrode are connected with the secondary signal output circuit.
Optionally, two grades of gating circuits also include the 6th resistance and the 7th resistance.6th resistance is connected to institute
State between the colelctor electrode of the first triode and the base stage of second triode.It is external that 7th resistance is connected to described second
Between the grid of power supply and the 3rd FET.
Optionally, second input circuit also includes the 8th resistance and the 9th resistance, and the 8th resistance is connected to institute
State between drain electrode and second data input port of the 3rd FET, the 9th resistance is connected to the 4th FET
Between drain electrode and secondary signal input port.
In the utility model embodiment, by the ingenious integrated of gating circuit, input circuit, output circuit etc. and design,
Enable the gating circuit receive control device transmission the first signal when, according to first signal gating
First input circuit, so that first input circuit is communicated to connect with the output circuit with the first communication modes.The choosing
When circuit passband receives the secondary signal that the control device sends, according to secondary signal gating the second input electricity
Road, so that second input circuit is communicated to connect with the output circuit with the second communication modes.So as to pass through an interface
Two input interfaces " multiplexing " of circuit realiration.Efficiently solve the problems, such as interface conversion complex operation.
To enable above-mentioned purpose of the present utility model, feature and advantage to become apparent, preferred embodiment cited below particularly, and
Coordinate appended accompanying drawing, be described in detail below.
Description of the drawings
In order to be illustrated more clearly that the technical scheme of the utility model embodiment, below will be to use needed for embodiment
Accompanying drawing be briefly described, it will be appreciated that the following drawings illustrate only some embodiments of the present utility model, therefore should not be by
Regard the restriction to scope as, for those of ordinary skill in the art, on the premise of not paying creative work, may be used also
To obtain other related accompanying drawings according to these accompanying drawings.
Fig. 1 shows a kind of structured flowchart of interface circuit that the utility model embodiment is provided.
Fig. 2 shows a kind of another structured flowchart of interface circuit that the utility model embodiment is provided.
Fig. 3 shows a kind of another structured flowchart of interface circuit that the utility model embodiment is provided.
Fig. 4 shows a kind of one-level gating circuit figure of interface circuit that the utility model embodiment is provided.
Fig. 5 shows a kind of two grades of gating circuit figures of interface circuit that the utility model embodiment is provided.
Fig. 6 shows a kind of circuit theory diagrams of interface circuit that the utility model embodiment is provided.
In above-mentioned accompanying drawing, each reference is：
10- interface circuits；
100- gating circuits, 110- one-level gating circuits, bis- grades of gating circuits of 120-；
200- input circuits, the input circuits of 210- first, the data input circuits of 212- first, the signal inputs of 214- first electricity
Road, the input circuits of 220- second, the data input circuits of 222- second, 224- secondary signal input circuits；
300- output circuits, the output circuits of 310- first, the data output circuits of 312- first, the signal outputs of 314- first electricity
Road, the output circuits of 320- second, the data output circuits of 322- second, 324- secondary signal output circuits, 20- control devices.
Specific embodiment
It is new below in conjunction with this practicality to make purpose, technical scheme and the advantage of the utility model embodiment clearer
Accompanying drawing in type embodiment, is clearly and completely described, it is clear that retouched to the technical scheme in the utility model embodiment
The embodiment stated is a part of embodiment of the present utility model, rather than the embodiment of whole.Generally retouch in accompanying drawing herein
The component of the utility model embodiment stated and illustrate can be arranged and designed with a variety of configurations.
Therefore, the detailed description of embodiment of the present utility model below to providing in the accompanying drawings is not intended to limit requirement
The scope of the present utility model of protection, but it is merely representative of selected embodiment of the present utility model.Based in the utility model
Embodiment, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, all
Belong to the scope of the utility model protection.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined in individual accompanying drawing, then it need not be further defined and is explained in subsequent accompanying drawing.Of the present utility model
In description, term " first, second, third, fourth etc. is only used for distinguishing description, and it is not intended that being or implying relatively heavy
The property wanted.
In description of the present utility model, unless otherwise clearly defined and limited, term " setting ", " connected ", " company
Connect " should be interpreted broadly, for example, it may be being fixedly connected, or being detachably connected, or it is integrally connected；It can be machine
Tool connects, or electrically connects；Can be joined directly together, it is also possible to be indirectly connected to by intermediary, can be two units
Connection inside part.For the ordinary skill in the art, can understand that above-mentioned term is new in this practicality with concrete condition
Concrete meaning in type.
As shown in figure 1, the utility model provides a kind of interface circuit 10, including gating circuit 100, input circuit 200
With output circuit 300.
Wherein, the input circuit 200 includes the first input circuit 210 and the second input circuit 220.The gating circuit
100 are connected respectively with the first input circuit 210 and the second input circuit 220.The input electricity of first input circuit 210 and second
Road 220 is connected with the output circuit 300, and the gating circuit 100 is connected with control device 20.
During work, the control device 20 to the gating circuit sends the first signal or secondary signal.The gating electricity
When road 100 receives the first signal of the transmission of the control device 20, the first input electricity according to first signal gating
Road 210 is with the output circuit 300 with the communication connection of the first communication modes.The gating circuit 100 receives the control dress
When putting the secondary signal of 20 transmissions, second input circuit 220 and the output circuit 300 are gated according to the secondary signal
With the communication connection of the second communication modes.
In the present embodiment, the first signal secondary signal is high level signal or low level signal, optionally, described
Control device 20 is micro-control unit (Microcontroller Unit；MCU).
As shown in Fig. 2 optional, the gating circuit 100 includes one-level gating circuit 110 and two grades of gating circuits 120,
The one-level gating circuit 110 is connected with two grades of gating circuits 120.The output circuit 300 includes the first output circuit
310 and second output circuit 320, the control device 20 is connected with the one-level gating circuit 110, the one-level gating circuit
110 are connected respectively with first input circuit 210 and first output circuit 310.Two grades of gating circuits 120 and institute
State one-level gating circuit 110 to connect, two grades of gating circuits 120 and second input circuit 220 and described second are exported
Circuit 320 connects respectively.First input circuit 210 is connected with first output circuit 310, second input circuit
220 are connected with second output circuit 320.
The one-level gating circuit 110 receive the control device 20 transmission first signal when, according to institute
First the first input circuit of signal gating 210 is stated with first output circuit 310 with the communication connection of the first communication modes.It is described
One-level gating circuit 110 when receiving the control device 20 and sending secondary signal, according to the secondary signal to described two
Level gating circuit 120 sends the 3rd signal, two grades of gating circuits 120, second input according to the 3rd signal gating
Circuit 220 is communicated to connect with second output circuit 320 with second communication modes.Optionally, the 3rd signal is
Low level signal.In the present embodiment, optionally, first input circuit 210 and HDMI (High
Definition Multimedia Interface, HDMI) connection.Second input circuit 220 is passed with universal asynchronous receiving-transmitting
Defeated device interface (Universal Asynchronous Receiver/Transmitter, UART) connection, the first output electricity
The output circuit 320 of road 310 and second is connected with HDMI.
As shown in figure 3, first input circuit 210 also includes the first data input circuit 212 and the first signal input
Circuit 214, second input circuit 220 also includes the second data input circuit 222 and secondary signal input circuit 224.Institute
Stating the first output circuit 310 also includes the first data output circuit 312 and the first signal output apparatus 314, second output
Circuit 320 also includes the second data output circuit 322 and secondary signal output circuit 324.First data input circuit 212
It is connected with first data output circuit 312, first signal input circuit 214 and first signal output apparatus
314 are connected, first data input circuit 212, the first signal input circuit 214, the first data output circuit 312 and first
Signal output apparatus 314 are connected with the one-level gating circuit 110.Second data input circuit 222 and the described second number
Connect according to output circuit 322, the secondary signal input circuit 224 is connected with the secondary signal output circuit 324, described
Two data input circuits 222, secondary signal input circuit 224, the second data output circuit 322 and secondary signal output circuit
324 are connected with two grades of gating circuits 120.
With reference to shown in Fig. 4, the one-level gating circuit 110 includes the first triode Q1, the first FET Q11 and second
FET Q12.The base stage of the first triode Q1 is connected with the control device 20, colelctor electrode and the first external power supply U1
Connected, grounded emitter.The grid of the first FET Q11 is connected with the first external power supply U1, drain with it is described
First data input circuit 212 connects, source electrode is connected with first data output circuit 312.The second FET Q12
Grid and first external power supply be connected U1, drain electrode be connected with first signal input circuit 214, source electrode and described the
One signal output apparatus 314 connect.
When the control device 20 sends low level signal to the base stage of the first triode Q1, the one or three pole
Pipe Q1 ends, and the first FET Q11 and the second FET Q12 is connected with the first external power supply U1.Described
When one triode Q1 ends, the first FET Q11 and the second FET Q12 is turned on, therefore, first field-effect
The drain electrode of pipe Q11 and the second FET Q12 is connected with source electrode, realizes that first data input port is defeated with first data
Data transfer between outlet, the signal transmission between first signal input and first signal output, so as to
Realize the first communication.
In the present embodiment, optionally, first communication modes are audio frequency, transmission of video.Optionally, the described 1st
Pole pipe Q1 is NPN type triode, and the first FET Q11 and the second FET Q12 is NPN type FET.It is described
The voltage of the first external power supply U1 is not specifically limited, as long as the first FET Q11 and the second FET Q12 can be made
Conducting.In the present embodiment, optionally, the voltage of the first external power supply U1 is 12V.
Optionally, the one-level gating circuit 110 also includes first resistor R1, second resistance R2 and 3rd resistor R3.Institute
State second resistance R2 to be connected between the base stage of the first triode Q1 and the control device 20.First resistor R1 mono-
End is connected with the 3rd external power supply U3, and the other end is connected between second resistance R2 and the control device 20.Described
Three resistance R3 are connected between the grid of the first external power supply U1 and the first FET Q11.In the present embodiment,
First resistor R1 is connected with the 3rd external power supply U3, makes to receive high level during the first triode Q1 original states
Signal.
In the present embodiment, optionally, the 3rd external power supply U3 voltages are 3.3 volts, second resistance R2 and the
Three resistance R3 play a part of step-down in interface circuit 10.Optionally, first resistor R1, second resistance R2 and the 3rd are electric
The resistance of resistance R3 is 4.7 kilo-ohms.
With reference to shown in Fig. 5, two grades of gatings, 120 circuits include the second triode Q2, the 3rd FET Q13 and the 4th
FET Q14.The base stage of the second triode Q2 is connected with the colelctor electrode of the first triode Q1, colelctor electrode and second
External power supply U2 is connected, grounded emitter.The grid of the 3rd FET Q13 is connected with the second external power supply U2,
Drain electrode is connected with second data input circuit 222, source electrode is connected with second data output circuit 322.Described 4th
The grid of FET Q14 is connected with the second external power supply U2, drain electrode is connected with the secondary signal input circuit 224,
Source electrode is connected with the secondary signal output circuit 324.
It should be noted that the second triode Q2 is NPN type triode, the 3rd FET Q13 and the 4th
FET Q14 is NPN type FET.When realizing first communication, the control device 20 is to one-level gating electricity
Road 110 sends low level, the first triode Q1 cut-offs.The colelctor electrode of the first triode Q1 and second triode
The base stage of Q2 is connected, and the base stage of the second triode Q2 receives high level signal and turns on so that the second triode Q2
Current collection extremely low level, the 3rd FET Q13 and the 4th FET Q14 end, it is impossible to realize that described second is defeated
Enter second communication between the output circuit 320 of circuit 220 and second.When realizing second communication, the control device
20 to the one-level gating circuit 110 sends high level, the first triode Q1 conductings, the base stage of the second triode Q2
For low level, the second triode Q2 cut-offs.The colelctor electrode of the second triode Q2 is connected to the 3rd external power supply U3
High level, the grid of the 3rd FET Q13 and the 4th FET Q14 is connected and turns on the second external power supply U2.
Realize the data transfer of second data input port and second data output, the secondary signal input port with it is described
The signal transmission of secondary signal delivery outlet, so as to realize second communication.
Optionally, second communication is universal asynchronous receiving-transmitting communication.As long as the voltage energy of the second external power supply U2
Make the 3rd FET Q13 and the 4th FET Q14 conductings.In the present embodiment, optionally, outside described second
The voltage for meeting power supply U2 is 12 volts.
Optionally, two grades of gating circuits 120 also include the 6th resistance R6 and the 7th resistance R7.The 6th resistance R6
It is connected between the base stage of the colelctor electrode of the first triode Q1 and the second triode Q2.The 7th resistance R7 connections
Between the grid of the second external power supply U2 and the 3rd FET Q13.The 8th resistance R8 and the 9th resistance
R9 plays a part of in circuit step-down.In the present embodiment, optionally, the resistance of the 6th resistance R6 is 22 kilo-ohms, institute
The resistance for stating the 7th resistance R7 is 10 kilo-ohms.
As shown in fig. 6, first input circuit 210 also includes the 4th resistance R4 and the 5th resistance R5.Described 4th is electric
Resistance R4 is connected between the drain electrode of the first FET Q11 and the first data input port, and the 5th resistance R5 is connected to
Between the drain electrode of the second FET Q12 and the first signal input.Second input circuit 220 also includes that the 8th is electric
Resistance R8 and the 9th resistance R9.The 8th resistance R8 is connected to the drain electrode of the 3rd FET Q13 and the second data input
Between mouthful, the 9th resistance R9 is connected between the drain electrode of the 4th FET Q14 and secondary signal input port.
The 4th resistance R4, the 5th resistance R5, the 8th resistance R8 and the 9th resistance R9 play in circuit the work of step-down
With.In the present embodiment, optionally, the resistance of the 4th resistance R4 and the 5th resistance R5 be 22 Europe, the 8th resistance R8
It is 100 Europe with the resistance of the 9th resistance R9.Optional first data output and the second data output and peripheral hardware
The data input port connection of HDMI, the letter of first signal output and secondary signal delivery outlet and the HDMI
The connection of number input port.
To sum up, the one-level gating circuit 110 is connected with control device 20, and the one-level gating receives the control dress
When putting the low level signal of 20 transmissions, the one-level gating circuit 110 is according to first input of low level signal gating
Circuit 210 so that first input circuit 210 with first output circuit 310 with the first communication modes communication link
Connect.
When the one-level gating circuit 110 receives the high level signal of the transmission of the control device 20, the one-level choosing
Circuit passband 110 gates two grades of gating circuits 120, and sends another low level signal, institute to two grades of gating circuits 120
State two grades of gating circuits 120 and second input circuit 220 is gated according to another low level signal, so that described second is defeated
Enter the output circuit 320 of circuit 220 and second to communicate to connect with second communication modes.
By above-mentioned design, gating circuit 100 can select different input interfaces under the control of control device 20, when
First input circuit 210 selects HDMI, the second input circuit 220 to be capable of achieving to be multiplexed UART functions using HDMI mouths from UART
Circuit.When transmitting different communication signals, without the need for changing interface circuit so that the interface circuit 10 is convenient to be suitable for.
Obviously, those skilled in the art should be understood that the function of above-mentioned the utility model embodiment can be with general
Computing device realizing, they can be concentrated on single computing device, or are distributed in multiple computing devices and are constituted
Network on, alternatively, they can be realized with the executable existing program code of computing device or algorithm, it is thus possible to
It is stored in storage device being performed by computing device, or they is fabricated to respectively each integrated circuit modules,
Or be fabricated to single integrated circuit module to realize by the multiple modules or step in them.So, work(of the present utility model
Can realize that being not restricted to any specific hardware and software combines.
Preferred embodiment of the present utility model is the foregoing is only, the utility model is not limited to, for this
For the technical staff in field, the utility model can have various modifications and variations.It is all it is of the present utility model spirit and principle
Within, any modification, equivalent substitution and improvements made etc. should be included within protection domain of the present utility model.
Claims (10)
1. a kind of interface circuit (10), it is characterised in that including gating circuit (100), input circuit (200) and output circuit
(300), the input circuit (200) includes the first input circuit (210) and the second input circuit (220), the gating circuit
(100) select under the control of a control device (20) first input circuit (210) or the second input circuit (220) with it is defeated
Go out circuit (300) connection；
When the gating circuit (100) receives the first signal of the control device (20) transmission, according to first signal
First input circuit (210) is gated with the output circuit (300) with the communication connection of the first communication modes；
When the gating circuit (100) receives the secondary signal of the control device (20) transmission, according to the secondary signal
Second input circuit (220) is gated with the output circuit (300) with the communication connection of the second communication modes.
2. interface circuit (10) according to claim 1, it is characterised in that the output circuit (300) is defeated including first
Go out circuit (310) and the second output circuit (320), the gating circuit (100) includes one-level gating circuit (110) and two grades of choosings
Circuit passband (120)；
The control device (20) is connected with the one-level gating circuit (110), the one-level gating circuit (110) and described
One input circuit (210) and first output circuit (310) connect respectively；
Two grades of gating circuits (120) are connected with the one-level gating circuit (110), two grades of gating circuits (120) with
Second input circuit (220) and second output circuit (320) connect respectively；
First input circuit (210) is connected with first output circuit (310), second input circuit (220) with
Second output circuit (320) connection；
The one-level gating circuit (110) receive the control device (20) transmission first signal when, according to institute
The first input circuit (210) described in the first signal gating is stated with first output circuit (310) with the communication of the first communication modes
Connection；
The one-level gating circuit (110) receive the control device (20) send secondary signal when, according to described second
Signal to two grades of gating circuits (120) send the 3rd signal, and two grades of gating circuits (120) are according to the 3rd signal
Gate second input circuit (220) to be connected with the communication of the second communication modes with second output circuit (320).
3. interface circuit (10) according to claim 2, it is characterised in that first input circuit (210) is including height
Definition multimedia interface, second input circuit (220) includes universal asynchronous receiving-transmitting transmitter interface, first output
Circuit (310) and second output circuit (320) are including HDMI.
4. interface circuit (10) according to claim 2, it is characterised in that first input circuit (210) also includes
First data input circuit (212) and the first signal input circuit (214), second input circuit (220) also includes second
Data input circuit (222) and secondary signal input circuit (224)；
First output circuit (310) also includes the first data output circuit (312) and the first signal output apparatus (314),
Second output circuit (320) also includes the second data output circuit (322) and secondary signal output circuit (324)；
First data input circuit (212) is connected with first data output circuit (312), first signal input
Circuit (214) is connected with first signal output apparatus (314), and first data input circuit (212), the first signal are defeated
Enter circuit (214), the first data output circuit (312) and the first signal output apparatus (314) and the one-level gating circuit
(110) connect；
Second data input circuit (222) is connected with second data output circuit (322), the secondary signal input
Circuit (224) is connected with the secondary signal output circuit (324), and second data input circuit (222), secondary signal are defeated
Enter circuit (224), the second data output circuit (322) and secondary signal output circuit (324) with described two grades gating (120) electricity
Road connects.
5. interface circuit (10) according to claim 4, it is characterised in that the one-level gating circuit (110) includes
One triode (Q1), the first FET (Q11) and the second FET (Q12)；
The base stage of first triode (Q1) is connected with the control device (20), colelctor electrode and the first external power supply (U1) phase
Even, grounded emitter；
The grid of first FET (Q11) is connected with first external power supply (U1), drains and first data
Input circuit (212) connection, source electrode are connected with first data output circuit (312)；
The grid of second FET (Q12) is connected with first external power supply (U1), drains and first signal
Input circuit (214) connection, source electrode are connected with first signal output apparatus (314).
6. interface circuit (10) according to claim 5, it is characterised in that the one-level gating circuit also includes that first is electric
Resistance (R1), second resistance (R2) and 3rd resistor (R3), the second resistance (R2) is connected to first triode (Q1)
Between base stage and the control device (20), described first resistor (R1) one end is connected with the 3rd external power supply (U3), the other end
It is connected between the second resistance (R2) and the control device (20), the 3rd resistor (R3) is connected to outside described first
Connect between power supply (U1) and the grid of first FET (Q11).
7. interface circuit (10) according to claim 6, it is characterised in that first input circuit (210) also includes
4th resistance (R4) and the 5th resistance (R5), the 4th resistance (R4) is connected to the drain electrode of first FET (Q11)
Between the first data input port, the 5th resistance (R5) is connected to the drain electrode and first of second FET (Q12)
Between signal input.
8. interface circuit (10) according to claim 5-7 any one, it is characterised in that two grades of gating circuits
(120) including the second triode (Q2), the 3rd FET (Q13) and the 4th FET (Q14), second triode
(Q2) base stage is connected with the colelctor electrode of first triode (Q1), colelctor electrode is connected, launches with the second external power supply (U2)
Pole is grounded；
The grid of the 3rd FET (Q13) is connected with second external power supply (U2), drains and second data
Input circuit (222) connection, source electrode are connected with second data output circuit (322)；
The grid of the 4th FET (Q14) is connected with second external power supply (U2), drains and the secondary signal
Input circuit (224) connection, source electrode are connected with the secondary signal output circuit (324).
9. interface circuit (10) according to claim 8, it is characterised in that two grades of gating circuits (120) also include
6th resistance (R6) and the 7th resistance (R7)；
6th resistance (R6) is connected to the colelctor electrode of first triode (Q1) and the base of second triode (Q2)
Between pole；
7th resistance (R7) be connected to second external power supply (U2) and the 3rd FET (Q13) grid it
Between.
10. interface circuit (10) according to claim 9, it is characterised in that second input circuit (220) also includes
8th resistance (R8) and the 9th resistance (R9), the 8th resistance (R8) is connected to the drain electrode of the 3rd FET (Q13)
Between the second data input port, the 9th resistance (R9) is connected to the drain electrode and second of the 4th FET (Q14)
Between signal input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620853193.XU CN206147606U (en) | 2016-08-08 | 2016-08-08 | Interface circuit |
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| CN201620853193.XU CN206147606U (en) | 2016-08-08 | 2016-08-08 | Interface circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110062185A (en) * | 2019-04-19 | 2019-07-26 | 北京灵优智学科技有限公司 | A kind of interface circuit |
| CN111092056A (en) * | 2019-07-05 | 2020-05-01 | 珠海艾派克微电子有限公司 | Integrated circuit and chip |
-
2016
- 2016-08-08 CN CN201620853193.XU patent/CN206147606U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110062185A (en) * | 2019-04-19 | 2019-07-26 | 北京灵优智学科技有限公司 | A kind of interface circuit |
| CN111092056A (en) * | 2019-07-05 | 2020-05-01 | 珠海艾派克微电子有限公司 | Integrated circuit and chip |
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Address after: 610094 Tianfu Software Park Area A, 1129 Century City Road, Chengdu High-tech Zone, Sichuan Province Patentee after: Chengdu Jimi Technology Co., Ltd. Address before: No. 1129 Tianfu Software Park A District Century City high tech Zone of Chengdu City, Sichuan Province Road 610000 7 5 storey building No. 501 Patentee before: CHENGDU XGIMI TECHNOLOGY CO., LTD. |
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