CN206162524U - FSI signal switch system based on openpower platform - Google Patents
FSI signal switch system based on openpower platform Download PDFInfo
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- CN206162524U CN206162524U CN201621198816.0U CN201621198816U CN206162524U CN 206162524 U CN206162524 U CN 206162524U CN 201621198816 U CN201621198816 U CN 201621198816U CN 206162524 U CN206162524 U CN 206162524U
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Abstract
The utility model provides a FSI signal switch system based on openpower platform, the FSP2 module is connected with the first input end of FSI switch chip, the BMC chip is connected with the second input of FSI switch chip, the output and the CPU of FSISwitch chip are connected, the BMC chip passes through the control channel to be connected with the control end of FSI switch chip, and the BMC chip is according to the current operational mode of CPU, selected CPU's initialization mode to sending to FSI switch chip through the control channel and chooseing control signal, FSI switch chip selects FSP2 module or BMC chip to use the FSI signal to carry out the initialization to CPU according to selected control signal, realized when carrying out the initialization to CPU that only a mode is gone on, guaranteed the rational distribution of FSI signal.
Description
Technical field
The utility model is related to Openpower platforms field, more particularly to a kind of FSI based on Openpower platforms believes
Number switched system.
Background technology
In Openpower platforms, the initialization of CPU generally has two ways, and a kind of mode is that BMC chip passes through FSI
Signal to CPU sends a series of configuration informations, and another way is to use FSP2 modules（The debugging that FSP2 modules are provided for IBM
Instrument, dedicated for Openpower platforms）A series of configuration informations are sent to CPU by FSI signals, to carry out correlation to CPU
Configuration.
When initializing to CPU, there can only be a kind of mode to carry out, and both FSP2 modules and BMC chip need
FSI signals are used, and can only send FSI signals to complete by one of them of FSP2 modules and BMC chip in the same time
Initialization to CPU.So, in Openpower platforms, how to solve switching between FSP2 modules and BMC chip is that assistant officer treats
The technical problem of solution.
The content of the invention
A kind of FSI signal switched systems based on Openpower platforms are provided based on above-mentioned technical problem the utility model,
Including：FSP2 modules, BMC chip, FSI Switch chips, CPU, a FSI passages, the 2nd FSI passages, the 3rd FSI passages,
Control passage；FSI Switch chips are provided with first input end, the second input, output end and control end；
FSP2 modules are connected by a FSI passages with the first input end of FSI Switch chips；BMC chip is by the
Two FSI passages are connected with the second input of FSI Switch chips；The output end of FSI Switch chips is logical by the 3rd FSI
Road is connected with CPU；BMC chip is connected by control passage with the control end of FSI Switch chips, and BMC chip is used for basis
CPU current operational mode, selectes the initialization mode of CPU, and sends selected to FSI Switch chips by control passage
Control signal, FSI Switch chips select FSP2 modules or BMC chip using FSI signals to CPU according to selected control signal
Initialized；BMC chip be additionally operable to by the 2nd FSI passages to FSI Switch chips send CPU is carried out it is initialized
FSI signals；FSP2 modules are used to be sent to FSI Switch chips by a FSI passages carries out initialized FSI letters to CPU
Number.
Preferably, the 2nd FSI passages are provided with Level Shift chips, and BMC chip is provided with IIC interfaces, and BMC chip passes through
IIC interfaces are connected with the input of Level Shift chips, output end and the FSI Switch chips of Level Shift chips
The second input connection.
Preferably, Level Shift chips adopt 74AVC4TD245GU models.
Preferably, FSI Switch chips adopt PI3USB102ZLE models.
Preferably, the input and output end of Level Shift chips is equipped with IIC interfaces.
As can be seen from the above technical solutions, the utility model has advantages below：
In system, BMC chip selectes the initialization mode of CPU according to CPU current operational mode, and logical by control
Road to FSI Switch chips send selected control signal, and FSI Switch chips select FSP2 modules according to selected control signal
Or BMC chip is initialized using FSI signals to CPU, realize when initializing to CPU, only a kind of mode is entered
OK, and FSP2 modules and BMC chip only send FSI signals by FSP2 modules or BMC chip one of them in the same time,
To complete the initialization to CPU, it is ensured that the reasonable distribution of FSI signals.
Description of the drawings
In order to be illustrated more clearly that the technical solution of the utility model, the accompanying drawing to be used needed for description will be made below
Simply introduce, it should be apparent that, drawings in the following description are only some embodiments of the present utility model, for this area
For those of ordinary skill, on the premise of not paying creative work, can be with according to these other accompanying drawings of accompanying drawings acquisition.
Fig. 1 is the overall schematic based on the FSI signal switched systems of Openpower platforms；
Fig. 2 is the schematic diagram based on the FSI signal switched system preferred embodiments of Openpower platforms.
Specific embodiment
It is concrete below in conjunction with this to enable the purpose of this utility model, feature, advantage more obvious and understandable
Accompanying drawing in embodiment, is clearly and completely described, it is clear that disclosed below to the technical scheme in the utility model
Embodiment is only a part of embodiment of the utility model, and not all embodiment.Based on the embodiment in this patent, ability
All other embodiment that domain those of ordinary skill is obtained under the premise of creative work is not made, belongs to this patent guarantor
The scope of shield.
The utility model provides a kind of FSI signal switched systems based on Openpower platforms, as shown in figure 1, bag
Include：FSP2 modules 1, BMC chip 2, FSI Switch chips 3, CPU4, a FSI passages 5, the 2nd FSI passages 6, the 3rd FSI
Passage 7, control passage 8；FSI Switch chips 3 are provided with first input end, the second input, output end and control end；
FSP2 modules 1 are connected by a FSI passages 5 with the first input end of FSI Switch chips 3；BMC chip 2 leads to
Cross the 2nd FSI passages 6 to be connected with the second input of FSI Switch chips 3；The output end of FSI Switch chips 3 is by the
Three FSI passages 7 are connected with CPU4；BMC chip 2 is connected by control passage 8 with the control end of FSI Switch chips 3, BMC cores
Piece 2 is used for according to CPU4 current operational mode, selectes the initialization mode of CPU4, and by control passage 8 to FSI
Switch chips 3 send selected control signal, and FSI Switch chips 3 select FSP2 modules 1 or BMC according to selected control signal
Chip 2 is initialized using FSI signals to CPU4；BMC chip 2 is additionally operable to by the 2nd FSI passages 6 to FSI Switch cores
Piece 3 is sent and CPU4 is carried out initialized FSI signals；FSP2 modules 1 are used for by a FSI passages 5 to FSI Switch cores
Piece 3 is sent and CPU4 is carried out initialized FSI signals.
The operational mode of CPU4 includes：Normal mode of operation and debugging mode.The default mode of operation of general CPU4 is for just
Normal mode of operation.When CPU4 enters debugging mode, BMC chip 2 sends selected FSP2 module control signals, sends out FSP2 modules
Go out FSI signals, realize a series of configurations of CPU.
BMC chip is carried out servomechanism remote side administration controller (Baseboard management controller)
A main control chip in IPMI.
In the present embodiment, if as shown in Fig. 2 BMC chip 2 is passed without special FSI interfaces using IIC interfaces
Defeated FSI signals, but both level mismatches, need to first pass through Level Shift chips to carry out level conversion, are changed by 3.3V
Matching for IIC interfaces and the 2nd FSI passages 6 is realized into 1.2V.
Specifically, the 2nd FSI passages 6 are provided with Level Shift chips 9, and BMC chip 2 is provided with IIC interfaces 10, BMC chip
2 are connected by IIC interfaces 10 with the input of Level Shift chips 9, the output end and FSI of Level Shift chips 9
The second input connection of Switch chips 3.
IIC（That is Inter-IntegratedCircuit IC bus）It is a kind of multidirectional controlling bus, mainly uses
To connect integrated circuit（ICS）.In IIC, multiple chips may be coupled under same bus structure, while each chip can
So that used as the voltage input for implementing data transfer, this mode simplifies signal transmission bus.
In the present embodiment, Level Shift chips 9 adopt 74AVC4TD245GU models.FSI Switch chips 3 are adopted
Use PI3USB102ZLE models.
The input and output end of Level Shift chips 9 is equipped with IIC interfaces 10.
Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
Term " first " in specification and claims of the present utility model and above-mentioned accompanying drawing, " second ", " the 3rd "
" 4th " etc.（If there is）It is the object for distinguishing similar, without being used to describe specific order or precedence.Should
The data that the understanding is so used can be exchanged in the appropriate case, so that embodiment of the present utility model described herein can
Implemented with the order in addition to those for illustrating here or describing.Additionally, term " comprising " and " having " and they
Any deformation, it is intended that cover non-exclusive including.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or new using this practicality
Type.Various modifications to these embodiments will be apparent for those skilled in the art, determine herein
The General Principle of justice can in other embodiments be realized in the case of without departing from spirit or scope of the present utility model.Cause
This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The most wide scope consistent with features of novelty.
Claims (5)
1. a kind of FSI signal switched systems based on Openpower platforms, it is characterised in that include：FSP2 modules, BMC cores
Piece, FSI Switch chips, CPU, a FSI passages, the 2nd FSI passages, the 3rd FSI passages, control passage；FSI Switch
Chip is provided with first input end, the second input, output end and control end；
FSP2 modules are connected by a FSI passages with the first input end of FSI Switch chips；BMC chip passes through second
FSI passages are connected with the second input of FSI Switch chips；The output end of FSI Switch chips passes through the 3rd FSI passages
It is connected with CPU；BMC chip is connected by control passage with the control end of FSI Switch chips, and BMC chip is used for according to CPU
Current operational mode, selectes the initialization mode of CPU, and sends selected control to FSI Switch chips by control passage
Signal, FSI Switch chips select FSP2 modules or BMC chip to carry out to CPU using FSI signals according to selected control signal
Initialization；BMC chip is additionally operable to be sent to FSI Switch chips by the 2nd FSI passages carries out initialized FSI letters to CPU
Number；FSP2 modules are used to be sent to FSI Switch chips by a FSI passages carries out initialized FSI signals to CPU.
2. FSI signal switched systems based on Openpower platforms according to claim 1, it is characterised in that
2nd FSI passages are provided with Level Shift chips, and BMC chip is provided with IIC interfaces, BMC chip by IIC interfaces with
The input connection of Level Shift chips, the output end of Level Shift chips and the second input of FSI Switch chips
End connection.
3. FSI signal switched systems based on Openpower platforms according to claim 2, it is characterised in that
Level Shift chips adopt 74AVC4TD245GU models.
4. FSI signal switched systems based on Openpower platforms according to claim 1, it is characterised in that
FSI Switch chips adopt PI3USB102ZLE models.
5. FSI signal switched systems based on Openpower platforms according to claim 2, it is characterised in that
The input and output end of Level Shift chips is equipped with IIC interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621198816.0U CN206162524U (en) | 2016-11-07 | 2016-11-07 | FSI signal switch system based on openpower platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621198816.0U CN206162524U (en) | 2016-11-07 | 2016-11-07 | FSI signal switch system based on openpower platform |
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| Publication Number | Publication Date |
|---|---|
| CN206162524U true CN206162524U (en) | 2017-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201621198816.0U Expired - Fee Related CN206162524U (en) | 2016-11-07 | 2016-11-07 | FSI signal switch system based on openpower platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115114201A (en) * | 2022-06-27 | 2022-09-27 | 山东云海国创云计算装备产业创新中心有限公司 | FSI controller and BMC chip comprising same |
-
2016
- 2016-11-07 CN CN201621198816.0U patent/CN206162524U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115114201A (en) * | 2022-06-27 | 2022-09-27 | 山东云海国创云计算装备产业创新中心有限公司 | FSI controller and BMC chip comprising same |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170510 Termination date: 20191107 |