KR100801179B1 - Flash memory device capable of reusing defective flash memories - Google Patents

Abstract

A flash memory device capable of reusing a defective flash memory is provided to increase productivity of the flash memory without costs for disposal of defective flash memory by reusing a normal flash memory. A flash memory(120) includes a first individual flash and a second individual flash. A controller(160) controls the operation of the flash memory. A conversion unit(150) is connected between the flash memory and the controller, and controls the operation of the first individual flash and the second individual flash selectively. The conversion unit controls the path of a state signal(#R/B1) and a chip selection signal(#CE1) supplied to the first individual flash from the controller, and controls the path of a state signal(#R/B2) and a chip selection signal(#CE2) supplied to the second individual flash from the controller.

Description

Flash Memory Device Capable of Reusing Defective Flash Memories}

1 is an overall configuration diagram of a system to which the present invention can be applied.

Fig. 2 is a block diagram showing the configuration of a dual die NAND flash memory.

Fig. 3 is a block diagram showing the configuration of a quad die NAND flash memory.

4 is a block diagram showing a configuration of a flash memory card to which the present invention is applied.

5 is a block diagram showing one embodiment of a conversion circuit used in the present invention.

FIG. 6 is a block diagram illustrating an operation of the conversion circuit of FIG. 5 when a limit error or a fatal defect occurs in a first individual memory in the flash memory device of the present invention. FIG.

FIG. 7 is a block diagram illustrating an operation of the conversion circuit of FIG. 5 when a limit error or a fatal defect occurs in a second individual memory in the flash memory device of the present invention. FIG.

The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of recycling the flash memory to overcome the limit exceeded error occurred in the individual flash constituting the flash memory.

As the data storage capacity required by various portable electronics and embedded devices increases, the demand for flash memory type EEPROM (Electrically Erasable Programmable Read Only Memory) is increasing. Flash Memory In particular, NAND flash memory is a Compact Flash Card (CFC) or SMC (Smart Media Card) used as a mobile storage medium for communication devices (mobile phones or PDAs), digital cameras, MP3 players, and e-books. ), A core component of Multi Media Card (MMC), Security Digital Card (SDC), and USB Flash Driver (UFD). Flash memory also serves as a replacement for high-capacity data storage devices, such as hard disks, and embedded processors such as RISC CPUs used in PCMCIA flash cards, MP3 players, digital voice recorders, routers used in routers, or DSPs used in mobile phones. It also stores program code for embedded processors.

The companies that produce flash memory, one of the key electronic components used in various fields, discard all the block error products generated in the production process and treat them as industrial waste scrap. In addition, companies that produce flash memory as a portable storage medium discard all defective products caused by flash error blocks or post-production products that have failed blocks.

On the other hand, flash memory is controlled by an MCU, and manufacturers of such MCUs correct bit errors using error correction codes (ECC) or use special software techniques to reduce defective products caused by error block problems. Minimizing blocks Flash memory errors are usually bit errors in which one or two bits appear on a page or sector because the charge on the cell leaks through the oxide film surrounding the floating gate of the memory cell. Because. There are two types of bit errors: write failures and read failures. A write error is a result of programming a page in a memory block of a flash memory or erasing a block and then the result is wrong, which can be determined by checking the write status bits of the flash memory. A read error occurs when the recorded data is changed after performing a write operation without error. To correct bit errors in such flash memory, Hamming Code is usually used, which is characterized by '2-bit detection and 1-bit correction'. That is, in the conventional Hamming code ECC, a single bit error can detect and even correct it. For a 2-bit error, it can only detect it, and cannot correct the error. It was the limit to replace.

As described above, all flash memory products that have exceeded the limit block that could not be solved in the prior art had to be discarded because there was no way to correct the error. As a result of errors occurring only in a small portion of the storage units constituting the flash memory, discarding the entire flash memory is not only a huge waste, but also results in a decrease in the productivity of the flash memory.

It is an object of the present invention to recycle a flash memory in which a prior limit error block has occurred.

Another object of the present invention is to increase the productivity of the flash memory by recycling the failed bad flash memory.

The flash memory device according to the present invention comprises (A) a flash memory including a first individual flash and a second individual flash, (B) a controller for controlling the operation of the flash memory, and (C) a connection between the flash memory and the controller. And converting means for selectively controlling the operation of the first individual flash and the second individual flash of the flash memory. Here, the conversion means controls the paths of the state signal # R / B1 and the chip select signal # CE1 supplied from the controller to the first individual flash, and the state signal # R / B2 and chip select supplied from the controller to the second individual flash. Controls the path of signal # CE2. According to one embodiment of the invention, the conversion means comprises: (a) a first resistor element for controlling the connection between the # R / B1 input signal from the controller and the # R / B1 output signal connected to the first individual flash; (b) a fifth resistor element controlling the connection between the # CE1 input signal from the controller and the # CE1 output signal connected to the first individual flash; and (c) the # R / B1 input signal and the # R / B2 output. A tenth resistive element controlling the connection between the signals, and (d) a seventh resistive element controlling the connection between the # CE1 input signal and the # CE2 output signal, wherein the # R / B1, # R / B2, And third, fourth, eighth and ninth resistive elements controlling the connection between # CE1 and # CE2 output signals and Vcc. In this case, when both the first and second individual flashes are normal, the third, fourth, eighth and ninth resistor elements and the tenth and seventh resistor elements are turned off, and the first and fifth resistor elements are turned on. When the limit error block occurs in the first individual flash and the second individual flash is normal, the fourth and ninth resistor elements and the first and fifth resistor elements are turned off, and the tenth, seventh, third, The eighth resistance element is turned on, and when the first individual flash is normal and the second individual flash has exceeded the limit error block, the third, eighth and tenth and seventh resistance elements are turned off, and the fourth , 9, 1, 5 resistance elements are turned on.

In the flash memory device according to another embodiment of the present invention, the converting means comprises: a second resistor element for controlling the connection between the # R / B2 input signal from the controller and the # R / B2 output signal connected to the second individual flash; And a sixth resistive element controlling the connection between the # CE2 input signal from the controller and the # CE2 output signal connected to the second individual flash. In this embodiment, when both the first and second individual flashes are normal, the third, fourth, eighth and ninth resistor elements and the tenth and seventh resistor elements are turned off, and the first, fifth, second and sixth resistors are turned off. The device is in an on state, and when the over limit error block occurs in the first individual flash and the second individual flash is normal, the fourth and ninth resistor elements and the first, second, five, and sixth resistor elements are turned off. And the 10th, 7th, 3rd and 8th resistance elements are turned on, and when the first individual flash is normal and the second individual flash has exceeded the limit error block, the third, 8th resistance element and the 10, 2, The seventh and sixth resistance elements are turned off, and the fourth, ninth, first and fifth resistance elements are turned on.

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment

1 is an overall configuration diagram of a system to which the present invention can be applied.

The flash memory operation control apparatus 110 is connected to the host system 100 through the host bus 105, and is connected through the flash memory 120 and the flash bus 115 to exchange data. The control device 110 includes a controller 112, a flash control block 114, and an ECC block 116. The controller 112 includes a static random access memory (SRAM), a data buffer, a BiT / link buffer, a memory management unit (MMU), and the like. In the present invention, the flash memory 120 is a stack of two dual die flash memory and is referred to as a 'quad die flash'. Quad-die flash memory allows common power and some signal lines to be tied together in dual-die flash memory, allowing the use of chip select (CE) signals and status signals (R / B), one for each dual die flash, and two dual die flashes. It is made of a semiconductor package device. Hereinafter, the dual die flash memory constituting the quad die flash memory is also referred to as 'individual flash'.

The flash control block 114 supplies a chip select signal CE, a control signal, and an I / O signal to the flash memory 120, and receives a status signal R / B (Ready / Busy) from the flash memory. As the I / O signal, data, an address, and a command signal may be supplied to the flash memory 120 at a time difference. In the present specification, the flash memory operation control device 110 and the flash memory 120 are collectively referred to as a “flash memory device”.

2 is a block diagram showing the configuration of a dual die NAND flash memory.

Dual die NAND flash memory 12 includes flash array 20, data register and S / A (Sense Amplifier) block 22, Y-gating block 24, X-butter / latch / decoder block 26, Y-buffer / latch / decoder block (28), instruction register (30), control logic & H / V generator block (32), I / O butter & latch block (34), global buffer (36, global buffer), An output driver 38. All address signals A0-A11, A12-A30 and command signals are multiplexed through eight I / O signal lines I / O 0 ... I / O 7. I / O is used to send commands, addresses, and data to the device and to receive data in read operations.

In the dual die NAND flash memory 12 of FIG. 2, the control signals #RE, #WE, # R / B1, #CE are input in common to the command register 30 and the control logic & H / V generator block 32. . Among the control signals, #RE (Read Enable) controls the data output and status signal output for the I / O line. The data output starts, for example, at the falling edge of #RE. Write Enable (WE) controls data and commands on the I / O lines during the write sequence. I / O lines are latched, for example, at the rising edge of the #WE signal. The # R / B (Ready / Busy) signal is generated from the flash memory and indicates whether the flash memory is ready or busy. The #CE (Chip Enable) input controls the active or standby state of the device. In the sequence in which the instruction is loaded and in the address-loaded sequence, #CE must be changed to the low level before the falling edge of # WE /.

On the other hand, the control signals CLE, ALE, #WP are input to the control logic & H / V generator block 32. Command Latch Enable (CLE) controls writing to the command register 30. If CLE is at the high level, the instruction is loaded at the rising edge of #WE. The Address Latch Enable (ALE) input controls writing to address registers in X-block 26 and Y-block 28. When ALE is at the high level, the address is loaded at the rising edge of #WE. ALE must remain high during the entire address sequence. Write Protection (WP) provides protection during program or erase operations on the flash array 20. When #WP is at the low level, program operation or erase operation is prevented.

3 is a block diagram showing the internal structure of a quad-die NAND flash memory 120 to which the present invention is applied.

In the quad-die flash memory 120, two separate flashes 12a and 12b described with reference to FIG. 2 are arranged in parallel. For the internal circuit configuration of each of the two individual flashes 12a and 12b, the same reference numerals as in Fig. 2 are used, and the internal circuits of the first individual flash 12a arranged on the left side are written with 'a' following the reference numerals and the right side. In the internal circuits of the second individual flashes 12b disposed in the circuit, 'b' is denoted after the reference numeral to distinguish each individual flash.

Referring to FIG. 3, the quad die NAND flash memory 120 includes an I / O and a power signal and some control signals for two separate flashes, that is, two dual die NAND flash memories 12a and 12b. #RE, CLE, ALE, #WP). Among the control signals, the chip select signal CE and the standby / operation separation signal R / B are separately supplied to each of the first individual flash 12a and the second individual flash 12b. According to one embodiment of the invention, quad die NAND flash memory 120 is implemented in a package with four power pins, eight data I / O pins, and nine control signal pins, four of 21 pins. Power pins, 8 data I / O pins, 5 control signal pins (#WE, #RE, CLE, ALE, #WP) are commonly connected to 2 separate flashes 12a, 12b, and 2 control Signal pins # CE1 and # R / B1 are connected only to the first individual flash 12a, and two control signal pins # CE2 and # R / B2 are connected only to the second individual flash 12b. Control signals # CE1 and # R / B1 control read / program operations for the flash array 20a of the first individual flash 12a, and control signals # CE2 and # R / B2 control the second individual flash 12b. Control read / program operations for the flash array 20b.

As described above, since the read / program operations of the two flash memory arrays can be controlled separately, if an error limit block occurs in one flash memory, it can be replaced with a block of another flash memory. This will be described taking the flash memory card of FIG. 4 as an example.

4 is a block diagram showing an internal configuration of a flash memory card to which the present invention is applied.

Referring to FIG. 4, the flash memory card 200 includes a flash memory 120, a conversion circuit 150, a central controller 160 (main control unit (MCU), and a power regulator 170). The flash memory card 200 transmits and receives a signal through an interface with a host (for example, '100' of FIG. 1), and receives a power signal (Vcc and Vss). The low voltage is converted into a low voltage and the converted power signal is supplied to the flash memory 120 and the central controller 160.

Flash memory 120 is usually composed of a plurality of memory blocks, one memory block is composed of a plurality of pages, one page is composed of a plurality of sectors. Each sector is composed of user data and corresponding ECC data. The page and the sector may have the same capacity, but when the capacity of the flash memory 120 is 1G or more, the page is larger than the sector. The central controller 160 controls a program or write operation, an erase operation, and a read operation of the flash memory 120 according to a request of a host coming through the host interface, and the program or write operation is performed on a page basis of the flash memory 120. The erase operation is performed in units of blocks. On the other hand, the unit for importing data from the host 100 to the flash memory card 200 is made in sector (or page) units. That is, the host 100 exchanges data in sector units with the flash memory 120 through the central controller 160.

As described above with reference to FIG. 3, the flash memory 120 includes two separate flashes 12a and 12b and includes an I / O signal and some control signals #WE, #RE, #WP, CLE, ALE. ) And the power supply signal are commonly supplied to the individual flashes 12a and 12b, and the # CE1, # CE2, # R / B1 and # R / B2 signals are supplied to the individual flashes 12a or 12b, respectively. In order to supply the control signals # CE1, # CE2, # R / B1, # R / B2 to the individual flashes 12a and 12b, respectively, first, an over limit error occurs in any memory block of the individual flashes 12a and 12b. Second, control signal # CE1, # CE2, # R / B1, # R / through the conversion circuit 150 so that the operation through the replacement memory block to replace the memory block that has exceeded the limit has occurred. B2 must be supplied to the respective individual flash 12a or 12b.

To determine which memory block of the two individual flashes 12a and 12b has exceeded a limit, a general flash memory test apparatus may be used, or firmware provided by a flash controller manufacturer may be used.

In FIG. 4, the present invention has been described using the flash memory card 200 as an example. However, the present invention is not only applied to such a flash memory card, but the communication using the CFC, SMC, MMC, SDC, UFD, and flash memory described above. It can be easily understood by those skilled in the art that the present invention can be applied to both devices and the like.

FIG. 5 is a block diagram showing an embodiment of a conversion circuit ('150' of FIG. 4) used in the present invention.

The conversion circuit 150a shown in FIG. 5 includes ten resistance elements R1 to R10. One end of the first resistor element R1 is connected to the # R / B1 input signal and the other is connected to the # R / B1 output signal. As can be seen from the foregoing description with reference to FIG. 4, the # R / B1 input signal refers to a signal output from the central controller 160 and input to the conversion circuit 150, and a # R / B2 output signal. Denotes a signal output from the conversion circuit 150 and input to the flash memory 120. The second resistor element R2 is connected between the input and the output of # R / B2. The third resistance element R3 is connected between the Vcc power supply and the # R / B1 output, and the fourth resistance element R4 is connected between the Vcc power supply and the # R / B1 output. The fifth and sixth resistors R5 and R6 are connected between inputs and outputs of # CE1 and # CE2, respectively. The seventh resistor element R7 is connected between the # CE1 input and the # CE2 output, the eighth resistor element R8 is connected between the Vcc power supply and the # CE1 output, and the ninth resistor element R9 is connected to the Vcc power supply. The tenth resistor element R10 is connected between the # R / B1 input and the # R / B2 output.

In the conversion circuit 150a of FIG. 5, R3, R4, R8, and R9 are pull-up resistors, and always supply a Vcc signal to a node connected to one side of the device, and R1, R2, R5, R6 and R7 are switching resistance devices that connect and block signals between the flash memory 120 and the central controller 160 to select a signal path.

The resistive elements R1 to R10 shown in FIG. 5 may be implemented as a general switching element in which the resistance value is selected from '0' or 'infinity', and may be implemented as a dual inline package (DIP) switch or a fuse. It may be. On the other hand, it is also possible to implement a resistor device as an EEPROM device to arbitrarily program the connection of the input signal and the output signal. In addition, although FIG. 5 illustrates an example in which the conversion circuit 150 is configured using 10 resistance elements, the resistance elements R2 and # CE2 connected between the # R / B2 input and the # R / B2 output are illustrated in FIG. 5. The resistive element R6 connected between the input and the # CE2 output can be omitted. In this case, if you want to block the # R / B2 input and the # R / B2 output, bind the # R / B2 output to Vcc through the resistor element R4, and connect the # R / B2 input to the # R / B2 output. In this case, the resistance element R4 may be turned off. Likewise, if it is necessary to block the # CE2 input and the # CE2 output, connect the # CE2 output to Vcc through the resistor element R9, and turn off the resistor element R9 when you want to connect the # CE2 input and the # CE2 output. So that the # CE2 input is connected directly to the # CE2 output.

The conversion circuit 150 of FIG. 5 controls the on / off of the resistive elements R1 to R10 so that a limit error block is placed on any one of the two individual flashes 12a and 12b included in the flash memory 120. The flash memory 120 may operate properly even when two separate flashes 12a and 12b are normal. That is, the conversion circuit 150 of FIG. 5 is applicable to both the normal and partial failure of the flash memory 120. When the two individual flashes 12a and 12b included in the flash memory 120 are all normal, the resistors R3, R4, R7, R8, R9 and R10 are turned off and the resistors R1, R2, R5 and R6 are turned off. To turn it on.

If either of the two individual flashes 12a and 12b included in the four-die NAND flash memory 120 includes the limit error block or a fatal defect occurs, the conversion circuit 150a of FIG. There are two cases in which replacement is done with other individual memory that has no over limit error blocks or fatal defects.

First, a case in which an over limit error or a fatal defect occurs in the first individual memory 12a will be described with reference to FIG. 6.

The resistors R1 and R5 are turned off, breaking the connections between the # R / B1 input and # R / B1 output and the # CE1 input and # CE1 output. To ensure a disconnect between them, turn resistor element R3 on to connect # R / B1 outputs to Vcc, and turn resistor element R8 on to connect # CE1 outputs to Vcc. The resistance element R2 is turned off to break the connection between the # R / B2 input and the # R / B2 output, and the resistance element R6 is turned off to also disconnect the connection between the # CE2 input and the # CE2 output.

Turn on resistor R10 to make the # R / B1 input and # R / B2 output connected, and turn off resistor R4 connected between # R / B2 output and Vcc. The resistor R7 is turned on to connect the # CE1 input and the # CE2 output, and the resistor R9 connected between the # CE2 and the Vcc is turned off.

In this way, the operation of the first individual flash 12a is prevented, and the second individual flash 12b is supplied with the signals necessary for # R / B2 through the # R / B1 input and the resistor element R10, and the # CE1 input, The resistor R7 is supplied with the necessary signal for # CE2 to operate. In FIG. 6, the reason why the # R / B2 output signal and the # CE2 output signal are connected to the # R / B1 input and the # CE1 input is that the controller of the flash memory first transmits the R / B signal and the CE signal for the first flash memory. It must be recognized.

Next, with reference to FIG. 7, a case in which an over limit error or a fatal defect occurs in the second individual flash 12b will be described.

The resistors R3 and R8 of the pull-up element are turned off and the resistors R2, R6, R7 and R10 of the switch element are turned off. On the other hand, the resistance elements R4 and R9 are turned on. The # R / B2 output is then connected to Vcc by a pullup element R4 so that a high level signal is always supplied, and the # CE2 output is connected to Vcc by a pullup element R9 so that a high level signal is always supplied. Then, the resistance element R10 connected between the # R / B1 input and the # R / B2 output and the resistance element R7 connected between the # CE1 input and the # CE2 output are turned off. Therefore, even if the second individual flash 12b is supplied with control signals #WE, #RE, #WP, CLE, and ALE different from the I / O signal, the second individual flash 12b cannot perform the read operation, the program / write operation, or the erase operation.

When the remaining resistor elements R1 and R5 except those listed above are turned on, the # R / B1 input is connected to the # R / B1 output and the # CE1 input is connected to the # CE1 output so that the first individual flash 12a It works.

Exemplary embodiments of the present invention have been described with reference to the drawings, which are provided to enable those skilled in the art to easily understand and reproduce the present invention. It is not intended to limit. Accordingly, the embodiments shown in the drawings may be modified and modified as many without departing from the scope of the invention, all such modifications and variations are included in the scope of the invention as defined by the claims.

According to the present invention, even when a limit error or a fatal defect occurs in any of the individual flash units constituting the flash memory, the flash memory can be recycled through the individual flash units that do not fail without having to discard the entire flash memory. Therefore, it is possible to prevent cost waste due to the disposal of the conventional flash memory and to increase the productivity of the flash memory.

In addition, according to the present invention, since only one operation of a resistance element or a switching element in one conversion circuit can deal with not only a failure of an individual flash but also one of the individual flashes, a defective flash can be dealt with. It can reduce the cost and effort of recycling.

Claims (7)

A flash memory including a first individual flash and a second individual flash; A controller for controlling an operation of the flash memory; A conversion means connected between the flash memory and a controller to selectively control the operation of the first individual flash and the second individual flash of the flash memory, The conversion means controls the paths of the state signal # R / B1 and the chip select signal # CE1 supplied from the controller to the first individual flash, and the state signal # R / B2 and chip supplied from the controller to the second individual flash. And controlling the path of the selection signal # CE2. In claim 1, The conversion means, A first resistance element controlling a connection between a # R / B1 input signal from the controller and a # R / B1 output signal connected to the first individual flash; A fifth resistive element controlling a connection between a # CE1 input signal from the controller and a # CE1 output signal connected to the first individual flash; A tenth resistive element controlling a connection between the # R / B1 input signal and a # R / B2 output signal; A seventh resistance element controlling a connection between the # CE1 input signal and a # CE2 output signal, 3, 4, 8, and 9 resistor elements for controlling the connection between each of the #R / B1, #R / B2, # CE1, # CE2 output signal and Vcc, When the first individual flash and the second individual flash are both normal, the third, fourth, eighth and ninth resistor elements and the tenth and seventh resistor elements are turned off, and the first and fifth resistor elements are turned on. When a limit error block occurs in the first individual flash and the second individual flash is normal, the fourth and ninth resistor elements and the first and fifth resistor elements are turned off, and the tenth, seventh, third and eighth elements are turned off. The resistive element is turned on, When the first individual flash is normal and the second individual flash has exceeded the limit block, the third and eighth resistors and the tenth and seventh resistors are turned off and the fourth, nine, one, and five resistors are turned off. And the device is in an on state. In claim 2, The conversion means, A second resistor element controlling a connection between a # R / B2 input signal from the controller and a # R / B2 output signal connected to the second individual flash; And a sixth resistor element controlling a connection between a # CE2 input signal from the controller and a # CE2 output signal connected to the second individual flash. In claim 3, The conversion means, When the first and second individual flashes are all normal, the third, fourth, eighth and ninth resistor elements and the tenth and seventh resistor elements are turned off, and the first, fifth, second and sixth resistor elements are turned on. State, When a limit error block occurs in the first individual flash and the second individual flash is normal, the fourth and ninth resistor elements and the first, second, five, and sixth resistor elements are turned off, and the tenth and seventh resistors are turned off. , 3 and 8 resistors are turned on, When the first individual flash is normal and the second individual flash has exceeded the limit error block, the third, eighth, and tenth, two, seven, sixth resistors are turned off, and the fourth, nine, A flash memory device, wherein the 1 and 5 resistive elements are turned on. The method of claim 3 or 4, And the first to tenth resistive elements are any one element selected from a device including a DIP switch, a fuse, and an EEPROM. The method of claim 1 or 2, And wherein the flash memory is a quad die NAND flash memory and the first and second individual flashes are dual die NAND flash memory. The method according to any one of claims 1 to 4, And the first and second individual flashes share control signals other than the I / O signals from the controller and the R / B and CE signals.

Images