CN101853699B - Nonvolatile memory device and operating method thereof - Google Patents
Nonvolatile memory device and operating method thereof Download PDFInfo
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- CN101853699B CN101853699B CN201010129599.0A CN201010129599A CN101853699B CN 101853699 B CN101853699 B CN 101853699B CN 201010129599 A CN201010129599 A CN 201010129599A CN 101853699 B CN101853699 B CN 101853699B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
Disclosed is an operating method of a non-volatile memory device which comprises randomizing data to store the randomized data; erasing the randomized data; and outputting erase data according to information of a flag cell of the non-volatile memory device at a read operation.
Description
The cross reference of related application
The present invention advocates the right of priority of the korean patent application No.10-2009-0018567 proposed on March 4th, 2009, is herein incorporated by reference.
Technical field
The present invention relates to non-volatile memory device, more specifically, the present invention relates to and randomization is done to data and the non-volatile memory device preserving randomization data, and relevant method of operating.
Background technology
Non-volatile memory device comprises flash memory, impedance variable memory device etc.Flash memory can be divided into NAND quick-flash memory and NOR flash memory.The design feature of NOR flash memory is that its storage unit is connected in parallel bit line.This parallel join mode allows the storage unit of accessing NOR flash memory randomly.On the contrary, the design feature of NAND quick-flash memory is that its storage unit is connected to bit line serially.In other words, the storage unit in NAND quick-flash memory is connected in a memory cell string, therefore only need one with the jointing of bit line.Therefore, NAND quick-flash memory can by integrated very to high-density.
In recent years, carried out the technical research work about preserving multiple data bit in single non-volatile memory cells, the per unit region of flash memory provides data storage capacity greatly thus.The storage unit can preserving multiple data bit is commonly referred to as multilevel-cell (MLC).On the contrary, the storage unit can preserving an only data bit is commonly referred to as single layer cell (SLC).Usually, the feature of MLC in program capability uses the distribution of two or more threshold voltage, and each and specific data mode is relevant.
Summary of the invention
The one side embodiment of concept of the present invention relates to the method for operating of providing package containing the non-volatile memory device of storage unit, and described method comprises: carry out randomization to produce randomization programming data to programming data; Preserve randomization programming data; Wipe a part of randomization programming data to produce obliterated data; And during follow-up read operation, respond the tag unit status data stored in non-volatile memory apparatus, or (1) obtain stored randomization programming data from storage unit, and go randomization to produce read data to stored randomization programming data; Or (2) obtain obliterated data from storage unit, and do not go randomization to produce read data to obliterated data.
The another aspect embodiment of concept of the present invention relates to the method for operating of providing package containing the non-volatile memory device of storage unit, and described method comprises: carry out randomization to produce randomization programming data to programming data; Preserve randomization programming data; Wipe a part of randomization programming data to produce obliterated data; And during subsequent read operation, or (1) checks the data that will read to be programming data, then, obtains stored randomization programming data from storage unit, goes randomization, and produce read data to stored randomization programming data; Or (2) check the data that will read to be obliterated data, then, obtain obliterated data from storage unit, do not going obliterated data to produce read data in randomized situation.
Another aspect embodiment of concept of the present invention relates to provides non-volatile memory device, comprising: memory cell array, containing the storage unit according to row and column arrangement; Page buffer circuit, is configured to from memory cell array read data; And random data interface, be configured to the programming data randomization to memory cell array will be programmed into, randomization is gone to the read data obtained from the storage unit selected in memory cell array, wherein, random data interface is configured to the program/erase state in response to selected storage unit further, is not going to export read data from memory cell array in randomized situation.
Accompanying drawing explanation
By reference to the following description of accompanying drawing, the above and other target of concept of the present invention and feature will become apparent, and wherein, unless specified otherwise herein, Ref. No. identical in figure and label represent same or analogous element.
Fig. 1 is the block diagram of the memory device schematically illustrated according to the embodiment of the present invention.
Fig. 2 is the block diagram of the random data interface further illustrating Fig. 1.
Fig. 3 is the block diagram of the random sequence generator further illustrating Fig. 2.
Fig. 4 is the concept map of the randomization operation of the memory device illustrated according to the embodiment of the present invention.
Fig. 5 is another concept map of the normal running of the memory device illustrated according to the embodiment of the present invention.
Fig. 6 is the block diagram of the read operation of the storage unit illustrated according to the embodiment of the present invention.
Fig. 7 sums up the process flow diagram according to the write operation of the memory device of the embodiment of the present invention.
Fig. 8 sums up the process flow diagram according to the read operation of the memory device of the embodiment of the present invention.
Fig. 9 is the block diagram schematically illustrating memory device in accordance with another embodiment of the present invention.
Figure 10 is the block diagram of the random data interface further illustrating Fig. 9.
Figure 11 is the general block diagram of the computing system of the memory device comprised according to the embodiment of the present invention.
Figure 12 is the general block diagram of the preservation equipment based on storer of the memory device comprised according to the embodiment of the present invention.
Embodiment
Referring now to the accompanying drawing of some embodiment of explanation concept of the present invention, concept of the present invention is more fully described.But concept of the present invention can carry out instantiation in many different forms, and be not appreciated that and be only defined in illustrated embodiment.And these embodiments are suggested as teaching citing.
Although should be appreciated that term first, second, third, etc. can be used to describe various element, assembly, region, layer and/or section here, these elements, assembly, region, layer and/or section not should limit by these terms.These terms are only used to distinguish different elements, assembly, region, layer or section.Therefore, when not departing from concept teaching of the present invention, the first element discussed below, assembly, region, layer or section can be called as the second element, assembly, region, layer or section.
Terminology used here is only used to describe specific embodiment, and is not intended to the restriction becoming concept of the present invention.As used herein, singulative " " and " this " intention also comprise plural form, unless clearly shown in literary composition.Be to be understood that further, term " comprises " and/" comprising ", when using in this manual, specify the existence of described feature, entirety, step, operation, element and/or assembly, but do not get rid of other feature one or more, entirety, step, operation, element, the existence of assembly and/or group or increase.As used herein, term "and/or" comprises any of one or more associated list item and all combinations.
Be to be understood that, when an element or layer be called as " ... on ", " being connected to ", " being coupled to " or " being close in " another element or layer time, it can be directly connected to, is couple to or is close in other element or layer, or can have intermediary element or layer.On the contrary, when an element be called as " directly existing ", " being directly connected to ", " being directly coupled to " or " closely adjacent to " another element or layer time, then there is no intermediary element or layer.
Unless otherwise defined, the implication of used here all terms (comprising technology and scientific terminology) is identical with the implication that concept those of ordinary skill in the field of the present invention understand jointly.Should be appreciated that the implication of those terms such as defined in public directory should be interpreted as further consistent with the implication in the context of this instructions and/or association area, and be not taken in meaning that is Utopian or that too format and explained.
Increase the corresponding increase that degree of memory cell integration may cause " interference " between storage unit.Between storage unit, interference can have a lot of form, comprises program voltage interference, by voltage disturbance, F-poly coupling etc.The degree disturbed between storage unit is subject to closing on each data mode of storage unit and is applied to the impact that at least is closed on the data access operation characteristic of storage unit.By the data preservation mode of randomization in storage unit territory, interference can be reduced widely.
The embodiment of concept of the present invention will be described in the environment of flash memory.But the guidance of concept of the present invention and adjoint benefit can be applied to the storage unit of other types of storage devices, particularly highdensity memory device.Therefore, concept of the present invention is not limited in flash memory.
Fig. 1 is the block diagram of the memory device schematically illustrated according to the embodiment of the present invention.With reference to figure 1, memory device 100 can be the storer suffering flash memory or some other types disturbed between storage unit due to integration density.
In the described embodiment, memory device 100 comprises memory cell array 110, and it comprises the storage unit can preserving M-bit data, and wherein M is positive integer.Memory cell array 110 can be divided into multiple region, comprises the data area and clear area of preserving user data.Each region of memory cell array 110 can be made up of multiple storage block be defined.Such as in U.S. Patent No. 6,236, disclose a kind of possible storage block structure in 594, its theme is incorporated in this by reference.
Memory cell array 110 also comprises at least one tag unit 111.Whether the storage unit that the state of tag unit 111 can be used to indicate in specific webpage, row or wordline has been wiped free of or has been programmed.Such as, when some storage unit corresponding with specific webpage, row or wordline is wiped free of (that is, being placed on erase status), indexing unit value ' 1 ' can be used to indicate this state.On the other hand, indexing unit value ' 0 ' can be used to indicate the programming state of the storage unit of specific webpage/OK/wordline, no matter and the storage unit formed is that MLC or SLC is applicable.
The memory device 100 of Fig. 1 comprises page buffer circuit 120, decoder circuit 130, voltage generator circuit 140 further, comprises and pass through/the steering logic 150 of failed check circuit 160, random data interface unit 170 and input/output buffer circuit 180.Here, pass through/failed check circuit 160 can be configured to independent of steering logic 150.
Page buffer circuit 120 is controlled by control logical one 50, and is configured to read data from memory cell array 110, or programs data in memory cell array 110.Decoder circuit 130 is also controlled by control logical one 50, and is configured to select storage block in memory cell array 110, and selects wordline in selected storage block.Selected wordline can be driven by the word line voltage from voltage generator circuit 140.Voltage generator circuit 140 is controlled by control logical one 50, and is configured to produce the word line voltage being provided to memory cell array 110, such as, read voltage, program voltage, by voltage, local voltage, verifying voltage etc.Steering logic 150 is configured to the whole operation of control store equipment 100.
Pass through/failed check circuit 160 be configured to during programming operation based on the data that read by page buffer circuit 120 make programming and pass through/failed determination.Determination result can be sent to steering logic 150.Steering logic 150 is configured to further based on passing through/the determination output control programmed order of failed check circuit 160.Pass through/failed check circuit 160 can be configured to connect up or (wired-OR) mode or column scan mode check that/failure is passed through in programming.Such as, in U.S. Patent No. 6,282, disclose a kind of possible programming in 121 and pass through/failed check circuit, its theme is incorporated herein by reference.
Input/output buffer circuit 180 in described embodiment is in FIG configured to by random data interface 170, data be sent to external unit from page buffer circuit 120 during read operation.Input/output buffer circuit 180 is configured to by random data interface 170, data be sent to page buffer circuit 120 from external unit further during programming operation.Input/output buffer circuit 180 comprises: input buffer 181, is configured to from outer equipment receiving data; Output buffer 182, is configured to data to export to external unit.
Random data interface 170 is in the described embodiment configured to the data that randomization receives from input/output buffer circuit 180, then randomization data is passed to page buffer circuit 120.Random data interface 170 is configured to the data that randomization receives from page buffer circuit 120 further, and randomization data then will be gone to pass to input/output buffer circuit 180.Random data interface 170 can be configured to selectivity under the control of steering logic 150 and also carry out randomizing data.
Memory device 100 can carry out work according to the request of memory controller.Although not shown in Fig. 1, as understood traditionally, memory controller can comprise processing unit, error correction/detection unit (ECC), memory buffer etc.
Fig. 2 is the block diagram of the random data interface further illustrating Fig. 1.With reference to figure 2, random data interface 170 comprises address buffer 171, random sequence generator 172, first and second XOR (XOR) door 173a and 173b, the first multiplexer 174, first and second strange/even latch 175a and 175b, indexing unit detector 176, multiplex controller 177 and the second multiplexer 178.
Address buffer 171 is configured to receive the address (such as, page address) be provided from outside together with normal read command, then institute's receiver address is sent to random sequence generator 172 as seed.
In embodiment in fig. 2, row address (such as, page address) can be provided to address buffer 171.Or the combination of column address or row address and column address can be provided to address buffer 171.
Random sequence generator 172 can be configured to produce random data (or, random key).In a possible embodiment, random sequence generator 172 can be formed by linear feedback signature register (LFSR).Therefore, random sequence generator 172 can be configured to produce random data based on the output of address buffer 171 and address as seed.
The first XOR gate 173a in the described embodiment performs XOR (XOR) operation to the random data from random sequence generator 172 and the data from input buffer in Fig. 1 181.First XOR gate 173a produces randomization data as combined result.Then first multiplexer 174 selects according to Stochastic choice signal R_SEL the data (that is, randomization data) that export from the first XOR gate 173a or from one of them of the data of input buffer 181.When randomizing data is established, Stochastic choice signal R_SEL is activated.By this way, the randomization to " writing " data being programmed into flash memory can effectively be realized.When randomizing data is not established, do not activate Stochastic choice signal R_SEL.
In an embodiment of concept of the present invention, under the control of steering logic 150, the part as power up routine occurs by randomizing data process.This can utilize and be stored in memory cell array 110 or in non volatile register (such as, insurance circuit), or fine setting (trim) information provided by external unit has been come.
First strange/even latch 175a is configured to the data batchmove that exports from the first multiplexer 174 to page buffer circuit 120.When Stochastic choice signal R_SEL is activated, randomization data will be transferred to page buffer circuit 120.When Stochastic choice signal R_SEL is not activated, derandominzation data will be transferred to page buffer circuit 120.
When asking read operation, page buffer circuit 120 will obtain read data from memory cell array 110.The read data obtained by page buffer circuit 120 is provided to the second XOR gate 173b and the second multiplexer 178 by second strange/even latch 175b.Second XOR gate 173b performs xor operation, to export randomization data to the random data received from random sequence generator 172 with from the data (that is, randomization data) of strange/even latch 175b.
Page buffer circuit 120 determines the state of the data be kept in the indexing unit 111 corresponding with selected wordline/page.And this indexing unit status data is supplied to indexing unit detector 176.Responsively, indexing unit detector 176 determines whether the relevant portion of memory cell array 110 is wiped free of.
Indexing unit detector 176 is configured to control multiplex controller 177 according to the programming state information provided by page buffer circuit 120.The output that multiplex controller 177 is configured to Stochastic choice signal R_SEL and the indexing unit detector 176 provided in response to the steering logic 150 by Fig. 1 controls the second multiplexer 178.
Second multiplexer 178 in response to the output of multiplex controller 177 from the data from strange/even latch 175b with select data among the data (namely going randomization data) of XOR gate 173b.Then data selected is supplied to external unit by the output buffer 182 in Fig. 1.Such as, when the indexing unit data mode received from indexing unit detector 176 exports expression erase status, multiplex controller 177 controls the second multiplexer 178 thus selects the data from strange/even latch 175b, no matter be activate or un-activation Stochastic choice signal R_SEL.Data selected can be from the read data that eraseable memory unit obtains in selected wordline.On the other hand, when the indexing unit data mode of indexing unit detector 176 represents programming state, multiplex controller 177 controls the second multiplexer 178 thus selects the data (in other words, going randomized data) from XOR gate 173b in response to Stochastic choice signal R_SEL.
In another embodiment of of the present invention concept similar to the described embodiment of Fig. 2, multiplex controller 177 can be configured to directly use the indexing unit data state info obtained from page buffer circuit 120.In other words, multiplex controller 177 can be configured to control multiplexer 178 when not usage flag unit detector 176.
Can be configured to write randomizing data to what will be programmed according to the memory device 100 of conceptual embodiment of the present invention, and randomization is gone to the randomization read data obtained from memory cell array.When memory device 100 is wiped free of, the data in all pieces of memory device 100 will be wiped free of.Equipment user may need the object in order to safety and debugging and read obliterated data.In this case, memory device 100 can go randomization to the read data obtained from eraseable memory unit.But, according to conceptual embodiment of the present invention, understood just as described above, likely stop the read data obtained from eraseable memory unit to be gone randomization.
Fig. 3 is the block diagram of a kind of possibility embodiment of the random sequence generator further illustrating Fig. 2.With reference to figure 3, random sequence generator 172 comprises multiple (such as, 10 trigger FF1 to FF10) trigger and XOR gate G1.Random sequence generator 172 in the present embodiment is made up of linear feedback signature register LFSR.In general, LFSR can be used as the equipment producing random data.Random sequence generator 172 can produce random data according to seed and clock signal, and the first and second XOR gate 173a random data is supplied in Fig. 2 and 173b.
Fig. 4 is that description is according to the randomization of the memory device of the embodiment of the present invention and the concept map going randomization operation.
By under the hypothesis be established at randomizing data, write operation is described.Data input buffer 41 receives source data ' 1100 ' from external unit.Then data randomizer 42 pairs of source datas ' 1100 ' do randomization, randomization data ' 1010 ' to be exported to data register 43 (that is, page buffer 120).Therefore, randomization data ' 1010 ' is stored in memory cell array 44.
By under the hypothesis be established at randomizing data, read operation is described.The data of data register 43 reading and saving in memory cell array 43.Then data de-randomizer 45 goes randomization to the data ' 1010 ' read by data register 43.Randomization data ' 1100 ' will be gone to be supplied to external unit by data output buffer 46.
In the aforementioned embodiment, data randomizer 42 and data de-randomizer 45 can be realized by the random data interface 170 of Fig. 2.Such as, data randomizer 42 and data de-randomizer 45 can be configured to the element sharing such as address buffer 171 and random sequence generator 172.Data randomizer 42 may further include XOR gate 173a, multiplexer 174 and strange/even latch 175a.Data de-randomizer 45 may further include very/even latch 175b, XOR gate 173b, indexing unit detector 176, multiplex controller 177 and multiplexer 178.
Fig. 5 describes the concept map according to the normal running of the memory device of the embodiment of the present invention.
Tentation data randomization is not established.Under this assumption normal running will be described, i.e. derandominzation write operation.By data input buffer 51, source data ' 1100 ' is supplied to data register 53, and without data randomizer 52.In other words, randomizing data is not performed.Then the source data ' 1100 ' in data register 53 is saved in memory cell array 54.
By under the hypothesis be not established at randomizing data, normal running is described, i.e. derandominzation read operation.Data register 53 obtains source data ' 1100 ' from memory cell array 54.Then by data output buffer 55, read source data ' 1100 ' is supplied to external unit, and goes randomization without what provided by data de-randomizer 55.
Fig. 6 describes the conceptual schema according to the read operation of the storage unit of the embodiment of the present invention.
With reference to figure 6, data register 62 can read data from eraseable memory unit.Here, assuming that be ' 1 ' from the value of all data bit of eraseable memory unit reading.During read operation, obliterated data is transferred to data de-randomizer 63 from data register 62.If determine that indexing unit state is erase status, then randomization is not gone to it when obliterated data is transferred to data output buffer 64.On the other hand, if determine that indexing unit state is programming state, then before data are transferred to data output buffer 64, first data de-randomizer 63 goes randomization to it.
Fig. 7 sums up the process flow diagram according to the write operation of the memory device of the embodiment of the present invention.
Exemplary write operation comprises: receive data (S11); Determine whether the data (S12) that randomization receives.If need randomizing data (S12=is), then to received data randomization (S13), then by its write storage unit array 110 (S14).Otherwise (S12=is no), by data normal write storage unit array (S15) when not having randomizing data.
Fig. 8 sums up the process flow diagram according to the read operation of the memory device of the embodiment of the present invention.
First, page buffer circuit 120 detects data (S21) from the storage unit be associated with selected wordline.Then based on corresponding indexing unit status data, determine whether to wipe or programme the storage unit (S22) be associated with selected wordline.If the storage unit be associated with selected wordline is wiped free of (S22=is), does not then perform randomization operation and institute's read data is exported to external unit (S23).Otherwise (S22=is no), the storage unit be associated with selected wordline is confirmed as programming, and be output (S25) to external unit before must first be gone randomization (S24).
Fig. 9 is the block diagram schematically describing memory device in accordance with another embodiment of the present invention.
Except special marking unit by from memory cell array 210 remove except, the example storage equipment of Fig. 9 and the memory device of Fig. 1 similar.During read operation, pass through/failed check circuit 260 determines whether the value of all read data bit obtained from page buffer circuit 220 is ' 1 ' (that is, storage unit is in erase status).Such as, when passing through/failed check circuit 260 is when being implemented as and operating in wiring or (wired-OR) mode, can complete this judgement work.Before by data batchmove to random data interface 270, the erase status of read data bit can be determined.Based on by passing through/determined the result of failed check circuit 260, random data interface 270 can export randomization or go randomization read data bit.Therefore, likely prevent the data read from eraseable memory unit from being gone randomization.
Figure 10 is the block diagram of the random data interface further illustrating Fig. 9.
The random data interface 270 of Figure 10 is similar to the random data interface of Fig. 2, just except the indexing unit detector of Fig. 2 is removed, and multiplex controller 276 carrys out work according to the Stochastic choice signal R_SEL received from steering logic and marking signal Erased_pg_rd.Random data interface 270 in mode similar as described in Figure 2 to the randomizing data that will be programmed, therefore can will omit its description.
During read operation, page buffer circuit 220 obtains read data from the storage unit be associated with selected wordline.Then pass through/failed check circuit 260 determines whether read data entirely for ' 1 '.If read data is ' 1 ' entirely, then steering logic activation tagging signal Erased_pg_rd., if read data non-fully is ' 1 ', then steering logic not activation tagging signal Erased_pg_rd.When marking signal Erased_pg_rd is activated, multiplex controller 276 controls multiplexer 278 and selects data from strange/even latch 275b, no matter and Stochastic choice signal R_SEL activates or unactivated state.On the other hand, when marking signal Erased_pg_rd is not activated, multiplex controller 276 is activate or unactivated state according to Stochastic choice signal R_SEL, control multiplexer 278 with select from strange/even latch 275b data and gone in randomized data by XOR gate 276 one.If Stochastic choice signal R_SEL is activated, then randomization data will be able to be gone to transfer to output buffer 282 by multiplexer 277.
In the related embodiment of concept of the present invention, random data interface can be configured to, and when determining that the storage unit be associated with selected wordline is wiped free of, skips the randomizing data undertaken by XOR gate 173b/273b.
In another embodiment, random data interface can be configured to, and utilizes the address counter increasing initial address, goes randomization to the randomization read data obtained during high-speed cache read operation.In this case, the address produced by address counter can be used as the seed of random sequence generator.
Now it should be noted that flash memory is only the nonvolatile memory (that is, can keep the storer of stored data under power-down conditions) of a type.Many mobile electronic devices, such as, cellular telephone, personal digital assistant (PDA), digital camera, portable game terminal and MP3, add flash memory more and more to preserve code and payload data.Similarly, flash memory can be applied more broadly in home appliance, such as, and high definition television machine, digital versatile disc (DVD), router and GPS (GPS).
Figure 11 is the general block diagram of the computing system schematically illustrating the memory device comprised according to the embodiment of the present invention.
With reference to Figure 11, computing system 10 comprises the flash memory 11, memory controller 12, processing unit 13 (such as microprocessor and CPU (central processing unit)), user interface 14 and the modulator-demodular unit 16 (such as baseband chipsets) that are connected with bus 17.Flash memory 11 can be configured in fact as shown in Fig. 1 and Fig. 9.In flash memory 11, by memory controller 12 preserve N bit data handled by processing unit 13 (N be more than or equal to 1 integer).If the computing system shown in Figure 11 is mobile device, it comprises the battery 15 providing power supply further.
Although not shown in Figure 11, computing system can be equipped with application chip group, camera images processor (such as, cmos image sensor, CIS), mobile DRAM etc. further.Such as, memory controller 12 and flash memory 11 can form the solid-state drive (SSD) utilizing nonvolatile memory to preserve data.Such as, in published U.S. Patent application No.2006-0152981, an example SSD is disclosed.Be herein incorporated by reference.Or flash memory 11 and memory controller 12 can form the storage card utilizing nonvolatile memory to preserve data.
Figure 12 is the block diagram of the preservation equipment based on storer schematically illustrating the memory device comprised according to the embodiment of the present invention.
As shown in figure 12, the preservation equipment 20 based on storer can comprise: card 21, it is formed by storer 22 and memory controller 23.Such as, the storage card that 21 can be such as flash memory cards is blocked.In other words, blocking 21 can be the card meeting any industrial standard that the such as electronic equipment such as digital camera, personal computer uses.Should be appreciated that memory controller 23 carrys out control store 22 by card 21 with based on the control signal received from main frame 24.
Theme disclosed above should be considered to illustrative, instead of restrictive, and appended claims intention covers all modifications fallen within the scope of it, enhancing and other embodiment.Therefore, in order to reach the maximum magnitude that law allows, being released by the most extensive admissible solutions of following claim and equivalent thereof and determining scope of the present invention, and not should limit by aforesaid detailed description and limit.
Claims (5)
1. comprise a method of operating for the non-volatile memory device of storage unit, described method comprises:
To programming data randomization to produce randomization programming data;
Preserve randomization programming data;
Wipe a part of randomization programming data, to produce obliterated data; And
During subsequent read operation, respond the indexing unit status data preserved in non-volatile memory device, or (1) obtain preserved randomization programming data from storage unit, and go randomization to produce read data to preserved randomization programming data; Or (2) obtain obliterated data from storage unit, and do not go randomization to produce read data to obliterated data,
Wherein, indexing unit status data indicates the data that will obtain from storage unit to be obliterated data or programming data.
2. method of operating as claimed in claim 1, wherein, comprises programming data randomization:
Seed is produced based on the address corresponding with programming data;
Random key is produced based on this seed; And
This random key is utilized to carry out randomization to programming data.
3. method of operating as claimed in claim 2, wherein, by realizing the randomization to programming data to programming data and random key execution xor operation.
4. a non-volatile memory device, comprising:
Memory cell array, has with the storage unit of row and column form arrangement;
Page buffer circuit, is configured to from memory cell array read data; And
Random data interface, is configured to the programming data randomization to being programmed into memory cell array, and goes randomization to the read data obtained from storage unit selected in memory cell array,
Wherein, in response to the indexing unit status data preserved in non-volatile memory device during read operation, non-volatile memory device is selected and is performed following central operation: (1) operation random data interface obtains preserved randomization programming data from selected storage unit, and goes randomization to produce read data to preserved randomization programming data; (2) operate random data interface and obtain obliterated data from selected storage unit, and do not go randomization to produce read data to obliterated data,
Wherein, random data interface is configured to further, in response to the program/erase state of storage unit selected by determining according to indexing unit status data, when selected storage unit has erase status, do not going to export read data from memory cell array in randomized situation.
5. non-volatile memory device as claimed in claim 4, wherein, random data interface is configured to further, when the selected storage unit of indexing unit status data instruction has programming state, exports and goes randomization data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR18567/09 | 2009-03-04 | ||
| KR1020090018567A KR101504338B1 (en) | 2009-03-04 | 2009-03-04 | Operating method of nonvolatile memory device |
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| CN101853699A CN101853699A (en) | 2010-10-06 |
| CN101853699B true CN101853699B (en) | 2015-07-22 |
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| US (1) | US8874934B2 (en) |
| KR (1) | KR101504338B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8413016B2 (en) * | 2009-04-28 | 2013-04-02 | Panasonic Corporation | Nonvolatile memory device and controller for judging a normal or anomalous condition of an error-corrected bit pattern |
| DE102011056141A1 (en) | 2010-12-20 | 2012-06-21 | Samsung Electronics Co., Ltd. | A negative voltage generator, decoder, non-volatile memory device and memory system using a negative voltage |
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| US20100229001A1 (en) | 2010-09-09 |
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