CN111391512A - Consumable chip and consumable - Google Patents
Consumable chip and consumable Download PDFInfo
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- CN111391512A CN111391512A CN202010411089.6A CN202010411089A CN111391512A CN 111391512 A CN111391512 A CN 111391512A CN 202010411089 A CN202010411089 A CN 202010411089A CN 111391512 A CN111391512 A CN 111391512A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
- B41J2/17566—Ink level or ink residue control
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
- B41J2/17503—Ink cartridges
- B41J2/17543—Cartridge presence detection or type identification
- B41J2/17546—Cartridge presence detection or type identification electronically
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
- B41J2/17566—Ink level or ink residue control
- B41J2002/17589—Ink level or ink residue control using ink level as input for printer mode selection or for prediction of remaining printing capacity
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Abstract
The invention provides a consumable chip and a consumable, comprising a first memory, a second memory and a third memory, wherein the first memory is configured to store first data, and the first data can not be modified; a second memory configured to store second data and modify the second data into third data; and the logic output circuit is connected with the first memory and the second memory and is configured to perform logic operation on the first data output by the first memory and the third data output by the second memory and output an electric signal exceeding a preset range, wherein the preset range is predetermined by the chip and the printing host, so that the electric signal exceeding the preset range is output outwards after the second data is modified, and the reliability of prompting the second data to be modified into the third data is improved.
Description
Technical Field
The invention relates to the technical field of printing and imaging, in particular to a consumable chip and a consumable.
Background
The printing system is equipped with replaceable consumables, and the use of consumables by the printing system results in a reduction in the life of the consumables during the printing process of the printing system. These consumables include, for example, a cartridge or drum that contains the printing material, and consumable chips mounted on the cartridge or drum. The consumable chip is used for storing information data including the updated residual quantity, the attribute, the production date and the like of the printing materials, storing authentication data for authenticating the safety of the consumable by the printing system and the like.
Generally, before printing, a printer reads data in a consumable chip to estimate information such as the life of the consumable. When the consumable allowance recorded in the consumable chip indicates that the life of the consumable is exhausted, the printing system prompts a user to replace the consumable.
However, after some printing systems prompt the user to replace the printer, if the user chooses to continue printing, the printing system will continue printing. Continuing to print can seriously affect print quality because the consumable is already empty of printing material, and in the case of thermal inkjet printing systems, can also damage the print head of the printing system, causing irreversible damage to the printing system. It can be seen that the reliability of the existing consumable chip for prompting the remaining amount of the consumable, for example, is not high enough, and then the printing system using the existing consumable chip is caused, and the reliability is not high enough.
Disclosure of Invention
The invention provides a consumable chip and a consumable, which improve the reliability of prompting that second data is modified into third data, and improve the printing stability of a printing system using the consumable.
According to a first aspect of the invention, there is provided a consumable chip comprising:
a first memory configured to store first data, and the first data is not modifiable;
a second memory configured to store second data and modify the second data into third data;
and the logic output circuit is connected with the first memory and the second memory, and is configured to perform logic operation on the first data output by the first memory and the third data output by the second memory and output an electric signal exceeding a preset range, wherein the preset range is predetermined by the chip and the printing host.
Optionally, the logic output circuit performs a logic operation on the first data output by the first memory and the second data output by the second memory, and outputs an electrical signal conforming to a preset range.
Optionally, the first data is different from the second data, and the first data is the same as the third data.
Optionally, the first data is the same as the second data, and the first data is different from the third data.
Optionally, the first memory includes 1 or more first-class storage units for storing the first data;
the second memory comprises 1 or more second class of memory cells for storing the second data or the third data;
the number of the first type of storage units is consistent with the number of the second type of storage units.
Optionally, the first memory is further configured to respond to an external modification instruction with a first programming rule, and the second memory is configured to respond to an external modification instruction with a second programming rule;
the first programming rule is opposite the second programming rule.
Optionally, the method further comprises:
a first programming circuit connected with the first memory for controlling the first memory to respond to the external modification command by a first programming rule
And the second programming circuit is connected with the second memory and controls the second memory to respond to the external modification instruction according to a second programming rule.
Optionally, the first programming rule indicates that a modification from 0 to 1 is allowed; the second programming rule indicates that a modification from 1 to 0 is allowed.
Optionally, the logic output circuit comprises:
a logical AND circuit configured to logically AND data transferred by the first memory and the second memory.
Optionally, the logical and circuit is a wire connecting the first memory and the second memory data output.
Optionally, the first programming rule indicates that a modification from 1 to 0 is allowed; the second programming rule indicates that a modification from 0 to 1 is allowed. Optionally, the logic output circuit comprises:
a logic OR circuit configured to logically OR data transferred by the first memory and the second memory.
Optionally, the first memory is further configured to store sixth data indicating a preset range of the chip output electrical signal.
According to a second aspect of the invention, there is provided a consumable comprising a consumable chip according to any one of the first aspects of the invention.
According to a third aspect of the present invention there is provided a printing system comprising a printing host and one or more consumables as claimed in any one of the second aspects of the present invention.
The invention provides a consumable chip and a consumable, which comprise a first memory, a second memory and a third memory, wherein the first memory is configured to store first data, and the first data can not be modified; a second memory configured to store second data and modify the second data into third data; and the logic output circuit is connected with the first memory and the second memory and is configured to perform logic operation on the first data output by the first memory and the third data output by the second memory and output an electric signal exceeding a preset range, wherein the preset range is predetermined by the chip and the printing host, so that the electric signal exceeding the preset range is output outwards after the second data is modified, and the reliability of prompting the second data to be modified into the third data is improved.
Drawings
FIG. 1 is a schematic diagram of a printing system provided by an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a consumable chip according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another consumable chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a consumable chip having a wire and a structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 1, a schematic diagram of a printing system according to an embodiment of the present invention is shown. The printing system shown in fig. 1 includes a printing host 11 and a consumable 12 mounted on the printing host 11. The consumable 12 may be, for example, an ink cartridge or a toner cartridge. Consumable chip 20 is also disposed in consumable 12, and is used for recording attribute information of consumable 12 and performing data interaction with host printer 11. In practical applications, there may be a plurality of consumables 12 installed on the host printing machine 11, each consumable 12 is provided with its own consumable chip 20, and the consumable chips 20 provide various attribute information of the consumables 12 to the host printing machine 11 through data interaction with the host printing machine 11. The attribute information includes, for example, consumable remaining amount, consumable color, consumable installation date, or consumable safety certification related information, and is not limited herein. For example, the host computer 11 estimates the remaining life of the consumable 12 by reading the information data of the consumable chip 20, and sends out an out-of-range electric signal to the host computer 11 when the remaining amount of the consumable recorded in the consumable chip 20 indicates exhaustion, and the host computer 11 reports an error and prompts the user to replace the consumable.
Fig. 2 is a schematic structural diagram of a consumable chip according to an embodiment of the present invention. The consumable chip 20 shown in FIG. 2 includes: a first memory 21, a second memory 22 and a logic output circuit 23.
Specifically, the first memory 21 is configured to store first data, and the first data may not be modified. As an embodiment, the first memory 21 may perform write-protected storage on the first data, for example, may be write-protected storage in a software manner, or may be write-protected storage in a hardware manner, which is not limited herein.
With continued reference to fig. 2, the second memory 22 is configured to store the second data and modify the second data into third data. It is understood that the second data is stored in the second memory 22 in a manner that can be modified, and when the second data is modified, it is modified into the third data. The second memory 22 may be configured to modify the second data into the third data in response to an external modification instruction, for example. As one implementation, the first memory 21 and the second memory 22 may be collectively operable in response to an external instruction.
Optionally, the first data, the second data, and the third data are, for example, data relating to a remaining life of the consumable. The first data is, for example, a non-modifiable reference quantity, while the second data is, for example, used to indicate that the remaining ink quantity is sufficient, and the third data is, for example, used to indicate that the remaining ink quantity is insufficient. The physical quantities indicated by the first data, the second data, and the third data are not limited herein.
With continued reference to fig. 2, the logic output circuit 23 is connected to the first memory 21 and the second memory 22, and configured to perform a logic operation on the first data output by the first memory 21 and the third data output by the second memory 22, and output an electrical signal exceeding a preset range, where the preset range is predetermined by the chip and the printing host. The preset range may be understood as a range of electrical signals defining data 0 and data 1 during communication of the consumable chip with the printing host. Generally, the predetermined range is determined by the design stage of the consumable chip and the printing host, and may be solidified in hardware circuits of the consumable chip and the printing host, for example. It should be understood that the first memory 21 and the second memory 22 output signals after performing logic operation on the output data of the first memory 21 and the second memory 22 through the logic output circuit 23. When the first memory 21 outputs the first data and the second memory 22 outputs the third data, the logic operation of the logic output circuit 23 outputs an electrical signal exceeding a predetermined range.
In one embodiment, the predetermined range is, for example, a voltage input/output range predetermined by the consumable chip and the printing host, for example, an electrical signal with a predetermined voltage within 3-5V represents data 0, an electrical signal with a voltage within 7-9V represents data 1, and an electrical signal exceeding the predetermined range is an electrical signal with a voltage less than 3V, or greater than 5V and less than 7V, or greater than 9V. The printing host may report an error and stop printing, for example, when receiving the electric signal output by the consumable chip and exceeding the preset range. In this embodiment, the preset range may not be limited to one or a combination of a voltage range, a current range, and a frequency range, and the preset range may be a continuous range or a discontinuous range, which is not limited herein. The chip and the printer recognize whether the electrical signal during communication represents data 0 or data 1 according to the preset range, which is the meaning of the preset range mentioned in the present invention.
The preconceiving of the consumable chip and the printing host to the preset range may mean that the consumable chip and the printing host are installed in the preset range to perform circuit design or software configuration. For example, the configuration of the compatible electrical characteristics of the input/output interface module of the printing host and the configuration of the output characteristics of the consumable chip should be matched, so that the printing host is compatible with the consumable chip. The consumable chip can also store data indicating a preset range, and the printing host can realize the appointment of the preset range by reading the data indicating the preset range. If the electric signal received from the consumable chip exceeds the preset range, the printing host stops working, and can also report errors or prompt a user to replace corresponding consumables.
As a specific implementation manner, in the present embodiment, the first memory 21 and the second memory 22 may respond to the external instruction simultaneously. For example, if the received external command is to read the data at the location D1, the data at the location D1 in the first memory 21 and the data at the location D1 in the second memory 22 are output to the logic output circuit 23 at the same time. Also for example, if the received external command is a modification of data at the memory address D2, then the data at the D2 location in the first memory 21 and the data at the D2 location in the second memory 22 respond to the modification at the same time, wherein the modification is rejected if the data at the D2 location in the first memory 21 is a write-protected memory.
In some embodiments, the logic output circuit 23 may further perform a logic operation on the first data output by the first memory 21 and the second data output by the second memory 22, and output an electrical signal meeting a preset range. For example, the second memory 22 is further configured to output data to the logic output circuit 23 according to the modifiable stored second data in response to an external read instruction before modifying the second data into the third data. Accordingly, the logic output circuit 23 is further configured to perform a logic operation on the data output by the first memory 21 according to the first data and the data output by the second memory 22 according to the second data, and output an electrical signal conforming to a preset range. It should be understood that, when the second data is output from the second memory 22, the logical operation result of the first data and the second data is within the preset range, and the host computer receives the electrical signal output by the consumable chip at this time and operates normally.
The consumable chip provided by the embodiment comprises a first memory, a second memory and a control module, wherein the first memory is configured to store first data, and the first data cannot be modified; a second memory configured to store second data, the second data being modifiable to third data; and the logic output circuit is connected with the first memory and the second memory, and is configured to perform logic operation on the first data output by the first memory and the third data output by the second memory and output an electric signal exceeding a preset range, wherein the preset range is predetermined by the chip and the printing host, so that the electric signal exceeding the preset range is output outwards after the second data is modified, and the reliability of prompting the second data to be modified into the third data is improved.
In the above embodiment, the first data and the second data may be the same or different.
In some embodiments, the first data is different from the second data, and the first data is the same as the third data. If the outputs of the first memory and the second memory are different, the logic output circuit outputs the electric signal which is in accordance with the preset range, otherwise, if the outputs of the first memory and the second memory are the same, the logic output circuit outputs the electric signal which is out of the preset range.
In other embodiments, the first data is the same as the second data, and the first data is different from the third data. The first memory and the second memory output the same, the logic output circuit outputs the electric signal which is in accordance with the preset range, otherwise, the first memory and the second memory output the different, the logic output circuit outputs the electric signal which is out of the preset range.
In the above various embodiments, the data lengths of the first data, the second data, and the third data are the same. The first memory comprises 1 or more first-type memory cells for storing the first data; the second memory comprises 1 or more second class of memory cells for storing the second data or the third data; the number of the first type of storage units is consistent with the number of the second type of storage units. For example, the first data, the second data, and the third data are all 1-bit data, the first memory includes 1 first-type memory cell, and the second memory includes 1 second-type memory cell. For another example, if the first data, the second data, and the third data are all 8-bit data, the first memory includes 8 first-type memory cells, and the second memory includes 8 second-type memory cells. Each first type of memory cell or second type of memory cell stores 1 bit of data.
In the above embodiments, the first memory and the second memory may be memories having different functions and structures, or may be memories having the same function and structure.
For example, the first memory is further configured to respond to an external modification instruction with a first programming rule. The second memory is further configured to respond to the external modification instruction with a second programming rule; and, the first programming rule is opposite to the second programming rule.
In some embodiments, the first memory and the second memory are different in function and structure, and when the first memory and the second memory receive the external modification instruction at the same time, the first memory modifies the data, which the external modification instruction indicates to modify, according to a first programming rule, and the second memory modifies the data, which the external modification instruction indicates to modify, according to a second programming rule opposite to the first programming rule. For example, the first memory modifies the stored modifiable data from 0 to 1, but the second memory modifies the stored modifiable data from 1 to 0. The first memory and the second memory respond to the modification of the external modification instruction, and modify the data stored in a storage mode of being capable of being modified, but do not modify the data stored in a write-protection mode.
In other embodiments, referring to fig. 3, a schematic diagram of a consumable chip structure according to another embodiment of the present invention is provided. The consumable chip as shown in fig. 3 further comprises a first programming circuit 31 and a second programming circuit 32. In the embodiment shown in fig. 3, the first memory 21 and the second memory 22 may be memories having the same function and structure. The first programming circuit 31 is connected to the first memory 21, and the first programming circuit 31 controls the first memory 21 to respond to the external modification command with a first programming rule. A second programming circuit 32 is coupled to the second memory 22, the second programming circuit 32 controlling the second memory 22 to respond to the external modification command with a second programming rule. The second programming rule is opposite the first programming rule. It can be seen that the corresponding programming circuits of the first memory 21 and the second memory 22 are different, so that the programming logic of the first memory 21 is the same as the programming logic agreed by the printer host and the consumable chip, and the programming logic of the second memory 22 is opposite to the programming logic agreed by the printer host and the consumable chip.
In the above embodiment, the first programming rule is opposite to the second programming rule, and for example, the first programming rule indicates that modification from 0 to 1 is allowed; the second programming rule indicates that a modification from 1 to 0 is allowed. Alternatively, the first programming rule is the opposite of the second programming rule, again for example the first programming rule indicates that a modification from 1 to 0 is allowed; the second programming rule indicates that a modification from 0 to 1 is allowed. The first programming rule may be a programming rule agreed by the printing host and the consumable chip, for example. For example, the printer host and the consumable chip agree to allow the data in the consumable chip to be modified from 0 to 1, and not allow the data to be modified otherwise. For another example, the printer host and the consumable chip agree to allow the data in the consumable chip to be modified from 1 to 0, and not otherwise.
In some embodiments, the logic output circuit 23 shown in fig. 2 and 3 may include a logic and circuit or a logic or circuit.
In an embodiment where the logic output circuit comprises a logic and circuit, the logic and circuit is configured to logically and the data transferred by the first memory and the second memory. In some embodiments, the first data is different from the second data, and if the first memory outputs a write-protected stored 0 and the second memory outputs an unmodified 1, the logical and circuit outputs an electrical signal indicating 0 that meets a preset range; if the first memory outputs a write-protected stored 0 and the second memory outputs a modified 0 (modified from 1 to 0), the logical and circuit outputs an electric signal exceeding a preset range. In other embodiments, the first data is different from the second data, and if the first memory outputs a write-protected stored 1 and the second memory outputs an unmodified 0, the logical and circuit outputs an electrical signal representing 0 that meets a predetermined range; if the first memory outputs a write-protected stored 1 and the second memory outputs a modified 1 (modified from 0 to 1), the logical and circuit outputs an electrical signal exceeding a preset range. In still other embodiments, the first data is the same as the second data, and if the first memory outputs a write-protected stored 1 and the second memory outputs an unmodified 1, the logical and circuit outputs an electrical signal indicating 1 that meets a preset range; if the first memory outputs a write-protected stored 1 and the second memory outputs a modified 0 (modified from 1 to 0), the logical and circuit outputs an electrical signal outside a preset range. In still other embodiments, the first data is the same as the second data, and if the first memory outputs a write-protected stored 0 and the second memory outputs an unmodified 0, the logical and circuit outputs an electrical signal indicating 0 that meets a predetermined range; if the first memory outputs a write-protected stored 0 and the second memory outputs a modified 1 (from 0 to 1), the logical and circuit outputs an electrical signal outside a preset range.
Referring to fig. 4, a schematic diagram of a consumable chip structure with wires and structures according to an embodiment of the present invention is shown as an implementation of logic and circuits. The logical and circuit 23 shown in fig. 4 is a conductor connecting the data outputs of the first memory 21 and the second memory 22. The first memory 21 and the second memory 22 output data to the logic output circuit, which may be output through ID lines of the memories, and then the ID lines of the first memory 21 and the second memory 22 are interconnected to form a line and structure. In the embodiment to which the line and structure provided in fig. 4 is applied, if the first data is different from the second data, one of the first memory 21 and the second memory 22 outputs a low level signal indicating 0 before the second data is modified into the third data, and the other outputs a high level signal indicating 1, and then the low level signal indicating 0 and the high level signal indicating 1 output low level electrical signals conforming to a preset range indicating 0 after and after the line and the line; after the second data is modified into the third data, the first memory 21 and the second memory 22 simultaneously output a low level signal representing 0 or a high level signal representing 1, and then both the low level signal representing 0 and the high level signal representing 1 are wired and then both output an electrical signal beyond a preset range. Wherein, two low level signals representing 0 are wired to each other and the electrical signal lower than the lowest value of the preset range is obtained, and two high level signals representing 1 are wired to each other and the electrical signal higher than the highest value of the preset range is obtained.
In embodiments where the logic output circuit comprises a logic or circuit, the logic or circuit is configured to logically or data transferred by the first memory and the second memory. In some embodiments, the first data is different from the second data, and if the first memory outputs a write-protected stored 0 and the second memory outputs an unmodified 1, the logic or circuit outputs an electrical signal indicating 1 that meets a preset range; if the first memory outputs a write-protected stored 0 and the second memory outputs a modified 0 (from 1 to 0), the logical or circuit outputs an electrical signal exceeding a preset range. In other embodiments, the first data is different from the second data, and if the first memory outputs a write-protected stored 1 and the second memory outputs an unmodified 0, the logic or circuit outputs an electrical signal indicating 1 that meets a preset range; if the first memory outputs a write-protected stored 1 and the second memory outputs a modified 1 (from 0 to 1), the logical or circuit outputs an electrical signal exceeding a preset range. In still other embodiments, the first data is the same as the second data, and if the first memory outputs a write-protected stored 1 and the second memory outputs an unmodified 1, the logic or circuit outputs an electrical signal indicating 1 that meets a preset range; if the first memory outputs a write-protected stored 1 and the second memory outputs a modified 0 (modified from 1 to 0), the logical or circuit outputs an electrical signal exceeding a preset range. In still other embodiments, the first data is the same as the second data, and if the first memory outputs a write-protected stored 0 and the second memory outputs an unmodified 0, the logic or circuit outputs an electrical signal indicating 0 that meets a preset range; if the first memory outputs a write-protected stored 0 and the second memory outputs a modified 1 (from 0 to 1), the logical or circuit outputs an electrical signal outside a preset range.
In the above embodiment, the first memory may be further configured to perform modifiable storage of preset fourth data. The fourth data in the consumable chip can be read and rewritten normally, and because the programming logic of the first memory is the same as the programming logic agreed by the printing host and the chip, when the printer rewrites the fourth data, the expectation of the printer is met, and the consumable chip works normally. The fourth data is, for example, other attribute data of the consumable chip than the first data, such as data indicating a color of the consumable, a mounting time of the consumable, a production time of the consumable, a usage state of the consumable, a capacity of the consumable, and/or a manufacturer of the consumable. Accordingly, the second memory is further configured to write-protect storage of preset fifth data. The fifth data is, for example, non-modifiable invalid information such as data constituted by all 1 s or all 0 s. The content of the fifth data is set with a view to enabling the fourth data to be normally output. For example, the logic output circuit is a logic and circuit, the electrical signal beyond a preset range is output when the first data is 0 and the third data is 0, then the fourth data is 000, and then the fifth data is 111 that is not modifiable. For another example, the logic output circuit is a logic or circuit, the electrical signal beyond the preset range is output when the first data is 1 and the third data is 1, then the fourth data is 111, and then the fifth data is 000 that is not modifiable. In order to save costs, the second memory may be the same size as the first memory, i.e. both memories have the same address length, in addition to the same memory as the first memory. Therefore, the first memory and the second memory are identical, and the first programming circuit and the second programming circuit can respectively control the corresponding first memory and the second memory to carry out data modification. By setting the fifth data in the second memory, the logic output circuit outputs an electric signal indicating the fourth data when the first memory and the second memory simultaneously output the fourth data and the fifth data in response to an external read instruction. The output of the fifth data does not affect the fourth data. In this embodiment, the logic output circuit is further configured to perform a logic operation on the fourth data output by the first memory and the fifth data output by the second memory, and output a logic operation result indicating the fourth data and conforming to the chip output electrical range.
On the basis of the various embodiments described above, the first memory may be further configured to store sixth data indicating a preset range of the chip output electric signal. For example, the printing host can obtain the preset range by reading the sixth data, so as to implement the agreement with the consumable chip on the preset range. For example, when the ink amount of the consumable is sufficient, the second data stored in the second memory is not rewritten into the third data, and then various outputs of the consumable chip conform to the preset range indicated by the sixth data; however, when the amount of ink of the consumable is insufficient, the second data stored in the second memory is rewritten to the third data, and then all the electric signals output from the consumable chip, or the electric signals output for the third data, are out of the preset range indicated by the sixth data. And the printing host stops printing after detecting the electric signal exceeding the preset range.
The invention also provides a consumable, which comprises the consumable chip in any embodiment.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
It should be understood that in the present application, "comprising" and "having" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that, in the present invention, "a plurality" means two or more. "and/or" is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "comprises A, B and C" and "comprises A, B, C" means that all three of A, B, C comprise, "comprises A, B or C" means that one of A, B, C comprises, "comprises A, B and/or C" means that any 1 or any 2 or 3 of A, B, C comprises.
It should be understood that in the present invention, "B corresponding to a", "a corresponds to B", or "B corresponds to a" means that B is associated with a, and B can be determined from a. Determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
It is to be understood that, in the present invention, unless otherwise expressly specified or limited, the term "connected" is to be interpreted broadly, as meaning "connected", "coupled", and the like, e.g. electrically connected or capable of communicating with each other; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
As used herein, "if" may be interpreted as "at … …" or "when … …" or "in response to a determination" or "in response to a detection", depending on the context.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. A consumable chip, comprising:
a first memory configured to store first data, and the first data is not modifiable;
a second memory configured to store second data and modify the second data into third data;
and the logic output circuit is connected with the first memory and the second memory, and is configured to perform logic operation on the first data output by the first memory and the third data output by the second memory and output an electric signal exceeding a preset range, wherein the preset range is predetermined by the chip and the printing host.
2. The consumable chip of claim 1, wherein the logic output circuit performs a logic operation on the first data output from the first memory and the second data output from the second memory, and outputs an electrical signal that meets a predetermined range.
3. The consumable chip of claim 2, wherein the first data is different from the second data, and the first data is the same as the third data.
4. The consumable chip of claim 2, wherein the first data is the same as the second data, and the first data is different from the third data.
5. The consumable chip of claim 2, wherein the first memory comprises 1 or more first class memory cells for storing the first data;
the second memory comprises 1 or more second class of memory cells for storing the second data or the third data;
the number of the first type of storage units is consistent with the number of the second type of storage units.
6. The consumable chip of claim 2,
the first memory is further configured to respond to an external modification instruction with a first programming rule;
the second memory is further configured to respond to an external modification instruction with a second programming rule;
the first programming rule is opposite the second programming rule.
7. The consumable chip of claim 2, further comprising:
the first programming circuit is connected with the first memory and controls the first memory to respond to an external modification instruction according to a first programming rule;
and the second programming circuit is connected with the second memory and controls the second memory to respond to the external modification instruction according to a second programming rule.
8. The consumable chip of claim 7, wherein the first programming rule indicates that a modification from 0 to 1 is allowed; the second programming rule indicates that a modification from 1 to 0 is allowed.
9. The consumable chip of any one of claims 1 to 8, wherein the logic output circuit comprises:
a logical AND circuit configured to logically AND data transferred by the first memory and the second memory.
10. The consumable chip of claim 9, wherein the logical and circuit is a wire connecting the first memory and the second memory data output.
11. The consumable chip of any one of claims 1 to 7, wherein the logic output circuit comprises:
a logic OR circuit configured to logically OR data transferred by the first memory and the second memory.
12. The consumable chip according to any one of claims 1 to 8,
the first memory is further configured to store sixth data indicating a preset range of the chip output electrical signal.
13. A consumable comprising a consumable chip according to any one of claims 1 to 12.
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| CN202010411089.6A CN111391512B (en) | 2020-05-15 | 2020-05-15 | Consumable chip and consumable |
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| CN202010411089.6A CN111391512B (en) | 2020-05-15 | 2020-05-15 | Consumable chip and consumable |
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Cited By (1)
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| CN113103765A (en) * | 2021-04-02 | 2021-07-13 | 杭州旗捷科技有限公司 | Printing consumable authentication method, printing consumable chip, printing consumable and printing system |
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Address after: 519060 building 01, 83 Guangwan street, Xiangzhou District, Zhuhai City, Guangdong Province Patentee after: Jihai Microelectronics Co.,Ltd. Address before: 519060 building 01, 83 Guangwan street, Xiangzhou District, Zhuhai City, Guangdong Province Patentee before: APEX MICROELECTRONICS Co.,Ltd. |