CN111061333A - Reference comparison circuit - Google Patents
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- CN111061333A CN111061333A CN202010189073.5A CN202010189073A CN111061333A CN 111061333 A CN111061333 A CN 111061333A CN 202010189073 A CN202010189073 A CN 202010189073A CN 111061333 A CN111061333 A CN 111061333A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
The invention provides a reference comparison circuit, which comprises a voltage detection module, a comparison module connected with the voltage detection module and an output module connected with the comparison module, wherein the voltage detection module is used for detecting the voltage of a reference signal; the voltage detection module comprises a divider resistor and is used for providing a first voltage related to the input voltage and a second voltage generated by the divider resistor; the comparison module comprises a current conversion module and a current mirror module connected with the current conversion module; the current conversion module is used for converting the second voltage into a corresponding first current and a corresponding second current, and the comparison module is used for comparing the first current mirrored by the current mirror module with the second current and outputting voltage according to the comparison result; and the output module is used for outputting a corresponding level value according to the output voltage, so that a comparator circuit occupying a larger chip area can be omitted, and the layout area is saved.
Description
Technical Field
The invention relates to the technical field of comparison circuits, in particular to a reference comparison circuit.
Background
In general, a rechargeable battery needs various protection circuits to protect the normal operation of the battery, such as an overcharge voltage protection circuit, an overdischarge voltage protection circuit, an overcurrent protection circuit, a short circuit protection circuit, and the like. The working principle of the voltage detection protection circuit is that an input voltage is subjected to resistance voltage division and then is compared with a reference voltage irrelevant to temperature through a comparator, and the output end of the comparator outputs a high-low level state to represent a voltage overvoltage/undervoltage state.
In the prior art, two circuit structures of a band gap reference voltage generating circuit and a comparator circuit are required to be used simultaneously. These two circuit structures consume a large chip area, which is not favorable for reducing the cost and miniaturizing the package.
Disclosure of Invention
The embodiment of the invention provides a reference comparison circuit, which reduces the complexity of a circuit structure and the occupied area of a chip, and can reduce the cost and the miniaturization of a package.
An embodiment of the present invention provides a reference comparison circuit, including: the voltage detection module, the comparison module connected with the voltage detection module and the output module connected with the comparison module;
the voltage detection module comprises a voltage dividing resistor and is used for providing a first voltage related to the input voltage and a second voltage generated by the voltage dividing resistor;
the comparison module comprises a current conversion module and a current mirror module connected with the current conversion module; the current conversion module is used for converting the second voltage into a corresponding first current and a corresponding second current, and the comparison module is used for comparing the first current mirrored by the current mirror module with the second current and outputting voltage according to the comparison result;
and the output module is used for outputting a corresponding level value according to the output voltage.
Optionally, the voltage detection module includes a third resistor and a voltage dividing resistor, where the voltage dividing resistor includes a fourth resistor;
one end of the third resistor is connected with the input voltage, the other end of the third resistor is connected with the fourth resistor, one end of the fourth resistor is connected with the third resistor, and the other end of the fourth resistor is grounded;
the voltage detection module acquires the first voltage related to the input voltage according to the third resistor and acquires the second voltage according to the fourth resistor.
Optionally, the current conversion module includes a transistor group for converting the second voltage into a corresponding first current and a second current.
Optionally, the transistor group includes a first transistor, a second transistor, a first resistor, and a second resistor;
the base electrode of the first triode is connected with the base electrode of the second triode, and is simultaneously connected with the middle node of the third resistor and the fourth resistor, the emitting electrode of the first triode is connected with the middle node of the first resistor and the second resistor, and the collecting electrode of the first triode is connected with the current mirror module;
an emitter of the second triode is connected with one end, far away from the second resistor, of the first resistor;
one end of the second resistor, which is far away from the first resistor, is connected with one end of the fourth resistor, which is far away from the third resistor;
the current conversion module obtains the first current according to the first triode and the second voltage, and obtains the second current according to the second triode and the second voltage.
Optionally, the transistor group comprises a first N-type mos transistor, a second N-type mos transistor, a first resistor and a second resistor;
the grid electrode of the first N-type mos tube is connected with the grid electrode of the second N-type mos tube, and is simultaneously connected with the middle node of the third resistor and the middle node of the fourth resistor, the source electrode of the first N-type mos tube is connected with the middle node of the first resistor and the second resistor, and the drain electrode of the first N-type mos tube is connected with the current mirror module;
the source electrode of the second N-type mos tube is connected with one end, far away from the second resistor, of the first resistor;
one end of the second resistor, which is far away from the first resistor, is connected with one end of the fourth resistor, which is far away from the third resistor;
the current conversion module obtains the first current according to the first N-type mos tube and the second voltage, and obtains the second current according to the second N-type mos tube and the second voltage.
Optionally, the second N-type mos tube includes a plurality of N-type mos tubes connected in parallel with each other.
Optionally, the second N-type mos tube comprises 10N-type mos tubes connected in parallel to each other.
Optionally, the current mirror module comprises a first P-type mos tube and a second P-type mos tube;
the grid electrode of the first P-type mos tube is connected with the grid electrode of the second P-type mos tube, the grid electrode of the first P-type mos tube is connected with the drain electrode of the first P-type mos tube, the source electrode of the first P-type mos tube is connected with a power supply, and the drain electrode of the first P-type mos tube is connected with the current conversion module;
the source electrode of the second P-type mos tube is connected with a power supply, and the drain electrode current conversion module of the second P-type mos tube is connected with the input end of the output module;
the current mirror module mirrors the first current according to the first P-type mos tube and the second P-type mos tube.
Optionally, the width-to-length ratio of the first P-type mos tube to the second P-type mos tube is 1: 1.
Optionally, the output module includes an amplifier, and the amplifier is configured to output a corresponding level value according to the output voltage;
one input end of the amplifier is connected with the source electrode of the second P-type mos tube, and the other input end of the amplifier is connected with the drain electrode of the second P-type mos tube and the middle node of the current conversion module.
An embodiment of the present invention provides a reference comparison circuit, including: the voltage detection module, the comparison module connected with the voltage detection module and the output module connected with the comparison module; the voltage detection module is used for providing a first voltage related to the input voltage and a second voltage generated by a divider resistor; the comparison module comprises a current conversion module and a current mirror module connected with the current conversion module; the current conversion module is used for converting the second voltage into a corresponding first current and a corresponding second current, and the comparison module is used for comparing the first current mirrored by the current mirror module with the second current and outputting voltage according to the comparison result; and the output module is used for outputting a corresponding level value according to the output voltage. According to the invention, a digital logic signal for outputting high and low levels is obtained through the voltage detection module, the voltage detection module and the comparison module, compared with the prior art, a comparator can be omitted, a comparator circuit occupying a larger chip area can be omitted, and the layout area is saved.
It should be understood that what is described in the summary above is not intended to limit key or critical features of embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a reference comparison circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another reference comparison circuit according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of another reference comparison circuit according to a third embodiment of the present invention.
Reference numerals:
1. a voltage detection module; 2. a comparison module; 2a, a current conversion module; 2b, a current mirror module 3 and an output module.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and the embodiments of the present invention are illustrative only and are not intended to limit the scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, and in the above-described drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1 is a schematic structural diagram of a reference comparison circuit according to an embodiment of the present invention, and as shown in fig. 1, the reference comparison circuit according to the embodiment includes: the voltage detection circuit comprises a voltage detection module 1, a comparison module 2 connected with the voltage detection module 1, and an output module 3 connected with the comparison module 2.
Specifically, the voltage detection module 1 includes a voltage dividing resistor, and the voltage detection module 1 is configured to provide a first voltage related to the input voltage and a second voltage generated by the voltage dividing resistor.
In some embodiments, the voltage detection module 1 includes a third resistor R3 and a voltage dividing resistor, the voltage dividing resistor may be a fourth resistor R4, wherein one end of the third resistor R3 is connected to the input voltage, the other end of the third resistor R4 is connected to the fourth resistor R4, one end of the fourth resistor R4 is connected to the third resistor R3, and the other end of the fourth resistor R4 is grounded, and the voltage detection module 1 obtains the first voltage according to the third resistor R3 and generates the second voltage with the fourth resistor R4.
Specifically, the comparison module 2 comprises a current conversion module 2a and a current mirror module 2b connected with the current conversion module 2 a; the current conversion module 2a is configured to convert the second voltage into a corresponding first current and a corresponding second current, and the comparison module 2 is configured to compare the first current mirrored by the current mirror module 2b with the second current, and output a voltage according to a comparison result.
It is understood that the current converting module 2a is configured to convert the second voltage acquired by the voltage detecting module 1 into the first current and the second current.
In some embodiments, the current conversion module 2a may include a transistor group for converting the second voltage into the corresponding first current and second current.
The transistor group may include a first transistor Q1, a second transistor Q2, a first resistor R1, and a second resistor R2; the base electrode of the first triode Q1 is connected with the base electrode of the second triode Q2, and is simultaneously connected with the middle node of the third resistor R3 and the fourth resistor R4, the emitting electrode of the first triode Q1 is connected with the middle node of the first resistor R1 and the second resistor R2, and the collecting electrode of the first triode Q1 is connected with the current mirror module 2 b; an emitter of the second triode Q2 is connected with one end of the first resistor R1 far away from the second resistor R2; the end of the second resistor R2 far away from the first resistor R1 is connected with the end of the fourth resistor R4 far away from the third resistor R3; the current converting module 2a obtains a first current according to the first transistor Q1 and the second voltage, and obtains a second current according to the second transistor Q2 and the second voltage.
It is to be understood that the currents at the first transistor Q1 and the second transistor Q2 are first and second currents, respectively.
It can be appreciated that the current mirror module 2b mirrors the first current according to the first and second P-type mos transistors PM1 and PM 2.
Specifically, the current mirror module 2b includes a first P-type mos tube PM1 and a second P-type mos tube PM 2; the grid electrode of the first P-type mos tube PM1 is connected with the grid electrode of the second P-type mos tube PM2, the grid electrode of the first P-type mos tube PM1 is connected with the drain electrode of the first P-type mos tube PM1, the source electrode of the first P-type mos tube PM1 is connected with the power supply, and the drain electrode of the first P-type mos tube PM1 is connected with the current conversion module 2 a; the source electrode of the second P-type mos tube PM2 is connected with a power supply, and the drain electrode current conversion module 2a of the second P-type mos tube PM2 is connected with the input end of the output module 3; the current mirror module 2b mirrors the first current according to the first and second P-type mos transistors PM1 and PM 2.
It is understood that, where the first P-type mos transistor PM1 is a master mirror in the current mirror module 2b and the second P-type mos transistor PM2 is a slave mirror in the current mirror module 2b, the first P-type mos transistor PM1 may be configured to receive a first current provided by the current converting module 2a and then mirror the first current to the second P-type mos transistor PM2, i.e., the current at the second P-type mos transistor PM2 is the first current.
In the present embodiment, a comparison between the first current at the second P-type mos transistor PM2 and the second current between the second transistor Q2 is used.
In some embodiments, the width to length ratio of the first P-type mos tube PM1 and the second P-type mos tube PM2 is 1: 1. It can be understood that if the ratio of the first P-type mos tube PM1 to the second P-type mos tube PM2 is 1:1, then the voltage detection flip threshold at VIN end is
At which the voltage at the output terminal VOUT flips, the temperature coefficient of the voltage detection threshold can be brought close to zero by adjusting the ratio of R1 and R2.
Specifically, the output module 3 is configured to output a corresponding level value according to the output voltage.
The output module 3 comprises an amplifier, and the amplifier is used for outputting a corresponding level value according to the output voltage; in some embodiments, one input terminal of the amplifier is connected to the source of the second P-type mos transistor PM2, and the other input terminal is connected to the drain of the second P-type mos transistor PM2 and the intermediate node of the current conversion module 2 a.
According to the invention, the voltage detection module 1 and the comparison module 2 are adopted to obtain a digital logic signal for outputting high and low levels, and compared with the prior art, a comparator can be omitted, a comparator circuit occupying a larger chip area can be omitted, and the layout area is saved. In addition, the proportion of the first resistor R1 and the second resistor R2 can be adjusted to enable the temperature coefficient of the voltage detection threshold to be close to zero, and the influence of temperature on the base station comparison circuit is reduced.
Example two
Fig. 2 is a schematic structural diagram of another reference comparison circuit provided in the embodiment of the present invention, and as shown in fig. 2, the difference between the reference comparison circuit provided in this embodiment and the reference comparison circuit provided in the first embodiment of the present invention is:
the transistor group comprises a first N-type mos transistor M1, a second N-type mos transistor Q2, a first resistor R1 and a second resistor R2; the grid electrode of the first N-type mos tube M1 is connected with the grid electrode of the second N-type mos tube Q2, and is simultaneously connected with the middle node of the third resistor R3 and the fourth resistor R4, the drain electrode of the first N-type mos tube M1 is connected with the middle node of the first resistor R1 and the second resistor R2, and the drain electrode of the first N-type mos tube is connected with the current mirror module 2 b; the drain electrode of the second N-type mos transistor Q2 is connected with one end, far away from the second resistor R2, of the first resistor R1; the end of the second resistor R2 far away from the first resistor R1 is connected with the end of the fourth resistor R4 far away from the third resistor R3; the current conversion module 2a obtains a first current according to the first N-type mos transistor M1 and the second voltage, and obtains a second current according to the second N-type mos transistor Q2 and the second voltage.
Wherein the second N-type mos tube Q2 includes a plurality of N-type mos tubes connected in parallel with each other, in some embodiments, the second N-type mos tube Q2 may include 10N-type mos tubes connected in parallel with each other.
In the present embodiment, if the width-to-length ratio of the first N-type mos tube M1 and the second N-type mos tube Q2 is large, the first N-type mos tube M1 and the second N-type mos tube Q2 will operate in the subthreshold region during actual operation.
In some embodiments, the width to length ratio of the first P-type mos tube PM1 and the second P-type mos tube PM2 is 1: 1. It can be understood that if the ratio of the first P-type mos tube PM1 to the second P-type mos tube PM2 is 1:1, then the voltage detection flip threshold at VIN end is
At which the voltage at the output terminal VOUT flips, the temperature coefficient of the voltage detection threshold can be brought close to zero by adjusting the ratio of R1 and R2.
EXAMPLE III
Fig. 3 is a schematic structural diagram of another reference comparison circuit provided in the third embodiment of the present invention, and as shown in fig. 3, the difference between the reference comparison circuit provided in this embodiment and the reference comparison circuit provided in the first embodiment of the present invention is:
the current mirror module 2b comprises a first P-type mos tube PM1 and a second P-type mos tube PM 2; the grid electrode of the first P-type mos tube PM1 is connected with the grid electrode of the second P-type mos tube PM2, the grid electrode of the second P-type mos tube PM2 is connected with the drain electrode of the second P-type mos tube PM2, the source electrode of the first P-type mos tube PM1 is connected with a power supply, and the drain electrode of the first P-type mos tube PM1 is connected with the current conversion module 2 a; the source electrode of the second P-type mos tube PM2 is connected with the power supply, and the drain electrode of the first P-type mos tube PM1 is connected with the current conversion module 2a and the input end of the output module 3; the current mirror module 2b mirrors the first current according to the first and second P-type mos transistors PM1 and PM 2.
It is understood that the second P-type mos transistor PM2 is a master mirror in the current mirror module 2b, the first P-type mos transistor PM1 is a slave mirror in the current mirror module 2b, and the second P-type mos transistor PM2 may be configured to receive the second current provided by the current converting module 2a and then mirror the second current to the first P-type mos transistor PM1, that is, the current at the first P-type mos transistor PM1 is the second current.
One input end of the amplifier of the output module 3 is connected with the source electrode of the second P-type mos transistor PM2, and the other input end is connected with the drain electrode of the first P-type mos transistor PM1 and the middle node of the current conversion module 2 a. That is, the second current at the first P-type mos transistor PM1 is compared with the first current between the first transistor Q1 in this embodiment.
In some embodiments, the width to length ratio of the first P-type mos tube PM1 and the second P-type mos tube PM2 is 1: 1. It can be understood that if the ratio of the first P-type mos tube PM1 to the second P-type mos tube PM2 is 1:1, then the voltage detection flip threshold at VIN end is
At which the voltage at the output terminal VOUT flips, the temperature coefficient of the voltage detection threshold can be brought close to zero by adjusting the ratio of R1 and R2.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A reference comparison circuit, comprising: the voltage detection module, the comparison module connected with the voltage detection module and the output module connected with the comparison module;
the voltage detection module comprises a voltage dividing resistor and is used for providing a first voltage related to the input voltage and a second voltage generated by the voltage dividing resistor;
the comparison module comprises a current conversion module and a current mirror module connected with the current conversion module; the current conversion module is used for converting the second voltage into a corresponding first current and a corresponding second current, and the comparison module is used for comparing the first current mirrored by the current mirror module with the second current and outputting voltage according to the comparison result;
and the output module is used for outputting a corresponding level value according to the output voltage.
2. The reference comparator circuit of claim 1, wherein the voltage detection module comprises a third resistor and a voltage divider resistor, wherein the voltage divider resistor comprises a fourth resistor;
one end of the third resistor is connected with the input voltage, the other end of the third resistor is connected with the fourth resistor, one end of the fourth resistor is connected with the third resistor, and the other end of the fourth resistor is grounded;
the voltage detection module acquires the first voltage related to the input voltage according to the third resistor and acquires the second voltage according to the fourth resistor.
3. The reference comparator circuit of claim 2 wherein the current conversion module comprises a set of transistors configured to convert the second voltage into corresponding first and second currents.
4. The reference comparator circuit of claim 3, wherein the transistor group comprises a first transistor, a second transistor, a first resistor, and a second resistor;
the base electrode of the first triode is connected with the base electrode of the second triode, and is simultaneously connected with the middle node of the third resistor and the fourth resistor, the emitting electrode of the first triode is connected with the middle node of the first resistor and the second resistor, and the collecting electrode of the first triode is connected with the current mirror module;
an emitter of the second triode is connected with one end, far away from the second resistor, of the first resistor;
one end of the second resistor, which is far away from the first resistor, is connected with one end of the fourth resistor, which is far away from the third resistor;
the current conversion module obtains the first current according to the first triode and the second voltage, and obtains the second current according to the second triode and the second voltage.
5. The reference comparator circuit of claim 3, wherein the transistor group comprises a first N-type mos transistor, a second N-type mos transistor, a first resistor, and a second resistor;
the grid electrode of the first N-type mos tube is connected with the grid electrode of the second N-type mos tube, and is simultaneously connected with the middle node of the third resistor and the middle node of the fourth resistor, the source electrode of the first N-type mos tube is connected with the middle node of the first resistor and the second resistor, and the drain electrode of the first N-type mos tube is connected with the current mirror module;
the source electrode of the second N-type mos tube is connected with one end, far away from the second resistor, of the first resistor;
one end of the second resistor, which is far away from the first resistor, is connected with one end of the fourth resistor, which is far away from the third resistor;
the current conversion module obtains the first current according to the first N-type mos tube and the second voltage, and obtains the second current according to the second N-type mos tube and the second voltage.
6. The reference comparator circuit of claim 5, wherein the second N-type mos transistor comprises a plurality of N-type mos transistors connected in parallel.
7. The reference comparator circuit as claimed in claim 5 or 6, wherein the second N-type mos transistor includes 10N-type mos transistors connected in parallel.
8. The reference comparator circuit of claim 4, wherein the current mirror block comprises a first P-type mos transistor and a second P-type mos transistor;
the grid electrode of the first P-type mos tube is connected with the grid electrode of the second P-type mos tube, the grid electrode of the first P-type mos tube is connected with the drain electrode of the first P-type mos tube, the source electrode of the first P-type mos tube is connected with a power supply, and the drain electrode of the first P-type mos tube is connected with the current conversion module;
the source electrode of the second P-type mos tube is connected with a power supply, and the drain electrode current conversion module of the second P-type mos tube is connected with the input end of the output module;
the current mirror module mirrors the first current according to the first P-type mos tube and the second P-type mos tube.
9. The reference comparator circuit of claim 8, wherein the first and second P-type mos transistors have a width-to-length ratio of 1: 1.
10. The reference comparator circuit as claimed in claim 8 or 9, wherein the output module comprises an amplifier for outputting a corresponding level value according to the output voltage;
one input end of the amplifier is connected with the source electrode of the second P-type mos tube, and the other input end of the amplifier is connected with the drain electrode of the second P-type mos tube and the middle node of the current conversion module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010189073.5A CN111061333B (en) | 2020-03-18 | 2020-03-18 | Reference comparison circuit |
| PCT/CN2020/132011 WO2021184823A1 (en) | 2020-03-18 | 2020-11-27 | Reference comparison circuit |
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| CN202010189073.5A CN111061333B (en) | 2020-03-18 | 2020-03-18 | Reference comparison circuit |
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| CN111061333A true CN111061333A (en) | 2020-04-24 |
| CN111061333B CN111061333B (en) | 2021-02-12 |
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| WO2021184823A1 (en) * | 2020-03-18 | 2021-09-23 | 南京华瑞微集成电路有限公司 | Reference comparison circuit |
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| CN114355027B (en) * | 2022-03-17 | 2022-06-14 | 深圳市芯卓微科技有限公司 | Detection circuit and chip |
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| CN202471841U (en) * | 2011-11-24 | 2012-10-03 | 苏州思瑞浦微电子科技有限公司 | Current source setting time detecting circuit |
| CN102609031A (en) * | 2012-03-09 | 2012-07-25 | 深圳创维－Rgb电子有限公司 | Highly integrated low-power reference source |
| CN102882482A (en) * | 2012-10-12 | 2013-01-16 | 西安三馀半导体有限公司 | Ultralow power consumption error amplifier |
| CN103888093A (en) * | 2014-04-17 | 2014-06-25 | 苏州坤信微电子科技有限公司 | Common-mode level reset circuit for differential signals |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021184823A1 (en) * | 2020-03-18 | 2021-09-23 | 南京华瑞微集成电路有限公司 | Reference comparison circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111061333B (en) | 2021-02-12 |
| WO2021184823A1 (en) | 2021-09-23 |
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