CN202471841U

CN202471841U - Current source setting time detecting circuit

Info

Publication number: CN202471841U
Application number: CN2011204739067U
Authority: CN
Inventors: 刘扬; 牟陟; 应峰; 何德军; 周之栩
Original assignee: 3PEAKIC (SUZHOU) MICROELECTRONICS Co Ltd
Current assignee: Scarlett Ruipu microelectronics technology (Suzhou) Co., Ltd.
Priority date: 2011-11-24
Filing date: 2011-11-24
Publication date: 2012-10-03
Anticipated expiration: 2021-11-24

Abstract

The utility model discloses a current source setting time detecting circuit mainly including a current comparator composed of current source P1 and current source P2 of PMOS, and a current mirror N1 and a current mirror N2 of NMOS. Corresponding common-drain terminals of the current sources and the current mirrors are connected together. The current mirror N1 and the current source N2 are in a common-source ground connection. The current source P1 and the current source P2 connect with bias voltage in common-gate manner. And a drain electrode of the current source P2 is a sensing electric level terminal. In order to guarantee that the sensing electric level skips to a high electric level, an adjusting current sub-circuit is provided with a PMOS tube Pad capable of adjusting IPad dynamically. According to the technical scheme provided by the utility model, the setting time of the current source in a power source electrifying stage can be measured through detecting the low-to-high electric level skip of the sensing electric level terminal, thereby providing a reference and an effective guarantee for the safe operation of a chip.

Description

Current source testing circuit Time Created

Technical field

The utility model relates to a kind of current source application circuit, relates in particular to a kind of stable testing circuit Time Created of power supply electrifying to current source that is used for.

Background technology

Current source is the confession source form that is widely used in the stable output of a kind of tool in the types of functionality circuit, needs just to reach stable one period Time Created at power supply electrifying stage current source.For the chip of harsh application, the electric current instability of this section Time Created possibly cause chip to be in the misoperation state, influences chip functions.Therefore, need testing circuit to judge the Time Created of current source, avoid chip influencing the risk of function during this period of time because of non-normal working.

Summary of the invention

In view of the defective that above-mentioned prior art exists, the purpose of the utility model is to propose a kind of current source testing circuit Time Created, makes chip realize the supervision that its current source is set up process, and the protection chip exempts to be in the misoperation state.

The technical solution of the utility model purpose is:

Current source testing circuit Time Created; It is characterized in that: said testing circuit main body is by the current mirror N1 of current source P1, P2 and the NMOS of PMOS, the current comparator that N2 forms; Wherein current source links to each other with the corresponding common drain terminal of current mirror; Current mirror N1, N2 common source ground connection, current source P1, P2 common gate connect bias voltage, and the drain electrode of current source P2 is the induced potential end.

Further, said testing circuit is used to provide the adjusting electric current I in current source P2 parallel connection one tunnel _Pad, regulate the current source P of induced potential end redirect _Ad, as regulating current branch.

Further, said adjusting current branch is provided with dynamic adjustments I _PadPMOS pipe P _Lim, said PMOS pipe P _LimWith the P that regulates in the current branch _AdBe in series.

Further, said adjusting current branch is provided with dynamic adjustments I _PadPMOS pipe P _Lim, said PMOS pipe P _LimWith the P that regulates in the current branch _AdConstitute the source negative feedback structure.

The application of the utility model technical scheme through detecting low, the high level redirect of induced potential end, can measure current source in the Time Created in power supply electrifying stage, for the chip normal operation reference frame and effective guarantee is provided.

Description of drawings

Fig. 1 is the connection synoptic diagram of the utility model current source;

Fig. 2 a and Fig. 2 b are the power on electrology characteristic synoptic diagram in stage of this current source;

Fig. 3 is the utility model current source testing circuit basic structure synoptic diagram of Time Created;

Fig. 4 is the structural representation of the utility model current source testing circuit Time Created one preferred embodiment;

Fig. 5 is that the utility model is further optimized embodiment one synoptic diagram that current branch is regulated in bypass;

Fig. 6 is that the utility model is further optimized embodiment two synoptic diagram that current branch is regulated in bypass.

Embodiment

To set up the unstable state output state in the process in order protecting chip to avoid better to be operated in its current source, its current source can be detectedly exactly to be obtained Time Created.The utility model innovation has proposed a kind of current source testing circuit of Time Created.Extremely shown in Figure 3 like Fig. 1; It is thus clear that be well understood to the major technique characteristic of this testing circuit; Its main body is by the current mirror N1 of current source P1, P2 and the NMOS of PMOS, the current comparator that N2 forms, and wherein current source links to each other current mirror N1, N2 common source ground connection with the corresponding common drain terminal of current mirror; Current source P1, P2 common gate connect bias voltage, and the drain electrode of current source P2 is induced potential end (illustrated SENSE).

As depicted in figs. 1 and 2, power supply just powers on the stage, and current source PMOS pipe P1 and P2 are in sub-threshold region, and at this moment P1 and P2 size are more or less the same, i.e. I _P1≈ I _P2, being higher than the PMOS threshold voltage up to supply voltage, P1 and P2 get into the saturation region, and electric current is just with V _BiasTwo powers relation doubly becomes big, and is final stable to I _P1=2 * I _P2

As shown in Figure 3, in the stage of powering on, carry out current transformation through a pair of NMOS current mirror N1 and N2, the N2 electric current should be I _N2=2 * I _N1=2 * I _P1, but if load is P2, I _N2Can be by I _P2Restriction gets into linear zone, and this moment, the voltage of induced potential end was low level.When electric current is set up basically, I _P1≈ 2 * I _P2, with I _N2Close, this moment, the voltage of induced potential end will redirect be high level, judged current source foundation completion.

In order to guarantee that the effective redirect of induced potential end is a high level, the utility model is at current source P2 parallel connection one road current source P _Ad,, be used for producing the adjusting electric current I as regulating current branch _Pad, regulate the redirect of induced potential end, as shown in Figure 4.But the electric current I that this adjusting current branch is produced _PadIf too conference reduces accuracy of detection, too Gao Zehui can't draw high SENSE under certain conditions, causes circuit malfunction.Therefore need further improve above-mentioned adjusting current branch, feasible method is more, below only lifts two examples and explains.

As shown in Figure 5, because fixing little electric current is bigger to the accuracy of detection influence, therefore increase PMOS pipe P _Lim, dynamic adjustments I _PadThis PMOS pipe P _LimWith the P that regulates in the current branch _AdBe in series, in case the induced potential terminal voltage uprises P _LimConducting resistance just increase, with P _AdBe depressed into linear zone, reduced I _Pad, improved accuracy of detection.

Again please be as shown in Figure 6, because fixing little electric current is bigger to the accuracy of detection influence, therefore increase PMOS pipe P _Lim, with P _AdConstitute the source class negative feedback structure, dynamic adjustments I _PadIn case the induced potential terminal voltage uprises, P _LimConducting resistance increase, also can be with P _AdBe depressed into linear zone, reduce I _Pad, improved accuracy of detection.

In sum; Use current source testing circuit Time Created of the utility model; Through detecting low, the high level redirect of induced potential end, can measure current source in the Time Created in power supply electrifying stage, for the chip safe operation reference frame and effective guarantee be provided.

Claims

1. current source testing circuit Time Created; It is characterized in that: said testing circuit main body is by the current mirror N1 of current source P1, P2 and the NMOS of PMOS, the current comparator that N2 forms; Wherein current source links to each other with the corresponding common drain terminal of current mirror; Current mirror N1, N2 common source ground connection, current source P1, P2 common gate connect bias voltage, and the drain electrode of current source P2 is the induced potential end.

2. current source testing circuit Time Created as claimed in claim 1 is characterized in that: said testing circuit is used to provide the adjusting electric current I in current source P2 parallel connection one tunnel _Pad, regulate the current source P of induced potential end redirect _Ad, as regulating current branch.

3. current source testing circuit Time Created as claimed in claim 2 is characterized in that: said adjusting current branch is provided with dynamic adjustments I _PadPMOS pipe P _Lim, said PMOS pipe P _LimWith the P that regulates in the current branch _AdBe in series.

4. current source testing circuit Time Created as claimed in claim 2 is characterized in that: said adjusting current branch is provided with dynamic adjustments I _PadPMOS pipe P _Lim, said PMOS pipe P _LimWith the P that regulates in the current branch _AdConstitute the source negative feedback structure.