CN212321726U - Chip resistance detection device and chip device - Google Patents
Chip resistance detection device and chip device Download PDFInfo
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- CN212321726U CN212321726U CN202020668070.5U CN202020668070U CN212321726U CN 212321726 U CN212321726 U CN 212321726U CN 202020668070 U CN202020668070 U CN 202020668070U CN 212321726 U CN212321726 U CN 212321726U
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Abstract
The utility model relates to a chip resistance detection device and chip device, the device include that electric current produces circuit, voltage comparison circuit and output conversion circuit: the current generating circuit is used for connecting an external resistor and generating reference current; the reference current is the ratio of the band gap reference voltage of the tested chip device to the resistance value of the external resistor. The current input end of the voltage comparison circuit is connected with the current output end of the current generation circuit and is used for generating a test voltage corresponding to the reference current and outputting a comparison result of the test voltage and the band-gap reference voltage. The input end of the output conversion circuit is connected with the output end of the voltage comparison circuit and is used for converting the comparison result into a digital signal and outputting the digital signal to the digital circuit of the chip device. Through the design of the current generating circuit, the voltage comparison circuit and the output conversion circuit, the internal resistance detection process generates reference current through the external resistor, and a reference clock and a register circuit in a chip device are not required to be introduced in the detection process, so that the purpose of greatly reducing the detection power consumption is achieved.
Description
Technical Field
The utility model relates to a resistance detection technical field especially relates to a chip resistance detection device and chip device.
Background
The resistance detection technology is often applied to detecting actual resistance values of resistors on various chip devices, such as but not limited to ADC (Analog-to-digital converter) and PLL (Phase Locked Loop). Due to the limitations of the chip production process and the influence of temperature, the precision of passive components such as resistors on the chip is low, for example, the actual resistance value of the resistor usually varies by 20% or more from its nominal value. Therefore, the designer cannot accurately know the actual resistance value of the resistor in the chip to make the actual resistance value equal to the nominal value, thereby ensuring the performance of the circuit on the chip.
In order to obtain the actual resistance value of the resistor in the chip, the conventional resistor detection technology is to design a special resistor detection device, and test the internal resistor of the chip by using a reference resistor and introducing a chip internal reference clock and a register circuit. However, in implementing the utility model, the inventors found out. The conventional resistance detection technology at least has the problem of large detection power consumption.
SUMMERY OF THE UTILITY MODEL
Accordingly, there is a need for a chip resistance detection device that can significantly reduce detection power consumption.
In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:
the embodiment of the utility model provides a chip resistance detection device, include:
the current generating circuit is used for connecting an external resistor and generating reference current; the reference current is the ratio of the band gap reference voltage of the tested chip device to the resistance value of the external resistor;
the current input end of the voltage comparison circuit is connected with the current output end of the current generation circuit and is used for generating a test voltage corresponding to the reference current and outputting a comparison result of the test voltage and the band gap reference voltage;
and the input end of the output conversion circuit is connected with the output end of the voltage comparison circuit and is used for converting the comparison result into a digital signal and outputting the digital signal to the digital circuit of the chip device.
In one embodiment, the voltage comparison circuit comprises a resistance network unit and a comparator;
the input end of the resistance network unit is respectively connected with the current output end of the current generating circuit and the positive phase input end of the comparator, the output end of the resistance network unit is grounded, the negative phase input end of the comparator is used for being connected with the band gap reference voltage, and the output end of the comparator is connected with the input end of the output conversion circuit.
In one embodiment, the resistance network unit comprises a first resistance network and a first switch group; the first resistor network comprises N resistors R0 which are sequentially connected in series, the first switch group comprises N gating switches K1 which are in one-to-one correspondence with the resistors R0, and N is a positive integer greater than or equal to 2;
the input end of the first resistance network is respectively connected with the current output end of the current generating circuit and the positive phase input end of the comparator, and the output end of the first resistance network is grounded;
one end of each gating switch K1 is connected to the input end of the first resistor network, and the other end of each gating switch K1 is connected to the output end of the corresponding resistor R0.
In one embodiment, the resistor network unit further comprises a second resistor network and a second switch group; the second resistor network comprises M sequentially connected sub-networks in series, each sub-network comprises a plurality of resistors R1 connected in parallel, the second switch group comprises M gating switches K2 corresponding to the sub-networks one by one, and M is a positive integer greater than or equal to 1;
the input end of the second resistor network is connected with the output end of the first resistor network, the output end of the second resistor network is grounded, and each gating switch K2 is respectively connected with the resistor R1 of the corresponding sub-network in parallel.
In one embodiment, the resistor network unit further comprises a ground resistor R2, and the output terminal of the second resistor network is grounded through a ground resistor R2; the number of resistors R1 connected in parallel in each sub-network is different; the gating switch K1 is a field effect transistor or a switching triode, and the gating switch K2 is a field effect transistor or a switching triode.
In one embodiment, the current generation circuit comprises an operational amplifier, a current mirror MP0, a current mirror MP2, a current mirror MP1, a current mirror MP3 and an ESD protection circuit;
the inverting input end of the operational amplifier is used for accessing a band gap reference voltage, and the output end of the operational amplifier is respectively connected with the gates of the current mirror MP0 and the current mirror MP 2;
the sources of the current mirror MP0 and the current mirror MP2 are respectively used for connecting a power supply source, the drain of the current mirror MP0 is connected with the source of the current mirror MP1, and the drain of the current mirror MP2 is connected with the source of the current mirror MP 3;
the gates of the current mirror MP1 and the current mirror MP3 are respectively connected with the positive phase input end of the operational amplifier, the drain of the current mirror MP1 is used for connecting an external resistor, and the drain of the current mirror MP3 is connected with the current input end of the voltage comparison circuit;
the ESD protection circuit is connected in parallel between the gate and the drain of the current mirror MP1, and is used for performing overvoltage protection on the current mirror MP 1.
In one embodiment, the ESD protection circuit comprises a protection resistor Rs and a secondary ESD protection tube Q; the secondary ESD protection tube Q is a diode or a field effect tube MN;
one end of the protective resistor Rs is connected with the gate of the current mirror MP1, and the other end of the protective resistor Rs is connected with the drain of the current mirror MP 1;
the negative end of the secondary ESD protection tube Q is connected with one end of the protection resistor Rs, and the positive end of the secondary ESD protection tube Q is grounded.
In one embodiment, the output conversion circuit comprises a current mirror MP4, a current mirror MP5, a current mirror MP6, a current mirror MN1, a current mirror MN2, and a current mirror MN 3;
the collectors of the current mirror MP4, the current mirror MP5 and the current mirror MP6 are respectively used for accessing digital-to-analog conversion reference voltage, the gates of the current mirror MP4 and the current mirror MN1 are connected to the output end of the voltage comparison circuit, and the drains of the current mirror MP6 and the current mirror MN3 are connected to the digital circuit of the tested chip;
the drains of the current mirror MP4 and the current mirror MN1 are connected to the gates of the current mirror MP5 and the current mirror MN2, respectively, and the drains of the current mirror MP5 and the current mirror MN2 are connected to the gates of the current mirror MP6 and the current mirror MN3, respectively;
the sources of current mirror MN1, current mirror MN2, and current mirror MN3 are all connected to ground.
In one embodiment, the output conversion circuit further comprises a current mirror MN 4;
the source of the current mirror MN4 is connected with the gates of the current mirror MP4 and the current mirror MN1 respectively, the gate of the current mirror MN4 is connected with the output end of the voltage comparison circuit, and the drain of the current mirror MN4 is used for accessing a digital-to-analog conversion reference voltage.
On the other hand, a chip device is also provided, which comprises the chip resistance detection device.
One of the above technical solutions has the following advantages and beneficial effects:
according to the chip resistance detection device and the chip device, through the design of the current generation circuit, the voltage comparison circuit and the output conversion circuit, the reference current generated when the current generation circuit is externally connected with the resistor eliminates the error influence caused by parasitic resistance; the reference current is input into the voltage comparison circuit to generate corresponding test voltage, the voltage comparison circuit compares the test voltage with the band gap reference voltage of the tested chip device, and the output comparison result is digitally converted by the output conversion circuit and then output to the digital circuit of the chip device, so that the digital circuit can output the actual resistance value of the internal resistor of the chip device according to the digital signal corresponding to the comparison result. Therefore, the required reference current can be directly generated through the external resistor in the detection process of the internal resistor, the reference current does not need to be generated by relying on band-gap reference voltage inside the chip device, the reference current is high in precision, and a reference clock and a register circuit inside the chip device are not introduced, so that the detection cost and the detection power consumption can be reduced to the greatest extent, and the purpose of greatly reducing the detection power consumption is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a chip resistance detection apparatus according to an embodiment;
FIG. 2 is a schematic diagram of a chip resistance detection apparatus according to another embodiment;
FIG. 3 is a schematic diagram of an embodiment of a voltage comparison circuit;
FIG. 4 is a schematic diagram of a voltage comparison circuit according to another embodiment;
FIG. 5 is a schematic diagram of an embodiment of a current generation circuit;
FIG. 6 is a schematic diagram of a current generation circuit according to another embodiment;
FIG. 7 is a schematic diagram of an embodiment of an output conversion circuit;
fig. 8 is a schematic structural diagram of an output conversion circuit in another embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.
It is to be understood that "connection" in the following embodiments is to be understood as "connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
As shown in fig. 1, in one embodiment, a chip resistance detection apparatus 100 is provided, which includes a current generation circuit 12, a voltage comparison circuit 14, and an output conversion circuit 16. The current generating circuit 12 is used for connecting an external resistor and generating a reference current; the reference current is the ratio of the band gap reference voltage of the tested chip device to the resistance value of the external resistor. The current input terminal of the voltage comparison circuit 14 is connected to the current output terminal of the current generation circuit 12, and is configured to generate a test voltage corresponding to the reference current, and output a comparison result between the test voltage and the bandgap reference voltage. The input end of the output conversion circuit 16 is connected to the output end of the voltage comparison circuit 14, and is used for converting the comparison result into a digital signal and outputting the digital signal to the digital circuit of the chip device.
It can be understood that the external resistor is an external resistor for detecting the internal resistance of the chip device, and the external resistor with corresponding resistance can be selected according to the nominal resistance of the internal resistors of different chip devices. The access mode of the external resistor can be similar to that of the traditional resistor detection device and method. The voltage at the two ends of the external resistor is kept consistent with the band gap reference voltage inside the chip device, and the current generating circuit 12 is used for generating reference current on the external resistor according to ohm's law when being connected to the external resistor.
The bias current generating circuit 12 in the conventional resistance detecting apparatus and method has a non-inverting input terminal of an operational amplifier in the circuit directly connected to a drain of a current mirror. Since a metal connecting line is arranged between the connecting point and a Pin (PAD) of the chip device, when the metal connecting line is long, the magnitude of the parasitic resistor Rp generated by the metal connecting line can reach the ohm magnitude, so that the reference current generated by the conventional bias current generating circuit 12 is actually the band gap reference voltage VREF divided by the sum of the resistance of the parasitic resistor and the resistance of the external resistor, and thus, the generated reference current has an error. When the resistance value of the external resistor is smaller, the error is more obvious, and the error of detecting the resistance value of the internal resistor of the chip device is larger. The access mode of the external resistor in the application can be consistent with that of the traditional resistor detection device and method.
In the present application, the influence of the parasitic resistance is considered in the designed current generating circuit 12, so as to ensure that the generated reference current is the ratio of the band gap reference voltage of the tested chip device to the resistance value of the external resistor, and avoid the influence of the parasitic resistance. For example, through circuit design, a positive phase input terminal of an operational amplifier in a circuit and a current mirror are directly connected on a PAD head of a chip device, so that the generated reference current is the ratio of a bandgap reference voltage VREF to the resistance value of an external resistor, and does not contain the components of a parasitic resistor.
The reference voltage applied to the current generation circuit 12 is equal to the bandgap reference voltage inside the chip device, and can be directly provided by an external voltage source. The bandgap reference voltage connected to the voltage comparison circuit 14 is a bandgap reference voltage inside the chip device, and can be directly connected to the chip device. The digital circuit of the chip device is a controller circuit of the chip device, and assumes the functions of a processor such as calculation, control, input and output of the chip device, and the digital circuits of different types of chip devices have different functions, which are not specifically limited in this specification.
Specifically, when the internal resistance of the chip device needs to be detected, an external resistor is connected to the current generating circuit 12 to generate a set of reference current from the outside of the chip device without depending on the bandgap reference voltage inside the chip device. After the reference current is input into the voltage comparison circuit 14, a corresponding voltage drop, i.e., a test voltage, is generated across a resistor inside the voltage comparison circuit 14. The test voltage is compared with the bandgap reference voltage inside the chip device by the voltage comparison circuit 14, and the comparison result is output in the form of an analog electrical signal. The analog electrical signal is converted into a corresponding digital signal by the output conversion circuit 16 and then sent to the digital circuit of the chip device, and the digital circuit of the chip device can judge the actual resistance value of the internal resistor of the chip device from the digital signal and determine the difference between the actual resistance value of the internal resistor of the chip device and the nominal value thereof. Meanwhile, because the signal of the output conversion circuit 16 is converted and output, the influence of a post-stage circuit on a front-stage circuit can be prevented, and a good signal isolation effect can be achieved.
The voltage comparator 14 may have a constant resistance or a variable resistance. When an external resistor with a certain resistance value is connected, the internal resistor resistance value of the voltage comparison circuit 14 can be adjusted, so that the voltage comparison circuit 14 correspondingly outputs different comparison results until the output comparison result corresponds to that the test voltage is equal to the band gap reference voltage inside the chip device, and the digital circuit of the chip device can correspondingly detect the actual resistance value of the internal resistor of the chip device. Correspondingly, the internal resistance value of the fixed voltage comparison circuit 14 can be selected, and by replacing external resistors with different resistance values, the voltage comparison circuit 14 can correspondingly output different comparison results until the output comparison result corresponds to that the test voltage is equal to the band gap reference voltage inside the chip device, and the digital circuit of the chip device can correspondingly detect the actual resistance value of the internal resistor of the chip device. Therefore, the former detection mode can quickly obtain the deviation between the actual resistance value of the internal resistor of the chip device and the nominal value thereof, and the latter detection mode can also screen the external resistor in reverse, so that the chip resistor detection device 100 utilizes the principle that the external resistor generates the corresponding reference current, synchronously generates the current bias required by the device, and has the function of resistor selection. In the detection process, the precision of externally generated reference current is guaranteed, an internal reference clock and a register circuit of a chip device are not introduced, and the effects of low cost and low power consumption of detection are achieved.
According to the chip resistance detection device 100, through the design of the current generation circuit 12, the voltage comparison circuit 14 and the output conversion circuit 16, the reference current generated when the current generation circuit 12 is externally connected with a resistor eliminates the error influence caused by parasitic resistance; the reference current is input into the voltage comparison circuit 14 to generate a corresponding test voltage, the voltage comparison circuit 14 compares the test voltage with the bandgap reference voltage of the chip device to be tested, and the output comparison result is digitally converted by the output conversion circuit 16 and then output to the digital circuit of the chip device, so that the digital circuit can output the actual resistance value of the internal resistor of the chip device according to the digital signal corresponding to the comparison result. Therefore, the required reference current can be directly generated through the external resistor in the detection process of the internal resistor, the reference current does not need to be generated by relying on band-gap reference voltage inside the chip device, the reference current is high in precision, and a reference clock and a register circuit inside the chip device are not introduced, so that the detection cost and the detection power consumption can be reduced to the greatest extent, and the purpose of greatly reducing the detection power consumption is achieved.
As shown in FIG. 2, in one embodiment, the voltage comparison circuit 14 includes a resistor network unit 142 and a comparator 144. The input terminal of the resistor network unit 142 is connected to the current output terminal of the current generating circuit 12 and the non-inverting input terminal of the comparator 144, and the output terminal of the resistor network unit 142 is grounded. The inverting input terminal of the comparator 144 is used for accessing the bandgap reference voltage, and the output terminal of the comparator 144 is connected to the input terminal of the output conversion circuit 16.
It can be understood that the voltage comparison circuit 14 includes two circuit components, wherein the resistor network unit 142 is a resistor network formed by connecting a plurality of resistors in series and/or in parallel, and the resistor network unit 142 is configured to generate a corresponding voltage drop after accessing the reference current generated by the current generation circuit 12, that is, generate a corresponding test voltage to be applied to the non-inverting input terminal of the comparator 144. The resistance value of the resistor connected to the resistor network unit 142 may be fixed, or may be adjustable in multiple steps, and the total resistance value (or the maximum resistance value) of the resistor network unit 142 may be determined according to the actual resistance value prediction condition of the internal resistor having the chip device to be tested, as long as the requirement for detecting the internal resistance value of the chip device can be met.
The comparator 144 is a voltage comparator cmp (comparator), which may be any type of voltage comparator 144 in the art, and may be specifically selected according to the internal resistance value detection requirement of the foot chip device and/or the design specification (such as cost and volume) of the chip resistance detection apparatus 100.
Specifically, the reference current generated by the current generating circuit 12 passes through the resistor network unit 142 to generate a corresponding voltage drop, which is a test voltage input to the non-inverting input terminal of the comparator 144, and the voltage drop is compared with the bandgap reference voltage at the inverting input terminal of the comparator 144. When the test voltage is equal to the bandgap reference voltage, the output of the comparator 144 will generate a comparison result of the inverted output pair, and the comparison result is subjected to level conversion by the output conversion circuit 16 and then sent to the digital circuit of the chip device for processing, so as to determine the deviation between the actual resistance value of the internal resistor of the chip device and the nominal value thereof.
By adopting the resistor network unit 142 and the comparator 144, and the current generation circuit 12 and the output conversion circuit 16 work in coordination, the comparison output of the test voltage and the band gap reference voltage inside the chip device can be realized to obtain the accurate resistance value of the internal resistor of the chip device, without introducing an internal reference clock and a register circuit of the chip device, the circuit structure is simple, and the detection power consumption is effectively reduced greatly.
As shown in fig. 3, in one embodiment, the resistor network unit 142 includes a first resistor network 1422 and a first switch set 1424. The first resistor network 1422 includes N resistors R0 connected in series in sequence, and the first switch group 1424 includes N gate switches K1 corresponding to the resistors R0 one to one; wherein N is a positive integer greater than or equal to 2. The input terminal of the first resistor network 1422 is connected to the current output terminal of the current generating circuit 12 and the non-inverting input terminal of the comparator 144, and the output terminal of the first resistor network 1422 is grounded. One end of each gate switch K1 is connected to the input end of the first resistor network 1422, and the other end of each gate switch K1 is connected to the output end of the corresponding resistor R0.
It should be noted that fig. 3 is a circuit example of only one first resistor network 1422 structure, the number of resistors R0 connected in series in practical application may be two, or may be three or more, and the number of resistors R0 connected in series may be determined according to the internal resistance value detection requirement of the chip device. The gate switch K1 may be a mechanical switch operated manually or an electrical control switch, and is used to respectively implement access and short circuit control of each corresponding resistor R0, so as to change the total access resistance of the first resistor network 1422 and implement adjustment of the test voltage.
Specifically, by gating the different gating switches K1 after the input of the reference current IB, different test voltages can be generated and applied to the non-inverting input of the comparator 144 for comparison with the bandgap reference voltage at the inverting input of the comparator 144. When the test voltage and the bandgap reference voltage are equal, the comparator 144 generates a flip-flop to output a corresponding comparison result (output signal). The actual resistance value deviation between the external resistor and the internal resistor of the chip device can be obtained through the total resistance value of the resistor R0 accessed through the gating switch K1. At this time, the internal resistance of the chip device can be accurately reflected by the comparison result corresponding to the actual resistance value accessed by the gate switch K1 on the external resistor and the first resistor network 1422.
By adopting the design that the first resistor network 1422 and the first switch group 1424 form the voltage comparison circuit 14 with adjustable resistance, accurate detection of the internal resistance of the chip device can be effectively realized, the detection adaptability is strong, and detection of the chip devices with different internal resistance sizes and selection of the external resistors with different resistance sizes can be supported.
As shown in fig. 4, in one embodiment, the resistor network unit 142 further includes a second resistor network 1426 and a second switch set 1428. The second resistor network 1426 includes M sequentially connected sub-networks, each of which includes a number of resistors R1 connected in parallel. The second switch group 1428 includes M gate switches K2 in one-to-one correspondence with the sub-networks, where M is a positive integer greater than or equal to 1. The input terminal of the second resistor network 1426 is connected to the output terminal of the first resistor network 1422, and the output terminal of the second resistor network 1426 is grounded. Each gate switch K2 is connected in parallel with the resistor R1 of the corresponding sub-network.
It can be understood that, in the present embodiment, the resistor R1 may be the same as the resistor R0 (resistance and/or type) used in the first resistor network 1422 (chip layout is more efficient), or may be different from the resistor R0; the resistors R1 may have the same resistance value or different resistance values. The number of the resistors R1 connected in parallel in each sub-network may be the same or different, and the specific number of the resistors R1 connected in parallel in each sub-network may be determined according to the internal resistance detection requirement of the chip device, as long as the test voltage is equal to the bandgap reference voltage of the chip device to be detected, so as to obtain the accurate resistance of the internal resistor of the chip device. It should be noted that fig. 4 is only a circuit example of one of the structures of the first resistor network 1422 and the second resistor network 1426, and is not a unique circuit structure design, and those skilled in the art can perform appropriate device expansion or reduction under the guidance of the design spirit of the present application to meet the detection requirement of chip devices with different internal resistor values.
The gate switch K2 may be a mechanical switch operated manually or an electrical control switch, and is used to respectively implement access and short circuit control of each corresponding sub-network, so as to change the total access resistance value of the second resistor network 1426, and implement adjustment of the test voltage by matching with the first resistor network 1422.
Specifically, in this embodiment, the first resistor network 1422 and the first switch group 1424 may be used as a coarse adjustment part, and the second resistor network 1426 and the second switch group 1428 may be used as a fine adjustment part. During testing, the actual resistance range of the internal resistor of the chip device can be preliminarily determined from the output upset condition of the comparator 144 by first gating each gating switch K1. When the total resistance value of the first resistor network 1422 corresponding to a certain gating switch K1 is the minimum deviation value between the resistance value of the external resistor and the actual resistance value of the internal resistor of the chip device, further trying to gate each gating switch K2 for fine tuning respectively until the test voltage on the comparator 144 is equal to the band gap reference voltage to generate output inversion; at this time, the total resistance values of the two resistor networks corresponding to the gated gating switch K1 and the gating switch K2 accurately reflect the actual resistance value deviation between the external resistor and the internal resistor of the chip device, the corresponding comparison result is sent to the digital circuit of the chip device through level conversion, and the digital circuit can acquire the actual resistance value of the internal resistor of the chip device during current detection.
By adopting the multi-stage design structure of the first resistor network 1422 and the first switch group 1424, and the second resistor network 1426 and the second switch group 1428, more accurate detection of the internal resistor of the chip device can be realized, and the method can be more suitable for actual resistance change detection of the internal resistor of the chip device in different use periods; when the total resistance values of the two resistance networks are fixed, the external resistors with different resistance values can be accurately selected in turn.
As shown in fig. 4, in one embodiment, the resistor network element 142 further includes a ground resistor R2. The output of the second resistor network 1426 is coupled to ground through a ground resistor R2. The number of resistors R1 connected in parallel in each sub-network is different.
It can be understood that the value of the ground resistor R2 is larger than that of the resistor R0, but not limited to, the value of the ground resistor R2 is usually 12 times that of the resistor R0, so that reliable and safe grounding of the whole circuit can be realized. It will be understood by those skilled in the art that the ground resistor may also be configured in the form of a resistor network, for example, a plurality of resistors may be connected in series and/or in parallel to form a ground resistor network, which may be determined according to the grounding reliability requirement of the voltage comparison circuit 14, as long as the required grounding protection can be effectively provided. By setting the grounding resistor R2, the reliability and safety of the whole voltage comparison circuit 14 can be greatly improved, thereby achieving the effect of better improving the reliability of the whole chip resistance detection device 100.
In one embodiment, the resistance R0 may be a 20K Ω resistor, and the resistance R1 may be the same as the resistance R0. It is understood that, in the above embodiment, the resistance value R0 is, for example, a resistor of 20K Ω or another resistance value, as long as the effect of quickly detecting the resistance value of the internal resistor can be achieved. In this embodiment, the resistors in the two resistor networks are both resistors R0 with the same resistance, so that the circuit design and manufacture are more efficient.
In one embodiment, as shown in fig. 4, the gate switch K1 is a fet or a switching transistor. The gating switch K2 is a field effect transistor or a switching triode.
It is understood that in the present embodiment, the gate switch K1 and the gate switch K2 may be the same kind of electrically controlled switches, for example, both may be fets, or both may be switching transistors. Fig. 4 shows an example of the application when field effect transistors are used as the gate switches K1 and K2. The gates (or bases) of the switching devices can be used for respectively accessing the control level (such as 0 or 1) provided by the external register to realize gating or turning-off control, so as to realize the resistance value adjustment of the resistance network unit 142. The circuit shown in fig. 4 is exemplified by a field effect transistor.
By applying the field effect transistor or the switching triode, the resistance value of the resistance network unit 142 can be conveniently regulated, the response speed of detection operation is improved, and the detection efficiency is improved.
As shown in fig. 5, in one embodiment, the current generation circuit 12 includes an operational amplifier, a current mirror MP0, a current mirror MP2, a current mirror MP1, a current mirror MP3, and an ESD protection circuit. The inverting input end of the operational amplifier is used for connecting a band gap reference voltage, and the output end of the operational amplifier is respectively connected with the gates of the current mirror MP0 and the current mirror MP 2. The sources of the current mirror MP0 and the current mirror MP2 are respectively used for connecting a power supply, the drain of the current mirror MP0 is connected to the source of the current mirror MP1, and the drain of the current mirror MP2 is connected to the source of the current mirror MP 3. The gates of the current mirror MP1 and the current mirror MP3 are respectively connected to the non-inverting input terminal of the operational amplifier. The drain of the current mirror MP1 is used to switch in an external resistor. The drain of the current mirror MP3 is connected to the current input of the voltage comparison circuit 14. The ESD protection circuit is connected in parallel between the gate and the drain of the current mirror MP1, and is used for performing overvoltage protection on the current mirror MP 1.
The inverting input terminal of the operational amplifier (i.e. AMP) is used for accessing a reference voltage VREF, which can be provided by an external voltage source and has a size consistent with a bandgap reference voltage inside the chip device. The ESD protection circuit may be any type of ESD protection circuit commonly used in the art, and may be specifically selected according to the operating environment of the current mirror MP1, as long as it can provide the required effective protection to prevent the current mirror MP1 from breaking down.
It can be understood that the positive phase input terminal of the operational amplifier and the current mirror MP0 are directly connected to the PAD of the chip device, so that the parasitic resistance of the connection line between the current mirror MP0 and the PAD is negligible, thereby ensuring that the generated reference current is not affected by the error caused by the parasitic resistance, and ensuring the accuracy of detecting the resistance value of the internal resistance of the chip device. The power supply source is VDD, and may be a device power source on the circuit substrate where the chip resistance detection apparatus 100 is located, or a device power source led from a chip device to be detected, and the specific voltage magnitude thereof may be determined according to the operation requirement of each device.
Specifically, when the internal resistance of the chip device needs to be detected, the external resistor (i.e., the resistor Rext) is connected to the current generating circuit 12, and the operational amplifier controls each current mirror to generate the required high-precision reference current IB. The reference current IB is sent from the drain of the current mirror MP3 to the voltage comparison circuit 14 for processing. Through the above current generating circuit 12, the generation of the high-precision reference current can be realized by accessing the external resistor, and the selection of different external resistors can be realized by replacing the external resistors with different resistance values by using the chip resistor detecting device 100.
As shown in fig. 6, in one embodiment, the ESD protection circuit includes a protection resistor Rs and a secondary ESD protection tube Q. One end of the protection resistor Rs is connected to the gate of the current mirror MP1, and the other end of the protection resistor Rs is connected to the drain of the current mirror MP 1. The negative end of the secondary ESD protection tube Q is connected with one end of the protection resistor Rs, and the positive end of the secondary ESD protection tube Q is grounded.
It can be understood that, in the present embodiment, a specific ESD protection circuit is provided, wherein the secondary ESD protection tube Q may be various types of semiconductor tubes in the art with a unidirectional conduction function, and the protection resistor Rs and the secondary ESD protection tube Q together form a two-stage ESD protection circuit. It will be understood by those skilled in the art that the other end of the protection resistor Rs is connected to the drain of the current mirror MP1 indirectly, i.e., indirectly connected to the drain of the current mirror MP1 through the PAD pin of the chip device. The specific type and electrical parameters of the protection resistor Rs and the secondary ESD protection tube Q can be determined according to the requirements of the working environment of each device in the current generation circuit 12.
Specifically, when the current generating circuit 12 is in operation, if the voltage between the gate and the drain of the current mirror MP1 is too high, the dual voltage discharge can be directly performed through the protection resistor Rs and the secondary ESD protection tube Q, so as to prevent the current mirror MP1 from breaking down. Through the above two-stage protection circuit design, the device protection function of the current generation circuit 12 can be more reliably realized, thereby further improving the reliability of the chip resistance detection apparatus 100.
As shown in fig. 6, in one embodiment, the secondary ESD protection tube Q is a diode or a field effect transistor MN. The drain of the field effect transistor MN is connected with one end of the protection resistor Rs, and the grid and the source of the field effect transistor MN are connected and grounded.
Optionally, in this embodiment, a diode may be directly used as the required secondary ESD protection tube Q, a cathode of the diode is connected to one end of the protection resistor Rs, and a cathode of the diode is grounded. Alternatively, the field effect transistor MN may be used as the required secondary ESD protection tube Q, and those skilled in the art can understand that in the current generation circuit 12 shown in fig. 6, the field effect transistor MN with N channels is used as an application example, and in practical application, the field effect transistor with P channel may also be used and the wiring polarity may be adaptively adjusted.
By applying the second-stage ESD protection tube Q as the second-stage fet MN, the circuit protection effect is good, the reliability is high, and the cost is low, so that the device protection effect required by the current generation circuit 12 can be effectively achieved.
As shown in fig. 7, in one embodiment, output conversion circuit 16 includes current mirror MP4, current mirror MP5, current mirror MP6, current mirror MN1, current mirror MN2, and current mirror MN 3. The collectors of the current mirror MP4, the current mirror MP5 and the current mirror MP6 are respectively used for receiving a digital-to-analog conversion reference voltage. The gates of the current mirror MP4 and the current mirror MN1 are connected to the output terminal of the voltage comparison circuit 14. The drain electrodes of the current mirror MP6 and the current mirror MN3 are connected and used for connecting a digital circuit of the chip to be tested. The drains of current mirror MP4 and current mirror MN1 are connected, and are connected to the gates of current mirror MP5 and current mirror MN2, respectively. The drains of current mirror MP5 and current mirror MN2 are connected, and are connected to the gates of current mirror MP6 and current mirror MN3, respectively. The sources of current mirror MN1, current mirror MN2, and current mirror MN3 are all connected to ground.
The current mirror MP4 and the current mirror MN1 are high voltage tubes, and the current mirror MP5, the current mirror MP6, the current mirror MN2 and the current mirror MN3 are low voltage tubes, so that the reliable operation of the whole output conversion circuit 16 can be ensured, and the analog-to-digital conversion of the comparison result output by the voltage comparison circuit 14 can be realized. The Digital-to-analog conversion reference voltage is a voltage DVDD (i.e., Digital VDD, Digital power supply) shown in fig. 7, which may be directly obtained from a chip device to be tested, or may be provided by an external device power supply, and the specific voltage may be determined according to the working requirement of each current mirror.
By adopting the above-described structural design of the typical output conversion circuit 16, analog-to-digital conversion output of the comparison result can be efficiently realized, the circuit structure is simple and the cost is not high, and thus the production cost of the chip resistance detection apparatus 100 can be reduced and the circuit volume can be reduced.
As shown in fig. 8, in one embodiment, output conversion circuit 16 further includes a current mirror MN 4. The source of the current mirror MN4 is connected to the gates of the current mirror MP4 and the current mirror MN1, respectively, the gate of the current mirror MN4 is connected to the output terminal of the voltage comparison circuit 14, and the drain of the current mirror MN4 is used for accessing a digital-to-analog conversion reference voltage.
It can be understood that the gates of the current mirror MP4 and the current mirror MN1 may be indirectly connected to the output terminal of the voltage comparison circuit 14 through the current mirror MN4, and an initialization state may be provided when the whole chip detection apparatus 100 is just powered on and started through the addition of the current mirror MN4, so as to accelerate the circuit start-up speed of the apparatus, thereby achieving the purpose of further improving the chip resistance detection efficiency.
The chip resistance detection device 100 can be applied to chip devices such as an ADC chip or a PLL chip, the chip resistance detection device 100 can be integrated into the chip device for use, or can be packaged with a single integrated device as an independent detection device, and can be used for detecting internal resistance values of one or more types of chip devices, and a specific application setting mode can be flexibly selected according to requirements of application scenarios. It should be noted that the semiconductor devices shown in the drawings of the above embodiments are only schematic and not exclusive limitations, such as gate switches, current mirrors, ESD protection circuits, and the like. It will be appreciated by those skilled in the art that semiconductor devices may generally include both N-channel and P-channel types, and thus, devices employing either N-channel or P-channel may be selected as desired and may achieve equal or better results within the spirit of the present disclosure.
In one embodiment, the present application further provides a chip device, which includes the chip resistance detection apparatus 100 described above.
It is understood that the chip device in the present embodiment may be, but is not limited to, a chip device such as an ADC chip or a PLL chip, and the chip resistance detection apparatus 100 described above is integrated in the chip device. The explanation of the chip resistance detection apparatus 100 in this embodiment can be understood by referring to the explanations of the embodiments of the chip resistance detection apparatus 100 and the same process, and repeated descriptions are not repeated here.
By applying the chip resistance detection device 100, when the chip device detects the internal resistance, only the external resistor needs to be connected to generate the reference current which needs to depend on the reference clock and the band-gap reference voltage of the chip device, so that the error caused by the parasitic resistance is eliminated; the reference current is input into the voltage comparison circuit 14 of the chip resistance detection apparatus 100 to generate a corresponding test voltage, the voltage comparison circuit 14 compares the test voltage with the bandgap reference voltage of the chip device to be detected, and the output comparison result is digitally converted by the output conversion circuit 16 and then output to the digital circuit of the chip device, so that the digital circuit can output the actual resistance value of the internal resistance of the chip device according to the digital signal corresponding to the comparison result.
Therefore, the required reference current can be directly generated through the external resistor in the detection process of the internal resistor, the reference current does not need to be generated by relying on band gap reference voltage inside the chip device, the reference current is high in precision, a reference clock and a register circuit inside the chip device are not introduced, the detection cost and the detection power consumption can be reduced to the greatest extent, the purpose of greatly reducing the detection power consumption is achieved, and the stability and the reliability of the whole controller system where the chip device is located are greatly improved.
In the description herein, reference to the description of the terms "one of the embodiments," "another embodiment," "an embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A chip resistance detection device, comprising:
the current generating circuit is used for connecting an external resistor and generating reference current; the reference current is the ratio of the band gap reference voltage of the tested chip device to the resistance value of the external resistor;
the current input end of the voltage comparison circuit is connected with the current output end of the current generation circuit and is used for generating a test voltage corresponding to the reference current and outputting a comparison result of the test voltage and the band gap reference voltage;
and the input end of the output conversion circuit is connected with the output end of the voltage comparison circuit and is used for converting the comparison result into a digital signal and outputting the digital signal to the digital circuit of the chip device.
2. The chip resistance detection device according to claim 1, wherein the voltage comparison circuit comprises a resistance network unit and a comparator;
the input end of the resistance network unit is respectively connected with the current output end of the current generating circuit and the positive phase input end of the comparator, the output end of the resistance network unit is grounded, the negative phase input end of the comparator is used for being connected with the band gap reference voltage, and the output end of the comparator is connected with the input end of the output conversion circuit.
3. The chip resistance detection device according to claim 2, wherein the resistance network unit comprises a first resistance network and a first switch group; the first resistor network comprises N resistors R0 which are sequentially connected in series, the first switch group comprises N gating switches K1 which are in one-to-one correspondence with the resistors R0, and N is a positive integer greater than or equal to 2;
the input end of the first resistance network is respectively connected with the current output end of the current generating circuit and the positive phase input end of the comparator, and the output end of the first resistance network is grounded;
one end of each gating switch K1 is connected to the input end of the first resistor network, and the other end of each gating switch K1 is connected to the output end of the corresponding resistor R0.
4. The chip resistance detection device according to claim 3, wherein the resistance network unit further comprises a second resistance network and a second switch group; the second resistance network comprises M sub-networks which are sequentially connected in series, each sub-network comprises a plurality of resistors R1 connected in parallel, the second switch group comprises M gating switches K2 corresponding to the sub-networks in a one-to-one mode, and M is a positive integer greater than or equal to 1;
the input end of the second resistor network is connected with the output end of the first resistor network, the output end of the second resistor network is grounded, and each gating switch K2 is respectively connected with the resistor R1 of the corresponding sub-network in parallel.
5. The on-chip resistance detection device according to claim 4, wherein the resistance network unit further comprises a ground resistor R2, and the output terminal of the second resistance network is grounded through the ground resistor R2; the number of the resistors R1 connected in parallel in each sub network is different; the gating switch K1 is a field effect transistor or a switching triode, and the gating switch K2 is a field effect transistor or a switching triode.
6. The chip resistance detecting device according to any one of claims 1 to 5, wherein the current generating circuit comprises an operational amplifier, a current mirror MP0, a current mirror MP2, a current mirror MP1, a current mirror MP3 and an ESD protection circuit;
the inverting input end of the operational amplifier is used for being connected with the band-gap reference voltage, and the output end of the operational amplifier is respectively connected with the gates of the current mirror MP0 and the current mirror MP 2;
the sources of the current mirror MP0 and the current mirror MP2 are respectively used for connecting a power supply source, the drain of the current mirror MP0 is connected with the source of the current mirror MP1, and the drain of the current mirror MP2 is connected with the source of the current mirror MP 3;
the gates of the current mirror MP1 and the current mirror MP3 are respectively connected to the non-inverting input terminal of the operational amplifier, the drain of the current mirror MP1 is used for connecting the external resistor, and the drain of the current mirror MP3 is connected to the current input terminal of the voltage comparison circuit;
the ESD protection circuit is connected in parallel between the gate and the drain of the current mirror MP1 and is used for performing overvoltage protection on the current mirror MP 1.
7. The chip resistance detection device according to claim 6, wherein the ESD protection circuit comprises a protection resistor Rs and a secondary ESD protection tube Q; the secondary ESD protection tube is a diode or a field effect tube MN;
one end of the protection resistor Rs is connected with the gate of the current mirror MP1, and the other end of the protection resistor Rs is connected with the drain of the current mirror MP 1;
the negative end of the secondary ESD protection tube Q is connected with one end of the protection resistor Rs, and the positive end of the secondary ESD protection tube Q is grounded.
8. The chip resistance detection device according to claim 6, wherein the output conversion circuit comprises a current mirror MP4, a current mirror MP5, a current mirror MP6, a current mirror MN1, a current mirror MN2 and a current mirror MN 3;
the collectors of the current mirror MP4, the current mirror MP5 and the current mirror MP6 are respectively used for accessing a digital-to-analog conversion reference voltage, the gates of the current mirror MP4 and the current mirror MN1 are connected to the output end of the voltage comparison circuit, and the drains of the current mirror MP6 and the current mirror MN3 are connected to the digital circuit of the chip under test;
the drains of the current mirror MP4 and the current mirror MN1 are connected to the gates of the current mirror MP5 and the current mirror MN2, respectively, and the drains of the current mirror MP5 and the current mirror MN2 are connected to the gates of the current mirror MP6 and the current mirror MN3, respectively;
the sources of the current mirror MN1, the current mirror MN2, and the current mirror MN3 are all grounded.
9. The chip resistance detection device according to claim 8, wherein the output conversion circuit further comprises a current mirror MN 4;
the source electrode of the current mirror MN4 is respectively connected with the grid electrodes of the current mirror MP4 and the current mirror MN1, the grid electrode of the current mirror MN4 is connected with the output end of the voltage comparison circuit, and the drain electrode of the current mirror MN4 is used for accessing the digital-to-analog conversion reference voltage.
10. A chip device comprising the chip resistance detection apparatus according to any one of claims 1 to 9.
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| WO2023029440A1 (en) * | 2021-09-02 | 2023-03-09 | 深圳市中兴微电子技术有限公司 | Resistance value acquisition circuit, method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023029440A1 (en) * | 2021-09-02 | 2023-03-09 | 深圳市中兴微电子技术有限公司 | Resistance value acquisition circuit, method and device |
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