CN111009577A - Method for improving electric leakage of groove type metal oxide semiconductor grid source - Google Patents

Method for improving electric leakage of groove type metal oxide semiconductor grid source Download PDF

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CN111009577A
CN111009577A CN201911220369.2A CN201911220369A CN111009577A CN 111009577 A CN111009577 A CN 111009577A CN 201911220369 A CN201911220369 A CN 201911220369A CN 111009577 A CN111009577 A CN 111009577A
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oxide layer
layer
thickness
grid
type impurity
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张二雄
黄泽军
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SHENZHEN RUICHIPS SEMICONDUCTOR CO LTD
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SHENZHEN RUICHIPS SEMICONDUCTOR CO LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The invention discloses a method for improving the grid-source leakage of a groove type metal oxide semiconductor, which ensures that the quality of a grid oxide layer on the side wall of a groove is good and the good isolation effect of a grid and a source is achieved by avoiding the grid oxide layer on the side wall of the groove from being damaged twice due to the injection of a P-type impurity body region and the injection of an N-type impurity source region, thereby improving the grid-source leakage of a device, avoiding the quality reduction and the failure of the device caused by the grid-source leakage and having good market application value.

Description

Method for improving electric leakage of groove type metal oxide semiconductor grid source
Technical Field
The invention relates to the field of semiconductor chip manufacturing, in particular to a method for improving electric leakage of a trench type metal oxide semiconductor grid source.
Background
double-Diffused Metal Oxide Semiconductor (DMOS) transistors combine the advantages of bipolar transistors and common Metal Oxide Semiconductor (MOS) devices, and DMOS is an ideal power device for both switching and linear applications. DMOS is mainly used for inverters, electronic switches, hi-fi stereo, automotive appliances, electronic ballasts, and the like.
DMOS is divided into planar DMOS and trench DMOS, planar DMOS mainly develops towards high voltage, and trench DMOS mainly develops towards medium and low voltage, and both of them are continuously changed and developed and innovated with the application environment, and the performance requirement is more and more rigorous, and a key parameter for measuring the performance is gate-source leakage, which generally requires that the gate-source leakage is less than 100 nanoamperes, if the gate-source leakage is large, the power consumption is increased slightly, the device life is shortened, and if the gate-source leakage is large, the gate-source short circuit occurs, and the device function is invalid. Meanwhile, among various parameters affecting the product yield, gate-source leakage is also a very difficult problem to solve, so that the problem of large gate-source leakage is overcome, and the gate-source leakage is very important for the DMOS device.
The prior art comprises the following steps:
as shown in fig. 1, X1, growing an initial oxide layer 3 on an N-type epitaxial layer 2 on an N-type silicon substrate 1, depositing an oxide layer 4, defining a cell region by using a trench lithography layer 5, and then etching the oxide layer 4 and the initial oxide layer 3 until the upper surface of the N-type epitaxial layer 2 is etched;
as shown in fig. 2, after the trench photoresist layer 5 is removed by X2, etching the trench 6 by using the remaining oxide layer 4 and the initial oxide layer 3 as hard masks;
as shown in fig. 3, X3, removing the oxide layer 4 and the initial oxide layer 3, then growing a sacrificial oxide layer, then removing the sacrificial oxide layer, then growing the gate oxide layer 7, and then depositing the gate polysilicon 8;
as shown in fig. 4, X4, etching back the doped gate polysilicon 8 to be parallel to the upper surface of the N-type epitaxial layer 2, then annealing the gate polysilicon 8, and then performing body implantation of the P-type impurity 9, wherein a part of the P-type impurity 9 will pass through the gate oxide layer 7 on the surface of the N-type epitaxial layer 2 and enter the N-type epitaxial layer 2 to form a P-type body region 10, a part of the P-type impurity will be implanted into the gate oxide layer 7 on the sidewall of the trench 6 to cause a primary implantation damage to the gate oxide layer 7, and the gate oxide layer 7 in the dashed line frame in fig. 4 is a damaged part;
as shown in fig. 5, X5, driving in the implanted P-type impurity 9 to form a P-type body region 10;
as shown in fig. 6, X6, then implantation of source region N-type impurity 11 is carried out; at the moment, a part of N-type impurities can penetrate through the gate oxide layer 7 on the surface of the N-type epitaxial layer 2 and enter the N-type epitaxial layer 2 to form a source region 12, and a part of N-type impurities can be injected into the gate oxide layer 7 on the side wall of the groove 6 to cause secondary injection damage to the gate oxide layer 7; the gate oxide layer 7 in the dashed frame of fig. 6 is the damaged portion;
as shown in FIG. 7, X7, source region anneal at N2The method is carried out under the environment, and a source region 12 is formed;
as shown in fig. 8, X8, depositing a dielectric isolation layer 13, performing annealing reflow treatment, then performing aperture layer lithography, performing aperture 14 etching until the depth of the upper surface of the N-type epitaxial layer is 350 nm, and then removing the aperture layer photoresist;
as shown in fig. 9, X9, performing hole injection, then performing annealing to form a P-type heavily doped region 15, then depositing titanium/titanium nitride 16, then performing annealing by rapid thermal annealing, then depositing tungsten and etching back to form a tungsten plug 17, and then depositing a 4 μm front metal layer 18 to form a source 19 of the device;
as shown in fig. 10, the back side of the wafer is thinned, and the remaining thickness is 50 micrometers to 200 micrometers; and growing a back metal layer 20, wherein the back metal layer adopts titanium/nickel/silver metal to form a drain electrode 21 of the device, and the whole device is manufactured.
For a DMOS device, a grid oxide layer plays an isolation role between a grid and a source, the quality of the grid oxide layer directly influences the magnitude of grid-source leakage, in the existing trench DMOS processing technology, after the grid oxide layer grows, the grid oxide layer on the side wall of a trench is exposed on the surface, the grid oxide layer is damaged after two times of bombardment of P-type body region ion implantation and source region ion implantation, and although the grid oxide layer can be repaired in the subsequent thermal process, the grid oxide layer is difficult to be completely repaired or recovered to a state without being bombarded by ions, so that the integrity of the quality of the grid oxide layer is influenced, the isolation effect of the grid and the source is poor, the product quality reduction or product failure caused by the larger grid-source leakage is often caused, and therefore, the problem of the larger grid-source leakage is urgently needed to be improved as soon as possible.
The prior art has defects and needs to be improved.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a method for improving the gate-source leakage of a trench metal oxide semiconductor.
The invention provides a technical scheme, and a method for improving the electric leakage of a groove type metal oxide semiconductor grid source, which comprises the following steps:
s1, growing an initial oxide layer on the N-type epitaxial layer of the N-type silicon substrate, and depositing the oxide layer by adopting a low-pressure chemical vapor deposition method; defining a cellular area by adopting a groove photoetching layer, then etching an oxide layer and an initial oxide layer until the upper surface of the N-type epitaxial layer is etched; the thickness of the oxide layer after subsequent corrosion is not less than the depth of the subsequent body region injection of the P-type impurity, the depth of the body region injection of the P-type impurity is 4 times of the energy value of the body region injection of the P-type impurity, and the unit is nanometer; meanwhile, the thickness of the oxidation layer is not less than the injection depth of the N-type impurity source region, the injection depth of the N-type impurity source region is 1.5 times of the injection energy value of the N-type impurity source region, and the unit is nanometer;
s2, after the photoetching layer of the groove is removed, etching the groove by using the remained oxide layer and the initial oxide layer as hard masks, wherein the etching depth is set to be 0.8-6 microns;
s3, etching the initial oxide layer and the oxide layer by hydrofluoric acid, etching the upper surface and the side wall of the oxide layer and the side wall of the initial oxide layer in equal proportion, growing a sacrificial oxide layer, and then removing the sacrificial oxide layer;
s4, growing a grid oxide layer with the thickness of 20-150 nanometers; depositing grid polysilicon with the thickness of 400-1200 nm;
s5, etching back the doped grid polysilicon until the doped grid polysilicon is parallel to the upper surface of the oxide layer, and then annealing the grid polysilicon;
s6, removing the oxide layer and the initial oxide layer, and then injecting a P-type impurity into the body region, wherein the gate polysilicon completely covers the gate oxide layer, the thickness of the gate polysilicon is the same as that of the oxide layer after etching, and the thickness of the gate polysilicon is greater than the injection depth of the P-type impurity into the body region;
s7, driving the injected P-type impurities to form a P-type body region 10;
s8, injecting N-type impurities 11 into the source region; at the moment, the grid polycrystalline silicon completely covers the grid oxide layer, the thickness of the grid polycrystalline silicon is the same as that of the oxide layer after corrosion and is larger than the injection depth of the N-type impurity source region, so that the N-type impurity cannot be injected into the grid oxide layer;
s9, annealing the source region to form the source region;
s10, depositing a medium isolation layer, annealing and refluxing, then carrying out pore layer photoetching, carrying out pore etching till the thickness of the upper surface of the N-type epitaxial layer is 350 nanometers below the upper surface of the N-type epitaxial layer, and then removing the pore layer photoresist;
s11, injecting holes, then annealing to form a P-type heavily doped region, depositing titanium/titanium nitride with the thickness of 20-100 nm, then annealing by adopting rapid thermal annealing, depositing tungsten and etching back to form a tungsten plug, and depositing a 4-micron front metal layer to form a source electrode of the device;
s12, thinning the back of the wafer; and growing a back metal layer to form a drain electrode of the device, and finishing the manufacture of the whole device.
Preferably, in step S3, the etching distance is set to 10 nm-100 nm, and the distance is greater than 0.6 times the thickness of the sacrificial oxide layer to be grown later, minus 0.4 times the thickness of the gate oxide layer.
Preferably, in step S3, the erosion distance is set to 50 nm.
Preferably, in step S3, the hydrofluoric acid is prepared from pure water and 49% hydrofluoric acid solution by volume ratio of 50: 1.
Preferably, in step S6, the energy of the body implantation of the P-type impurity is set to 40KeV-200KeV, and the dose is set to 5E12-9E13ion/cm2。
Preferably, in step S8, the impurity for N-type impurity implantation is set to As +, the energy is set to 40KeV-150KeV, and the dose is set to 2E15-8E15ion/cm2。
Preferably, in step S8, the impurity for N-type impurity implantation is set to As +, the energy is set to 70KeV, and the dose is set to 4E15ion/cm2。
Preferably, in step S10, the dielectric isolation layer is made of an oxide layer with a thickness of 200 nm and borophosphosilicate glass with a thickness of 700 nm.
Preferably, in step S11, the hole-implanted impurity is BF2+, the energy is set to 20KeV-100KeV, and the dose is set to 5E13-3E15ion/cm2。
Preferably, in step S11, the hole-implanted impurity is BF2+, the energy is set to 40KeV, and the dose is set to 3E14ion/cm2。
Compared with the prior art, the trench DMOS device structure has the advantages that the gate oxide layer on the side wall of the trench is prevented from being damaged twice due to injection of the P-type impurity body region and injection of the N-type impurity source region, the quality of the gate oxide layer on the side wall of the trench is good, a good gate and source isolation effect is achieved, gate-source leakage of the device is improved, quality reduction and device failure caused by gate-source leakage are avoided, and the trench DMOS device structure has good market application value.
Drawings
FIG. 1 is a schematic representation of prior art step X1;
FIG. 2 is a schematic diagram of prior art step X2;
FIG. 3 is a schematic diagram of prior art step X3;
FIG. 4 is a schematic diagram of prior art step X4;
FIG. 5 is a schematic of prior art step 5X;
FIG. 6 is a schematic diagram of prior art step X6;
FIG. 7 is a schematic view of prior art step X7;
FIG. 8 is a schematic view of prior art step X8;
FIG. 9 is a schematic diagram of prior art step X9
FIG. 10 is a schematic view of prior art step X10;
FIG. 11 is a diagram illustrating step S1 according to the present invention;
FIG. 12 is a diagram illustrating step S2 according to the present invention;
FIG. 13 is a schematic view of step S3 according to the present invention;
FIG. 14 is a diagram illustrating step S4 according to the present invention;
FIG. 15 is a schematic view of step S5 according to the present invention;
FIG. 16 is a diagram illustrating step S6 according to the present invention;
FIG. 17 is a schematic view of step S7 according to the present invention;
FIG. 18 is a diagram illustrating step S8 according to the present invention;
FIG. 19 is a schematic view of step S9 according to the present invention;
FIG. 20 is a schematic view of step S10 according to the present invention;
FIG. 21 is a diagram illustrating step S11 according to the present invention;
FIG. 22 is a schematic view of step S12 according to the present invention;
the figures are labeled as follows:
1. an N-type silicon substrate; 2. A type epitaxial layer;
3. an initial oxide layer; 4. an oxide layer;
5. a groove photoetching layer; 6. a trench;
7. a gate oxide layer; 8. grid polysilicon;
9. a P-type impurity; 10. a P-type body region;
11. an N-type impurity; 12. a source region;
13. a dielectric isolation layer; 14. an aperture;
15. a P-type heavily doped region; 16. titanium/titanium nitride;
17. a tungsten plug; 18. a front metal layer;
19. a source electrode; 20. a back metal layer;
21. and a drain electrode.
Detailed Description
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for descriptive purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail with reference to the accompanying drawings.
A method for improving the electric leakage of a trench type metal oxide semiconductor gate source comprises the following steps of S1, growing an initial oxide layer 3 on an N type epitaxial layer 2 of an N type silicon substrate 1, setting the thickness to be 10 nanometers-100 nanometers, preferably 50 nanometers, and depositing an oxide layer 4 of 700 nanometers-1200 nanometers, preferably 800 nanometers, by adopting a low-pressure chemical vapor deposition method, as shown in figure 11; defining a cellular area by adopting a trench photoetching layer 5, and then etching an oxide layer 4 and an initial oxide layer 3 until the upper surface of the N-type epitaxial layer is etched; the thickness of the oxide layer after subsequent corrosion is not less than the depth of the subsequent body region injection of the P-type impurity, the depth of the body region injection of the P-type impurity is 4 times of the energy value of the body region injection of the P-type impurity, and the unit is nanometer; meanwhile, the thickness of the oxidation layer is not less than the injection depth of the N-type impurity source region, the injection depth of the N-type impurity source region is 1.5 times of the injection energy value of the N-type impurity source region, and the unit is nanometer;
as shown in fig. 12, after removing the trench photoresist layer 5, S2, etching the trench 6 by using the remaining oxide layer 4 and the initial oxide layer 3 as a hard mask, wherein the etching depth is set to 0.8 to 6 microns, preferably 1.3 microns;
as shown in fig. 13, S3, etching the initial oxide layer 3 and the oxide layer 4 with hydrofluoric acid, where the upper surface and the sidewalls of the oxide layer 4 and the sidewalls of the initial oxide layer 3 are etched in equal proportion, the etching is performed to shrink the sidewalls of the oxide layer 4 and the thermally generated oxide layer 3 by a distance compared with the sidewalls of the trench 6, and then a structure for protecting the gate oxide layer is formed in the subsequent step, where the etching distance is in a range of 10 nm to 100 nm, and cannot exceed the distance, otherwise, the subsequent implantation of the P-type impurity body region and the formation of the P-type body region are affected, and the distance range is greater than 0.6 times the thickness of the sacrificial oxide layer to be grown in the subsequent step, minus 0.4 times the absolute value of the thickness of the gate oxide layer, and preferably 50 nm, growing the sacrificial oxide layer; for example, a 50 nm distance etch with hydrofluoric acid is followed by a 50 nm sacrificial oxide layer growth and then a 50 nm sacrificial oxide layer removal.
Further, the hydrofluoric acid is prepared from pure water and 49% hydrofluoric acid raw solution according to the volume ratio of 50: 1.
As shown in fig. 14, S4, growing the gate oxide layer 7 with a thickness set to 20 nm-150 nm, preferably 50 nm; a gate polysilicon 8 is then deposited to a thickness of 400 nm to 1200 nm, preferably set to a thickness of 1000 nm.
As shown in fig. 15, S5 is performed to etch back the doped gate polysilicon 8 to be parallel to the upper surface of the oxide layer 4, and then the gate polysilicon 8 is annealed at 1000 degrees celsius for 90 minutes.
As shown in FIG. 16, S6, removing the oxide layer 4 and the initial oxide layer 3, and then performing a body implantation of P-type impurity 9 with an energy of 40KeV-200KeV and a dose of 5E12-9E13ion/cm2Preferably B +,60KeV,1E13ion/cm2At this time, the gate polysilicon 8 completely covers the gate oxide layer 7, the thickness of the gate polysilicon is the same as that of the oxide layer after etching, the thickness of the gate polysilicon 8 is 750 nanometers, and the thickness is larger than the injection depth of the P-type impurity 9 in the body region, so that the P-type impurity 9 cannot be injected into the gate oxide layer 7, and the gate oxide layer 7 is prevented from being damaged by one-time injection.
As shown in fig. 17, S7 forms the P-type body region 10 by driving-in the implanted P-type impurity 9 at 1000-.
As shown in FIG. 18, S8, implantation of N-type impurity 11 is performed in the source region, the impurity is As +, the energy is 40KeV-150KeV, and the dose is 2E15-8E15ion/cm2The preferred conditions are: AS +,70KeV,4E15ion/cm2(ii) a At this time, the grid polycrystalline silicon 8 completely covers the grid oxide layer 7, the thickness of the grid polycrystalline silicon 8 is the same as that of the oxide layer 4 after corrosion, the thickness of the grid polycrystalline silicon is 750 nanometers and is larger than the injection depth of the N-type impurity 11 source region, so that the N-type impurity 11 cannot be injected on the grid oxide layer 7, and the secondary injection damage of the grid oxide layer 7 is avoided;
as shown in fig. 19, S9, source region annealing is performed under the condition set to 850 degrees celsius for 60 minutes at N2The process is performed in ambient conditions to form source regions 12.
As shown in fig. 20, S10, depositing a dielectric isolation layer 13, where the dielectric isolation layer 13 is composed of an oxide layer with a thickness of 200 nm + borophosphosilicate glass with a thickness of 700 nm, performing annealing reflow treatment under the condition of 850 ℃ for 30 minutes, then performing a hole layer lithography, performing a hole 14 lithography until the etching is 350 nm below the upper surface of the N-type epitaxial layer, and then removing the hole layer photoresist.
As shown in FIG. 21, S11, hole implantation was performed with the implantation impurity BF2+, the energy was 20KeV-100KeV, and the dose was 5E13-3E15ion/cm2The preferred conditions are: BF2+,40KeV,3E14 ion/cm2Then annealing at 1000 ℃ for 30 seconds to form a P-type heavily doped region 15, then depositing titanium/titanium nitride 16 with the thickness of 20-100 nanometers, preferably depositing titanium 40 nm/titanium nitride 60 nm, and then annealing the titanium/titanium nitride by adopting rapid thermal annealing under the conditions of 650-900 ℃ for 15-60 seconds, N2Ambient, preferably 850 degrees celsius for 30 seconds, and then depositing and etching back tungsten to form the tungsten plug 17 and then depositing the 4 micron front side metal layer 18 to form the source 19 of the device.
As shown in fig. 22, S12, thinning the back side of the wafer to a remaining thickness of 50 microns to 200 microns, preferably 90 microns; and growing a back metal layer 20, wherein the back metal layer is made of titanium/nickel/silver metal and is set to be 100 nm/200 nm/1000 nm, forming a drain electrode 21 of the device, and finishing the manufacturing of the whole device.
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method for improving the drain current of a trench metal oxide semiconductor gate source is characterized by comprising the following steps:
s1, growing an initial oxide layer on the N-type epitaxial layer of the N-type silicon substrate, and depositing the oxide layer by adopting a low-pressure chemical vapor deposition method; defining a cellular area by adopting a groove photoetching layer, then etching an oxide layer and an initial oxide layer until the upper surface of the N-type epitaxial layer is etched; the thickness of the oxide layer after subsequent corrosion is not less than the depth of the subsequent body region injection of the P-type impurity, the depth of the body region injection of the P-type impurity is 4 times of the energy value of the body region injection of the P-type impurity, and the unit is nanometer; meanwhile, the thickness of the oxidation layer is not less than the injection depth of the N-type impurity source region, the injection depth of the N-type impurity source region is 1.5 times of the injection energy value of the N-type impurity source region, and the unit is nanometer;
s2, after the photoetching layer of the groove is removed, etching the groove by using the remained oxide layer and the initial oxide layer as hard masks, wherein the etching depth is set to be 0.8-6 microns;
s3, etching the initial oxide layer and the oxide layer by hydrofluoric acid, etching the upper surface and the side wall of the oxide layer and the side wall of the initial oxide layer in equal proportion, growing a sacrificial oxide layer, and then removing the sacrificial oxide layer;
s4, growing a grid oxide layer with the thickness of 20-150 nanometers; depositing grid polysilicon with the thickness of 400-1200 nm;
s5, etching back the doped grid polysilicon until the doped grid polysilicon is parallel to the upper surface of the oxide layer, and then annealing the grid polysilicon;
s6, removing the oxide layer and the initial oxide layer, and then injecting a P-type impurity into the body region, wherein the gate polysilicon completely covers the gate oxide layer, the thickness of the gate polysilicon is the same as that of the oxide layer after etching, and the thickness of the gate polysilicon is greater than the injection depth of the P-type impurity into the body region;
s7, driving the injected P-type impurities to form a P-type body region 10;
s8, injecting N-type impurities 11 into the source region; at the moment, the grid polycrystalline silicon completely covers the grid oxide layer, the thickness of the grid polycrystalline silicon is the same as that of the oxide layer after corrosion and is larger than the injection depth of the N-type impurity source region, so that the N-type impurity cannot be injected into the grid oxide layer;
s9, annealing the source region to form the source region;
s10, depositing a medium isolation layer, annealing and refluxing, then carrying out pore layer photoetching, carrying out pore etching till the thickness of the upper surface of the N-type epitaxial layer is 350 nanometers below the upper surface of the N-type epitaxial layer, and then removing the pore layer photoresist;
s11, injecting holes, then annealing to form a P-type heavily doped region, depositing titanium/titanium nitride with the thickness of 20-100 nm, then annealing by adopting rapid thermal annealing, depositing tungsten and etching back to form a tungsten plug, and depositing a 4-micron front metal layer to form a source electrode of the device;
s12, thinning the back of the wafer; and growing a back metal layer to form a drain electrode of the device, and finishing the manufacture of the whole device.
2. The method of claim 1, wherein in step S3, the etching distance is set to be 10 nm-100 nm, and the distance is greater than 0.6 times the thickness of the sacrificial oxide layer to be grown later and 0.4 times the thickness of the gate oxide layer.
3. The method of claim 2, wherein in step S3, the etching distance is set to 50 nm.
4. The method of claim 2 or 3, wherein in step S3, the hydrofluoric acid is prepared from pure water and 49% hydrofluoric acid solution by volume ratio of 50: 1.
5. The method of claim 1, wherein in step S6, the energy of the body implantation of P-type impurities is set to 40KeV-200KeV, and the dose is set to 5E12-9E13ion/cm2。
6. The method of claim 1, wherein in step S8, the N-type impurity implantation is performed with As + and energy set to 40KeV-150KeV and dose set to 2E15-8E15ion/cm2。
7. The method of claim 6, wherein in step S8, the N-type impurity implantation impurity is set As +, the energy is set to 70KeV, and the dose is set to 4E15ion/cm2。
8. The method of claim 1, wherein in step S10, the dielectric isolation layer is formed of an oxide layer with a thickness of 200 nm and borophosphosilicate glass with a thickness of 700 nm.
9. The method of claim 1, wherein in step S11, the hole implantation impurity is BF2+, the energy is set to 20KeV-100KeV, and the dose is set to 5E13-3E15ion/cm2。
10. An apparatus as claimed in claim 9The method for improving drain leakage of trench MOS gate source is characterized in that in step S11, the hole-implanted impurity is BF2+, the energy is set to 40KeV, and the dose is set to 3E14ion/cm2。
CN201911220369.2A 2019-12-03 2019-12-03 Method for improving electric leakage of groove type metal oxide semiconductor grid source Pending CN111009577A (en)

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Application publication date: 20200414