CN111008101A - Debugging verification platform and testing method of RISC-V processor system - Google Patents

Debugging verification platform and testing method of RISC-V processor system Download PDF

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CN111008101A
CN111008101A CN201910995241.7A CN201910995241A CN111008101A CN 111008101 A CN111008101 A CN 111008101A CN 201910995241 A CN201910995241 A CN 201910995241A CN 111008101 A CN111008101 A CN 111008101A
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control module
mode
processor
risc
interface
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CN111008101B (en
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王贤坤
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2247Verification or detection of system hardware configuration
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273Test methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/267Reconfiguring circuits for testing, e.g. LSSD, partitioning

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

The invention provides a debugging verification platform and a testing method of a RISC-V processor system, comprising a processor soft core, wherein the processor soft core is respectively communicated with an RAM storage control module and a UART data control module through a bus module; the platform also comprises a mode control module, wherein the mode control module is respectively connected with the RAM storage control module and the UART data control module; the RAM storage control module is connected with an RAM storage; the method is used for code instruction storage and program operation; the mode control module is connected with a GPIO interface and used for generating a control signal to the processor soft core to carry out system mode conversion according to an input signal of the GPIO interface; the UART data control module is connected with a UART interface; and the UART interface switching control module is used for controlling and switching the mode of the UART interface according to the conversion of the system mode.

Description

Debugging verification platform and testing method of RISC-V processor system
Technical Field
The invention relates to the technical field of design verification of processors, in particular to a debugging verification platform and a testing method of a RISC-V processor system.
Background
The FPGA has the programmable characteristic, is flexible and stable, has high speed and high efficiency, is a supplement to the ASIC, and can also be used as a verification platform of the ASIC.
RISC-V is a novel and advanced instruction set that is widely adopted in processor design due to its look-ahead, reduction, extensibility, and open source features.
In the design verification process of the processor, the starting and debugging of the operating system are indispensable processes. The starting file of the system needs storage space of an SD card or Flash and the like, an SoC verification platform of a RISC-V processor is built based on FPGA, and related peripheral devices such as the SD card or Flash are added, so that the system is a relatively time-consuming task, and meanwhile, the FPGA board card needs to be provided with an SD card interface or a Flash debugging interface and enough Flash storage space, so that the limitation condition is more.
Disclosure of Invention
The invention provides a debugging verification platform and a testing method of a RISC-V processor system, aiming at the problems that the SoC verification platform is set up complicatedly and the requirement of a board card is high in the debugging process of the RISC-V system.
The technical scheme of the invention is as follows:
on one hand, the technical scheme of the invention provides a debugging verification platform of a RISC-V processor system, the RISC-V processor system starting SoC verification platform based on FPGA comprises a processor soft core, the processor soft core is respectively communicated with an RAM storage control module and a UART data control module through a bus module;
the platform also comprises a mode control module, wherein the mode control module is respectively connected with the RAM storage control module and the UART data control module;
the RAM storage control module is connected with an RAM storage; the method is used for code instruction storage and program operation;
the mode control module is connected with a GPIO interface and used for generating a control signal to the processor soft core to carry out system mode conversion according to an input signal of the GPIO interface;
the UART data control module is connected with a UART interface; and the UART interface switching control module is used for controlling and switching the mode of the UART interface according to the conversion of the system mode.
Preferably, the system mode includes a system debugging mode or a code updating mode.
The mode control module is a GPIO mode control module.
A minimum system of the RISC-V processor is built on the FPGA and comprises a soft core of the RISC-V processor, a bus module is mounted with a RAM memory and a UART interface, the mode switching of the operation and debugging of the processor is realized through an external general GPIO interface, the UART interface is fully utilized as a communication interface and a code updating and debugging interface of the system operation, and the system starting program stored in the RAM memory is updated and tested.
Preferably, the RAM memory control module is configured to switch the control right of the RAM memory between the bus module of the RISC-V processor and the UART data control module according to the control signal of the GPIO.
Preferably, the UART data control module is configured to switch the UART interface to a system debugging interface or a code updating interface according to the control mode of the GPIO;
in the update mode, the UART data control module comprises an RAM initialization function and controls the storage and the read-back of RAM memory data, thereby ensuring the smooth update of codes.
Preferably, the platform further comprises a CRC check module; and the CRC check module is used for counting the updated data of the UART interface codes and the stored read-back data of the RAM memory according to bytes and carrying out CRC check in the updating mode.
Preferably, the platform further comprises a mode switch indicator light;
the mode switching indicator lamp is connected with the GPIO mode control module and used for indicating a switching mode;
preferably, the platform further comprises a verification indicator light; and the verification indicator light is connected with the CRC check module and used for indicating the check result.
Preferably, the RAM memory comprises a first memory and a second memory; the first memory and the second memory are respectively connected with the RAM memory control module and used for storing a system starting code;
the GPIO interface comprises a first GPIO interface and a second GPIO interface.
And the mode control module generates a control signal according to the general purpose GPIO interface and divides the system into a debugging mode or an updating mode. In a debugging mode, a RISC-V processor bus normally mounts an RAM storage module and a UART interface module, and the system normally runs; in the update mode, the RISC-V processor is in the reset state, the control right of the bus to the peripheral is taken over, the UART interface is used as a code update interface, and the replacement of debugging codes in the RAM memory is realized.
The RAM storage control module realizes the conversion between an AXI bus interface and a storage interface and supports the non-byte alignment write operation of a RAM with 64bits of bit width. And flexibly switching the control right of the RISC-V processor bus end and the UART update interface end to the RAM according to the control enabling of the GPIO.
And the UART data control module switches the UART interface into a system debugging interface or a code updating interface according to the control mode of the GPIO. In the updating mode, the module comprises an initialization function of the RAM memory, can control the storage and the read-back of the RAM data and ensures the smooth updating of the code.
And the CRC check module can count the updated data of the UART interface code and the read-back data stored in the RAM according to bytes and perform CRC check in an updating mode, and when the byte numbers are consistent and the CRC check values are matched, the code updating is finished and correct. The read-back data can also be output through the UART interface.
On the other hand, the technical scheme of the invention provides a method for testing a debugging system of a RISC-V processor system, which comprises the following steps:
the RISC-V processor starts to run, and the start code starts to run;
entering a system debugging mode, judging whether the system runs normally, and finishing the operation, otherwise, executing the next step;
optimizing and modifying the starting code, entering a system code updating mode to update the starting code, setting GPIO (general purpose input/output) to 0 after the code is updated, clearing the reset state of the processor, and executing the following steps: the RISC-V processor starts running and the boot code starts running.
Preferably, the step of updating the boot code includes:
setting GPIO to 1, switching the control right of UART interface and corresponding RAM memory, and setting the processor in reset state;
refreshing the corresponding RAM memory space value to be 0;
updating and writing the UART interface code into a corresponding RAM memory for storage;
after the updating is finished, the updated data is checked, if the checking is correct, whether the next code file needs to be updated is judged, if not, GPIO is set to be 0, and the reset state of the processor is cleared; if the verification is incorrect or not correct, executing the following steps: and setting GPIO to be 1, switching the control right of the UART interface and the corresponding RAM memory, and setting the processor to be in a reset state.
According to the technical scheme, the invention has the following advantages: the simplified RISC-V processor system platform structure designed by the invention can quickly build a system debugging platform; the universal UART/GPIO debugging interface is simple and reusable; the hardware resource requirement is low, and the method is suitable for a universal FPGA board card; the method has the advantages of being flexible, convenient, simple in interface, high in debugging flexibility, suitable for a universal FPGA board card, capable of improving project parallelism and accelerating project progress, and the like, and can be used for quickly inputting system test work.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a block diagram of a debug verification platform of a RISC-V processor system according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating a testing method for a debugging system of a RISC-V processor system according to a second embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 1, the technical solution of the present invention provides a debugging and verifying platform of a RISC-V processor system, the RISC-V processor system starting SoC verifying platform based on FPGA comprises a processor soft core, the processor soft core communicates with a RAM storage control module and a UART data control module through a bus module respectively;
the platform also comprises a mode control module, wherein the mode control module is respectively connected with the RAM storage control module and the UART data control module;
the RAM storage control module is connected with an RAM storage; the method is used for code instruction storage and program operation;
the mode control module is connected with a GPIO interface and used for generating a control signal to the processor soft core to carry out system mode conversion according to an input signal of the GPIO interface;
the UART data control module is connected with a UART interface; and the UART interface switching control module is used for controlling and switching the mode of the UART interface according to the conversion of the system mode.
The system mode comprises a system debugging mode or a code updating mode. In this embodiment, the bus module includes an AXI bus; the mode control module is a GPIO mode control module. And the mode control module generates a control signal according to the general purpose GPIO interface and divides the system into a debugging mode or an updating mode. In a debugging mode, an AXI bus of the RISC-V processor normally mounts an RAM storage module and a UART data control module, and the system normally runs; in the update mode, the RISC-V processor is in the reset state, the control right of the bus to the peripheral is taken over, the UART interface is used as a code update interface, and the replacement of debugging codes in the RAM memory is realized.
A minimum system of the RISC-V processor is built on the FPGA and comprises a soft core of the RISC-V processor, an AXI bus is used for mounting a RAM memory and a UART interface, the mode switching of the running and debugging of the processor is realized through an external general GPIO interface, the UART interface is fully utilized as a communication interface and a code updating and debugging interface of the system running, and a system starting program stored in the RAM memory is updated and tested.
The RAM storage control module is used for switching the control right of the RAM storage by the AXI bus of the RISC-V processor and the UART data control module according to the control signal of the GPIO. The RAM storage control module realizes the conversion between an AXI bus interface and a storage interface and supports the non-byte alignment write operation of a RAM with 64bits of bit width. And flexibly switching the control right of the RISC-V processor bus end and the UART update interface end to the RAM according to the control enabling of the GPIO.
The UART data control module is used for switching the UART interface into a system debugging interface or a code updating interface according to the control mode of the GPIO; and the UART data control module switches the UART interface into a system debugging interface or a code updating interface according to the control mode of the GPIO. In the updating mode, the module comprises an initialization function of the RAM memory, can control the storage and the read-back of the RAM data and ensures the smooth updating of the code.
In the update mode, the UART data control module comprises an RAM initialization function and controls the storage and the read-back of RAM memory data, thereby ensuring the smooth update of codes.
The platform also comprises a CRC check module; and the CRC check module is used for counting the updated data of the UART interface codes and the stored read-back data of the RAM memory according to bytes and carrying out CRC check in the updating mode. And the CRC check module can count the updated data of the UART interface code and the read-back data stored in the RAM according to bytes and perform CRC check in an updating mode, and when the byte numbers are consistent and the CRC check values are matched, the code updating is finished and correct. The read-back data can also be output through the UART interface.
The platform further comprises a mode switching indicator light;
the mode switching indicator lamp is connected with the GPIO mode control module and used for indicating a switching mode;
the platform further comprises a verification indicator light; and the verification indicator light is connected with the CRC check module and used for indicating the check result.
The RAM memory includes a first memory RAM1 and a second memory RAM 2; the first storage RAM1 and the second storage RAM2 are respectively connected with the RAM storage control module and are used for storing system starting codes;
the GPIO interfaces comprise a first GPIO interface GPIO1 and a second GPIO interface GPIO 2.
Example two
As shown in fig. 2, the present invention provides a testing method for a debugging system of a RISC-V processor system, and for the debugging platform of the first embodiment, the RISC-V system start testing method of the present invention can be divided into two modes of debugging and updating according to GPIO control, including the following steps:
s1: the RISC-V processor starts to run;
s2: starting the code to run;
for a RISC-V processor soft core, its operating frequency, the BootRom address, and the bus address of the RAM need to be configured correctly. The system boot code includes ZSBL, FSBL, BBL, and Kernel, in order to save storage resources, optimize invalid codes as much as possible, optimize and simplify Kernel, and meanwhile, because the SoC minimum system is adopted, redundant hardware initialization codes are omitted, and the final system boot code file meets the requirements of storage and running space (for the function and optimization process of the boot code, detailed description is not given in this embodiment). In the practical application process, ZSBL is stored in a BootRom of a RISC-V processor, FSBL is stored in a RAM1, BBL and Kernel are stored in a RAM2, and a proper amount of running space is reserved, so that a simple testing environment for starting and running the system is realized.
S: 3: entering a system debugging mode, judging whether the system operation debugging is normal or not, if so, finishing the test, and otherwise, executing S4;
in a debugging mode, the GPIO1 and 2 value is 0, the RISC-V processor normally runs, starts from BootRom, jumps to the RAM1 and RAM2 running codes step by step, completes the initialization of hardware equipment, reads the memory address and running address of BBL and Kernel, starts the starting test of an operating system, and a UART interface can be used as a debugging interface for information printing and system operation.
S4: and (4) performing optimization modification on the starting code, entering a system code updating mode to update the starting code, setting the GPIO to 0 after the code is updated, clearing the reset state of the processor, and executing the step S1.
It should be noted that the step of updating the boot code includes:
s41: setting GPIO to 1, switching the control right of UART interface and RAM memory, and setting the processor in reset state;
s42: refreshing the space value of the RAM memory to be 0;
s43: updating and writing the UART interface code into an RAM memory for storage;
s44: checking the updated data after the updating is finished, if the checking is correct, executing the step S45, and if the checking is incorrect, executing the step S41;
s45: judging whether a next code file needs to be updated or not, if not, setting GPIO (general purpose input/output) to 0 and clearing the reset state of the processor; step S1 is executed; if yes, go to step S41.
In the test process, when the system code needs to be reloaded, the corresponding GPIO value can be set to be 1, an updating mode is entered, the RISC-V processor is in a reset state in the mode, and meanwhile, UART is switched to be used as an updating interface of the system code to update the code of the corresponding RAM (in an example system, GPIO1 corresponds to RAM1, and GPIO2 corresponds to RAM 2). After the GPIO is set, the corresponding RAM space value is initialized to be 0 at first, and the problem of subsequent system operation caused by inconsistent code size is solved. And then updating and checking codes, and ensuring the accuracy of data updating each time (for convenient debugging, different RAM debugging and checking states can be indicated by using an LED lamp). After the code is updated, the GPIO value is set to 0, the reset state of the RISC-V processor can be cleared, and the system is debugged again.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A debugging verification platform of a RISC-V processor system is characterized by comprising a processor soft core, wherein the processor soft core is respectively communicated with an RAM storage control module and a UART data control module through a bus module;
the platform also comprises a mode control module, wherein the mode control module is respectively connected with the RAM storage control module and the UART data control module;
the RAM storage control module is connected with an RAM storage; the method is used for code instruction storage and program operation;
the mode control module is connected with a GPIO interface and used for generating a control signal to the processor soft core to carry out system mode conversion according to an input signal of the GPIO interface;
the UART data control module is connected with a UART interface; and the UART interface switching control module is used for controlling and switching the mode of the UART interface according to the conversion of the system mode.
2. A debugging validation platform for a RISC-V processor system according to claim 1, wherein said system mode comprises a system debugging mode or a code update mode.
The mode control module is a GPIO mode control module.
3. A debugging platform of RISC-V processor system according to claim 2, characterized in that said RAM memory control module is used for switching the control right of the RAM memory to the bus module of RISC-V processor and the UART data control module according to the control signal of GPIO.
4. The debugging platform of a RISC-V processor system of claim 3, characterized in that said UART data control module, is used for switching UART interface to system debugging interface or code updating interface according to the control mode of GPIO;
in the update mode, the UART data control module comprises a RAM initialization function and controls the storage and read-back of RAM memory data.
5. A RISC-V processor system debug validation platform according to claim 2, wherein said platform further comprises a CRC check module; and the CRC check module is used for counting the updating data of the UART interface codes and the stored read-back data of the RAM memory according to bytes and carrying out CRC check in the code updating mode.
6. A RISC-V processor system debugging validation platform according to claim 2, further comprising a mode switch indicator light;
and the mode switching indicator lamp is connected with the GPIO mode control module and used for indicating a switching mode.
7. A RISC-V processor system debugging validation platform according to claim 5, further comprising a validation indicator light; and the verification indicator light is connected with the CRC check module and used for indicating the check result.
8. A debugging validation platform of a RISC-V processor system according to claim 2, characterized in that said RAM memory comprises a first memory and a second memory; the first memory and the second memory are respectively connected with the RAM memory control module and used for storing a system starting code;
the GPIO interface comprises a first GPIO interface and a second GPIO interface.
9. A test method for debugging system of RISC-V processor system is characterized by that it includes the following steps:
the RISC-V processor starts to run, and the start code starts to run;
entering a system debugging mode, judging whether the system runs normally, and finishing the operation, otherwise, executing the next step;
optimizing and modifying the starting code, entering a system code updating mode to update the starting code, setting GPIO (general purpose input/output) to 0 after the code is updated, clearing the reset state of the processor, and executing the following steps: the RISC-V processor starts running and the boot code starts running.
10. A method for testing a debugging system of a RISC-V processor system according to claim 9, wherein said step of performing an update of the boot code comprises:
setting GPIO to 1, switching the control right of UART interface and corresponding RAM memory, and setting the processor in reset state;
refreshing the corresponding RAM memory space value to be 0;
updating and writing the UART interface code into a corresponding RAM memory for storage;
after the updating is finished, the updated data is checked, if the checking is correct, whether the next code file needs to be updated is judged, if not, GPIO is set to be 0, and the reset state of the processor is cleared; if the verification is incorrect or not correct, executing the following steps: and setting GPIO to be 1, switching the control right of the UART interface and the corresponding RAM memory, and setting the processor to be in a reset state.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113010355A (en) * 2021-02-20 2021-06-22 山东英信计算机技术有限公司 RISC-V system verification method and device based on FPGA and electronic equipment
CN113836081A (en) * 2021-09-29 2021-12-24 南方电网数字电网研究院有限公司 System-on-a-chip architecture
CN116450570A (en) * 2023-06-19 2023-07-18 先进能源科学与技术广东省实验室 32-bit RISC-V processor based on FPGA and electronic equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090217105A1 (en) * 2008-02-26 2009-08-27 Po-Chun Hsu Debug device for embedded systems and method thereof
CN109783290A (en) * 2019-01-09 2019-05-21 郑州云海信息技术有限公司 A kind of RISC-V controller adjustment method and device based on UART

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090217105A1 (en) * 2008-02-26 2009-08-27 Po-Chun Hsu Debug device for embedded systems and method thereof
CN109783290A (en) * 2019-01-09 2019-05-21 郑州云海信息技术有限公司 A kind of RISC-V controller adjustment method and device based on UART

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HYUNGBAE PARK 等: "《Design of On-Chip Debug System for embedded processor》", 《2008 INTERNATIONAL SOC DESIGN CONFERENCE》 *
张明 等: "《面向众核处理器的独立调试系统设计方法》", 《湖南大学学报(自然科学版)》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113010355A (en) * 2021-02-20 2021-06-22 山东英信计算机技术有限公司 RISC-V system verification method and device based on FPGA and electronic equipment
CN113836081A (en) * 2021-09-29 2021-12-24 南方电网数字电网研究院有限公司 System-on-a-chip architecture
CN113836081B (en) * 2021-09-29 2024-01-23 南方电网数字电网研究院有限公司 System-on-chip architecture
CN116450570A (en) * 2023-06-19 2023-07-18 先进能源科学与技术广东省实验室 32-bit RISC-V processor based on FPGA and electronic equipment
CN116450570B (en) * 2023-06-19 2023-10-17 先进能源科学与技术广东省实验室 32-bit RISC-V processor based on FPGA and electronic equipment

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