CN113836081B - System-on-chip architecture - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The application provides a system-on-chip architecture. The system-on-chip architecture comprises an open source instruction set architecture based on a reduced instruction set principle, a memory, an AHB bus matrix, a bus architecture and a peripheral module. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory. The AHB bus matrix is electrically connected with the memory and the open source instruction set architecture based on the reduced instruction set principle. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory and the AHB bus matrix through the bus architecture. The AHB bus matrix is electrically connected with the peripheral module. By the open source instruction set architecture based on the principle of a simplified instruction set, the development can be independently and controllably performed. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory and the AHB bus matrix through the bus architecture, and the AHB bus matrix is electrically connected with the peripheral module, so that the performances, parameters and the like of the cache, the bus and the core can be subjected to autonomous controllable configuration design, and autonomous controllable development can be completed aiming at different application scenes.
Description
Technical Field
The present disclosure relates to the field of chip architecture, and in particular, to a system-on-chip architecture.
Background
With the development of the economy and society, electric energy becomes an important foundation for the development of the society. And the safe, stable and efficient use of power systems has become a hotspot for research. Currently, smart grid systems are being gradually popularized and developed, and the security problem is a serious issue in development.
The embedded control system in the intelligent power grid is a key for guaranteeing the safety of the power grid system, and the intelligent power grid has the characteristics of being capable of monitoring and early warning faults of the power grid system in real time and being autonomous and controllable. Processor cores are a core component of embedded systems, with the use of soft-core processors being very widespread. The existing soft core processor has the technical problem that the development cannot be performed independently and controllably.
Disclosure of Invention
Based on this, it is necessary to provide a system-on-chip architecture for the problem that the existing soft-core processor cannot be developed independently and controllably.
A system-on-chip architecture comprises an open source instruction set architecture based on a reduced instruction set principle, a memory, an AHB bus matrix, a bus architecture and a peripheral module. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory. The AHB bus matrix is electrically connected with the memory and the open source instruction set architecture based on the reduced instruction set principle. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory and the AHB bus matrix through the bus architecture. The AHB bus matrix is electrically connected with the peripheral module.
In one embodiment, a system-on-chip architecture includes a debug component and a clock control module. The debugging component is connected with the open source instruction set architecture based on the principle of simplifying instruction sets. The clock control module is connected with the open source instruction set architecture based on the reduced instruction set principle and controls the working clock of the system-on-chip architecture.
In one embodiment, the peripheral modules include a high-speed peripheral, an AHB2APB bridge, and a low-speed peripheral. The AHB bus matrix is electrically connected with the high-speed peripheral and the AHB2APB bridge. The AHB2APB bridge is electrically connected with the low-speed peripheral.
In one embodiment, the bus architecture includes an instruction bus, a data bus, and a system bus. The memory may include on-chip static random access memory, read-only memory, and/or on-chip flash memory. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the read-only memory and/or the on-chip flash memory through the instruction bus. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the on-chip static random access memory through the data bus. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the AHB bus matrix through the system bus.
In one embodiment, the high-speed peripheral includes a phase-locked loop controller, an analog-to-digital converter controller, a fault algorithm determiner, and a separate static random access memory. The phase-locked loop controller is connected with the AHB bus matrix and the phase-locked loop module and is used for controlling the register configuration of the phase-locked loop module. The analog-to-digital converter controller is connected with the AHB bus matrix and the analog-to-digital converter sampling switch and is used for controlling the analog-to-digital converter front-end sampling switch to sample data. The fault algorithm decision device is connected with the AHB bus matrix and is used for checking and/or early warning faults of the power grid system according to sampling data of the sampling front end of the analog-to-digital converter. The independent static random access memory is connected with the AHB bus matrix and used for storing data, including data sampled by the analog-to-digital converter and data processed by the fault algorithm decision device.
In one embodiment, the analog-to-digital converter front end sampling switch comprises a multi-way sampling switch. The multi-channel sampling switch is connected with the analog-to-digital converter controller, and the analog-to-digital converter controller controls the multi-channel sampling switch to collect multi-channel data.
In one embodiment, the AHB bus matrix includes a master arbiter, an address and control selector, a write data selector, a read data selector, and a slave decoder. The address and control selector is electrically connected with the host arbiter, the write data selector is electrically connected with the host arbiter, and the read data selector is electrically connected with the slave decoder.
In one embodiment, the analog-to-digital converter controller includes an analog-to-digital converter controller master and an analog-to-digital converter controller slave. The fault algorithm decision device comprises a fault algorithm decision host and a fault algorithm decision slave. The analog-to-digital converter controller host is electrically connected with the address and control selector and the write data selector, respectively. The fault algorithm judgment host is electrically connected with the address and control selector and the write data selector respectively. The analog-to-digital converter controller host is connected with the fault algorithm judgment host and then is electrically connected with the read data selector together. The analog-to-digital converter controller slave is electrically connected with the read selector, and the fault algorithm judgment slave is electrically connected with the read data selector. The analog-to-digital converter controller slave is connected with the fault algorithm judgment slave and is electrically connected with the address and control selector together. The analog-to-digital converter controller slave is connected with the fault algorithm judgment slave and then is electrically connected with the write data selector together.
In one embodiment, the low-speed peripherals include a peripheral bus, a pulse width modulator, a watchdog, a timer, a universal asynchronous receiver transmitter serial port, a serial peripheral interface, and a universal I/O port. The peripheral bus is connected with the AHB2APB bridge. The pulse width modulator is connected with the AHB2APB bridge through the peripheral bus. The watchdog is connected with the AHB2APB bridge through the peripheral bus. The timer is connected with the AHB2APB bridge through the peripheral bus. The universal asynchronous receiving and transmitting transmitter serial port is connected with the AHB2APB bridge through the peripheral bus. The serial peripheral interface is connected with the AHB2APB bridge through the peripheral bus. The general I/O port is connected with the AHB2APB bridge through the peripheral bus.
In one embodiment, the reduced instruction set architecture based on open source instruction set architecture comprises a single issue five stage pipeline architecture.
In summary, the present application provides a system-on-chip architecture. The system-on-chip architecture comprises an open source instruction set architecture based on a reduced instruction set principle, a memory, an AHB bus matrix, a bus architecture and a peripheral module. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory. The AHB bus matrix is electrically connected with the memory and the open source instruction set architecture based on the reduced instruction set principle. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory and the AHB bus matrix through the bus architecture. The AHB bus matrix is electrically connected with the peripheral module. By the open source instruction set architecture based on the principle of a simplified instruction set, the development can be independently and controllably performed. The open source instruction set architecture based on the reduced instruction set principle is electrically connected with the memory and the AHB bus matrix through the bus architecture, and the AHB bus matrix is electrically connected with the peripheral module, so that the performances, parameters and the like of the cache, the bus and the core can be subjected to autonomous controllable configuration design, and autonomous controllable development can be completed aiming at different application scenes.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a system-on-chip architecture according to an embodiment of the present application;
FIG. 2 is a second schematic diagram of a system-on-chip architecture according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a system-on-chip architecture according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a system-on-chip architecture according to an embodiment of the present application.
Fig. 5 is a schematic connection diagram of an AHB bus matrix of a system-on-chip architecture and an analog-to-digital converter controller and a fault algorithm determiner according to an embodiment of the present application.
Reference numerals:
an open source instruction set architecture 100 based on the reduced instruction set principle; a bus architecture 200; an instruction bus 210; a data bus 220; a system bus 230; a memory 300; read-only memory and/or on-chip flash memory 310; an on-chip static random access memory 320; an AHB bus matrix 400; a host arbiter 410; an address and control selector 420; a write data selector 430; a read data selector 440; a slave decoder 450; a peripheral module 500; a high-speed peripheral 510; analog-to-digital converter controller 511, analog-to-digital converter front end sampling switch 512; a phase locked loop controller 513; a phase locked loop module 514; a stand alone static random access memory 515; a fault algorithm determiner 516; AHB2APB bridge 520; a low-speed peripheral 530; peripheral bus 531; a universal asynchronous receiver transmitter serial port 532; a serial peripheral interface 533; a general purpose I/O port 534; a timer 535; a watchdog 536; a pulse width modulator 537; a debug component 600; a clock control module 700; analog-to-digital converter controller host 811; analog to digital converter controller slave 812; the failure algorithm decision host 821; the failure algorithm determines the slave 822.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below by way of examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In this application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
Referring to fig. 1, an embodiment of the present application provides a system-on-chip architecture 10. The system-on-chip architecture 10 includes an open source instruction set architecture 100 based on the reduced instruction set principle, a bus architecture 200, a memory 300, an AHB bus matrix 400, and a peripheral module 500. The open source instruction set architecture 100 based on the reduced instruction set principle is electrically connected to the memory 300. The AHB bus matrix 400 is electrically connected to the memory 300 and the open source instruction set architecture 100 based on the reduced instruction set principle. The reduced instruction set architecture 100 is electrically coupled to the memory 300 and the AHB bus matrix 400 via the bus architecture 200. The AHB bus matrix 400 is electrically connected to the peripheral module 500.
The open source instruction set architecture based on the reduced instruction set principle in the system-on-chip architecture 10 provided by the embodiment of the application is an open source RISC-V processor core, and through the RISC-V processor core, the open source instruction set architecture can be developed in an autonomous and controllable manner, and the design from low power consumption to high performance can be realized for different application scenes. And the power grid fault monitoring system is provided with common peripherals of the power grid, has the characteristics of low power consumption and high performance, and can monitor and early warn the power grid fault in real time. The working frequency of the whole system is 100MHz, the abundant hardware interfaces can meet most application requirements, the system is suitable for the scenes such as control of industrial power systems and intelligent household appliances, and the system has wide application space in 5G and IOT ages.
According to the embodiment of the application, the open source RISC-V processor Core is adopted, the internal code of the Core is developed based on the Chisel language, the open source RISC-V processor Core is an open source high-level hardware description language designed by the university of Berkeley, and the open source is completely opened, so that the cache, bus, core performance, parameters and the like of the CPU Core can be completely and controllably configured and designed according to specific application scenes, and various requirements under the smart grid environment are met.
Compared with the traditional RISC architecture, such as ARM, MIPS and the like, the RISC-V instruction set architecture has the advantages that the design of the instruction set architecture is more mature, the forward compatibility problem is not needed to be considered, and the CPU design can be optimized at the architecture level. The modularized instruction subset can cover the characteristics from a low-power-consumption deep embedded scene to a high-performance processor, such as regular instruction codes, compact memory access instructions, high-efficiency branch jump instructions and the like, so that the design of the processor is compact and the performance is not lost.
Referring also to fig. 2, in one embodiment, the system-on-chip architecture 10 includes a debug component 600 and a clock control module 700. The debug component 600 interfaces with the reduced instruction set architecture 100 based on the reduced instruction set principle. The clock control module 700 is connected to the open source instruction set architecture 100 based on the reduced instruction set principle, and controls the working clock of the system-on-chip architecture 10.
Referring to fig. 3, in one embodiment, the peripheral module 500 includes a high-speed peripheral 510, an AHB2APB bridge 520, and a low-speed peripheral 530, the AHB bus matrix 400 is electrically connected to the high-speed peripheral 510 and the AHB2APB bridge 520, and the AHB2APB bridge 520 is electrically connected to the low-speed peripheral 530.
Referring also to FIG. 4, in one embodiment, the bus architecture 200 includes an instruction bus 210, a data bus 220, and a system bus 230. The memory 300 includes on-chip static random access memory 320, read only memory, and/or on-chip flash memory 310. The reduced instruction set architecture 100 is electrically coupled to the read only memory and/or on-chip flash memory 310 via the instruction bus 210. The reduced instruction set architecture 100 is electrically coupled to the on-chip sram 320 via the data bus 220. The reduced instruction set architecture 100 is electrically coupled to the AHB bus matrix 400 via the system bus 230.
The instruction bus 210, the data bus 220, and the system bus 230 are all AHB bus architectures. The instruction bus 210 is coupled to the read only memory and/or on-chip flash memory 310. The read-only memory and the on-chip flash memory may be switched via external pins. The CPU may read the boot program from the rom or the on-chip flash memory, complete the boot of the CPU, and may select to read and execute the user program from the on-chip sram 320 or the on-chip flash memory through address jump. The data bus 220 is connected to the on-chip rom, and distributes addresses of stacks and other data running by a program through a software compiler. The system bus 230 is connected to the peripheral module 500 through the AHB bus matrix 400 for data transfer and associated address and register control of peripheral IP.
In one embodiment, the high-speed peripheral 510 includes a phase-locked loop controller 513, an analog-to-digital converter controller 511, a fault algorithm determiner 516, and a separate static random access memory 515. The phase-locked loop controller 513 is connected to the AHB bus matrix 400 and the phase-locked loop module 514, and is configured to control a register configuration of the phase-locked loop module 514. The analog-to-digital converter controller 511 is connected to the AHB bus matrix 400 and the analog-to-digital converter sampling switch, and is configured to control the analog-to-digital converter front-end sampling switch 512 to perform data sampling. The fault algorithm determiner 516 is connected to the AHB bus matrix 400, and is configured to perform troubleshooting and/or early warning on a fault of the power grid system according to sampling data of the sampling front end of the analog-to-digital converter. The independent sram 515 is coupled to the AHB bus matrix 400 for storing data, including the data sampled by the analog-to-digital converter and the data processed by the fault algorithm determiner 516.
The pll controller 513 mainly completes the register configuration of the pll module 514. The master clock frequency of the system-on-chip architecture may be autonomously adjusted by means of external software compilation. And meanwhile, the system-on-chip architecture can be connected with a bypass of the phase-locked loop, and the working clock of the system-on-chip architecture can be controlled in a mode of externally connecting the clock.
The analog-to-digital converter controller 511 is primarily used for direct memory access transfer of analog-to-digital converter sampled data. The data collected by the analog-to-digital converter can be written into the independent sram 515 by setting a transmission address or directly transmitted to an external pin through the SPI interface. The analog-to-digital converter controller 511 controls the analog-to-digital converter front-end sampling switch 512 to perform data collection.
The fault algorithm determiner 516 is an algorithm module for determining a fault of the smart grid, mainly realizes reading of data of the analog-to-digital converter, and can rapidly perform troubleshooting and determination on the fault through combination of software and hardware algorithms, thereby realizing early warning of the fault of the power grid. Common grid faults, such as arc faults in the grid, can cause abrupt changes in the voltage and current signals in the grid. The analog-digital converter is used for sampling in real time, so that the power grid fault signal data can be rapidly obtained, and specific fault information can be obtained through the fault algorithm decision device 516.
The independent sram 515 is mainly used as a system stack and a buffer for related IP data, such as data sampled by the analog-to-digital converter, data processed by the fault algorithm determiner 516, etc. The independent sram 515 has a fast read/write speed, and compared with on-chip register storage, the independent sram 515 saves more chip area, thereby improving the performance of system operation.
In one embodiment, the analog-to-digital converter front end sampling switch 512 comprises a multi-way sampling switch. The multi-path sampling switch is connected with an analog-to-digital converter controller 511, and the analog-to-digital converter controller 511 controls the multi-path sampling switch to perform multi-path data acquisition.
The multi-path selection switch can support data acquisition of eight paths of signals and multi-mode sampling, wherein the multi-path selection switch comprises single sampling and configurable multi-path sampling, and can set sampling intervals and the period of each sampling.
In one embodiment, the AHB bus matrix 400 includes a master arbiter 410, an address and control selector 420, a write data selector 430, a read data selector 440, and a slave decoder 450450. The address and control selector 420 is electrically connected to the master arbiter 410, the write data selector 430 is electrically connected to the master arbiter 410, and the read data selector 440 is electrically connected to the slave decoder 450.
In one embodiment, the analog-to-digital converter controller 511 includes an analog-to-digital converter controller host 811 and an analog-to-digital converter controller slave 812. The fault algorithm determiner 516 includes a fault algorithm determining master 821 and a fault algorithm determining slave 822. The analog-to-digital converter controller host 811 is electrically connected with the address and control selector 420 and the write data selector 430, the fault algorithm decision host 821 is electrically connected with the address and control selector 420 and the write data selector 430, the analog-to-digital converter controller host 811 is connected with the fault algorithm decision host 821 and then commonly connected with the read data selector 440, the analog-to-digital converter controller slave 812 is electrically connected with the read selector 440, the fault algorithm decision slave 822 is electrically connected with the read data selector 440, the analog-to-digital converter controller slave 812 is connected with the fault algorithm decision slave 822 and then commonly connected with the address and control selector 420, and the analog-to-digital converter controller slave 812 is connected with the fault algorithm decision slave 822 and then commonly connected with the write data selector 430.
In the AHB bus protocol design, a central multiplexing switch interconnect scheme is used. In this scheme all hosts (including the adc controller host 811 and the fault algorithm decision host 821) output address and control signals indicating the transmissions they are to perform, while the host arbiter 410 decides that a certain host can communicate its address and control signals to all slaves (including the adc controller slave 812 and the fault algorithm decision slave 822). The slave decoder 450 controls the reading of data and responds to the signal selector which selects the signal from the slave included in the transmission. The address and control selector 420 generates an address map between the master and slave devices.
The slave decoder 450 controls the read data selector 440 to select multiple signals and read data from corresponding slaves, the master arbiter 410 controls the write data selector 430 and determines that a certain host can write data to the corresponding slaves, the address and control selector 420 generates an address map between the master and slave devices, and the output address and control signals of each host determine the transmission to be performed by them, and the master arbiter 410 cooperates to realize communication with the corresponding slaves.
In one embodiment, the low-speed peripheral 530 includes a peripheral bus 531, a pulse width modulator 537, a watchdog 536, a timer 535, a universal asynchronous receiver transmitter serial port 532, a serial peripheral interface 533, and a universal I/O port 534. The peripheral bus 531 is connected to the AHB2APB bridge 520. The pulse width modulator 537 is coupled to the AHB2APB bridge 520 via the peripheral bus 531. The watchdog 536 is coupled to the AHB2APB bridge 520 via the peripheral bus 531. The timer 535 is connected to the AHB2APB bridge 520 via the peripheral bus 531. The UART serial 532 is connected to the AHB2APB bridge 520 through the peripheral bus 531. The serial peripheral interface 533 is coupled to the AHB2APB bridge 520 via the peripheral bus 531. The general purpose I/O port 534 is connected to the AHB2APB bridge 520 through the peripheral bus 531.
In one embodiment, the reduced instruction set architecture 100 comprises a single-issue five-stage pipeline architecture.
The single-issue five-stage pipeline architecture includes fetch, decode, execute, access, and write-back. Meanwhile, the system has complete instruction cache and data cache, comprises 64-depth branch target caches, 256-depth branch history tables, 2-depth return address stacks, a memory management unit, a hardware Floating Point Unit (FPU) and the like, and has the advantages that the performance is greatly improved under the same process as that of the existing ARM Cortex-A5, and the area and the power consumption are smaller.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (9)
1. A system-on-a-chip architecture, comprising:
a bus architecture;
an open source instruction set architecture based on a reduced instruction set principle, connected to the bus architecture;
a memory connected to the bus architecture;
an AHB bus matrix connected with the memory; and
the peripheral module is electrically connected with the AHB bus matrix;
the bus architecture comprises an instruction bus, a data bus and a system bus, wherein the memory comprises an on-chip static random access memory, a read-only memory and/or an on-chip flash memory, the open source instruction set architecture based on the principle of a reduced instruction set is electrically connected with the read-only memory and/or the on-chip flash memory through the instruction bus, the open source instruction set architecture based on the principle of the reduced instruction set is electrically connected with the on-chip static random access memory through the data bus, and the open source instruction set architecture based on the principle of the reduced instruction set is electrically connected with the AHB bus matrix through the system bus.
2. The system-on-chip architecture of claim 1, comprising:
the debugging component is connected with the open source instruction set architecture based on the reduced instruction set principle and is used for debugging the system-on-chip architecture;
and the clock control module is connected with the open source instruction set architecture based on the reduced instruction set principle and used for controlling the working clock of the system-on-chip architecture.
3. The system-on-chip architecture of claim 1, wherein the peripheral module comprises a high-speed peripheral, an AHB2APB bridge, and a low-speed peripheral, the AHB bus matrix being electrically connected to the high-speed peripheral and the AHB2APB bridge, respectively, the AHB2APB bridge being electrically connected to the low-speed peripheral.
4. The system-on-chip architecture of claim 3, wherein the high-speed peripheral comprises:
the phase-locked loop controller is connected with the AHB bus matrix and the phase-locked loop module and used for controlling the register configuration of the phase-locked loop module;
the analog-to-digital converter controller is connected with the AHB bus matrix and the sampling switch at the front end of the analog-to-digital converter and is used for controlling the sampling switch at the front end of the analog-to-digital converter to sample data;
the fault algorithm decision device is connected with the AHB bus matrix and is used for checking and/or early warning the fault of the power grid system according to the sampling data of the sampling front end of the analog-to-digital converter;
and the independent static random access memory is connected with the AHB bus matrix and used for storing data, including the data sampled by the analog-to-digital converter and the data processed by the fault algorithm decision device.
5. The system-on-chip architecture of claim 4, wherein the analog-to-digital converter front-end sampling switch comprises a multi-way sampling switch, the multi-way sampling switch being coupled to an analog-to-digital converter controller, the analog-to-digital converter controller controlling the multi-way sampling switch to perform multi-way data acquisition.
6. The system-on-chip architecture of claim 5, wherein the AHB bus matrix comprises a host arbiter, an address and control selector, a write data selector, a read data selector, and a slave decoder, the address and control selector being electrically connected to the host arbiter, the write data selector being electrically connected to the host arbiter, the read data selector being electrically connected to the slave decoder.
7. The system-on-chip architecture of claim 6, wherein the analog-to-digital converter controller comprises an analog-to-digital converter controller host and an analog-to-digital converter controller slave, the fault algorithm determiner comprises a fault algorithm determination host and a fault algorithm determination slave, the analog-to-digital converter controller host is electrically connected to the address and control selector and the write data selector, respectively, the fault algorithm determination host is electrically connected to the address and control selector and the write data selector, respectively, the analog-to-digital converter controller host is electrically connected to the fault algorithm determination host and is then commonly electrically connected to the read data selector, the analog-to-digital converter controller slave is electrically connected to the read data selector, the fault algorithm determination slave is then commonly connected to the fault algorithm determination slave, and is then commonly connected to the address and control selector.
8. The system-on-chip architecture of claim 7, wherein the low-speed peripheral comprises,
a peripheral bus connected with the AHB2APB bridge;
the pulse width modulator is connected with the AHB2APB bridge through the peripheral bus;
a watchdog connected to the AHB2APB bridge through the peripheral bus;
the timer is connected with the AHB2APB bridge through the peripheral bus;
the universal asynchronous receiving and transmitting transmitter serial port is connected with the AHB2APB bridge through the peripheral bus;
the serial peripheral interface is connected with the AHB2APB bridge through the peripheral bus;
and the universal I/O port is connected with the AHB2APB bridge through the peripheral bus.
9. The system-on-chip architecture of claim 8, wherein the reduced instruction set principle-based open source instruction set architecture comprises a single-issue five-stage pipeline architecture.
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