CN110988931A - Clock self-checking circuit based on AD8310 detector - Google Patents
Clock self-checking circuit based on AD8310 detector Download PDFInfo
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- CN110988931A CN110988931A CN201911055490.4A CN201911055490A CN110988931A CN 110988931 A CN110988931 A CN 110988931A CN 201911055490 A CN201911055490 A CN 201911055490A CN 110988931 A CN110988931 A CN 110988931A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/25—Acquisition or tracking or demodulation of signals transmitted by the system involving aiding data received from a cooperating element, e.g. assisted GPS
- G01S19/256—Acquisition or tracking or demodulation of signals transmitted by the system involving aiding data received from a cooperating element, e.g. assisted GPS relating to timing, e.g. time of week, code phase, timing offset
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/20—Integrity monitoring, fault detection or fault isolation of space segment
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/26—Automatic control of frequency or phase; Synchronisation using energy levels of molecules, atoms, or subatomic particles as a frequency reference
Abstract
A clock self-checking circuit based on an AD8310 detector belongs to the technical field of navigation. The invention integrates a primary power divider, a secondary power divider, an AD8310 wave detector, a voltage comparator, a linear voltage stabilizer and a clock generator into a whole; the switching function of the main clock signal and the standby clock signal is realized; the serial connection use method of the first-stage power divider and the second-stage power divider improves the isolation between the main clock signal and the standby clock signal, and avoids the problem that the standby clock signal cannot be started due to wrong interpretation of the voltage comparator when the main clock signal is closed. The clock self-checking circuit provided by the invention converts the power of the main clock signal into a voltage value by using the logarithmic detector, judges the on-off state of the main clock signal, realizes the control of the enabling signal of the linear voltage stabilizer by using the overvoltage comparator, and can accurately perform self-checking on the main clock signal. The invention has high reliability, light weight, low power consumption and strong practical value.
Description
Technical Field
The invention relates to a clock self-checking circuit based on an AD8310 detector, and belongs to the technical field of navigation.
Background
The clock circuit has important practical application value, such as being used in communication, navigation positioning and numerous application technical fields. With the rapid development of the internet and the synchronization technology, people put higher demands on the accuracy and stability of the communication system clock, and the ultra-high precision clock can be used for improving the synchronization precision of the satellite positioning system. The navigation positioning system can provide navigation and time service for vast users, and the clock source is designed and generated under the background. The requirements of some advanced disciplines such as aerospace, navigation positioning, telecommunication and transportation and the like on time frequency are increasing day by day, and in some fields, even a plurality of clocks are required to jointly complete a time-keeping task. In the navigation positioning system, the accurate measurement of the positioning position actually depends on the accurate measurement of the positioning time, an atomic clock is used as an on-satellite time reference for the distance measurement of the navigation system and is the core part of the payload of the satellite navigation system, and the performance of the atomic clock determines the accuracy of the user navigation positioning. Therefore, the method has important significance for fault detection and backup of the navigation satellite clock. The traditional clock circuit has the advantages of complex structure, slow response and small coverage.
Disclosure of Invention
The technical problem solved by the invention is as follows: the clock self-detection circuit based on the AD8310 detector is provided, and the smooth switching function of the main clock signal and the standby clock signal can be realized. In order to realize the non-blocking crossing of a receiving and transmitting system in satellite-borne communication, a wave detector, a voltage comparator and a linear voltage stabilizer are used for realizing the smooth switching function of a multi-path input clock, and the circuit is stable and reliable in work and good in performance.
The technical solution of the invention is as follows: a clock self-checking circuit based on an AD8310 detector comprises a clock generator, a primary power divider, a secondary power divider, a detector, a voltage comparator and a linear voltage stabilizer;
the primary power divider receives the main clock signal and outputs two paths of main clock signals;
the detector receives the first path of main clock signal, and outputs detection voltage to the voltage comparator after processing;
the voltage comparator receives the detection voltage and outputs an enable signal to the linear voltage stabilizer;
the linear voltage regulator is used for controlling the output clock supply voltage;
the clock generator receives the clock power supply voltage, outputs a standby clock signal, combines the standby clock signal with the second path of main clock signal, sends the standby clock signal and the second path of main clock signal into the second-stage power divider, obtains the combined clock signal, and outputs the combined clock signal to subsequent equipment.
Further, the frequency point of the master clock signal is 62MHz, the frequency point of the standby clock signal is 62MHz, and the frequency point of the combined clock signal is 62 MHz.
Further, the clock generator comprises a clock generator G1, a capacitor C4;
the supply voltage end Vdd of the clock generator G1 is connected to the output end +3.3V of the linear regulator, one GND end of the clock generator G1 is grounded, the signal output end of the clock generator G1 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is used as the output of the clock generator G1.
Further, the primary power divider comprises a power divider circuit D1, an attenuator D5, and a capacitor C1;
the synthesis end of the power divider circuit D1 receives a main clock signal, one GND end of the power divider circuit D1 is grounded, the signal output end RF1 of the power divider circuit D1 is connected with one end of a capacitive attenuator D5, the other end of the attenuator D5 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with the input end of a detector; the other signal output terminal RF2 of the power divider circuit D1 is connected to the signal output terminal RF2 of the secondary power divider.
Further, the secondary power divider comprises a power divider circuit D2;
the combined end of the power divider circuit D2 is connected to the clock signal after combination, one GND end of the power divider circuit D2 is grounded, the signal output end RF1 of the power divider circuit D2 is connected to the standby clock signal, and the signal output end RF2 of the power divider circuit D2 is connected to the signal output end RF2 of the primary power divider.
Further, the detector comprises a detector circuit D3, a resistor R2, a capacitor C2;
the input end of the detector circuit D3 is connected with the other end of the capacitor C1, and the power supply end of the detector circuit D3 is connected with +5V voltage; the other input end of the detector circuit D3 is connected with one end of a capacitor C2, and the other end of C2 is grounded; the output end of the detector circuit D3 is connected with one end of a resistor R2, and the other end of the resistor R2 is connected with a voltage comparator.
Further, the voltage comparator includes a voltage comparator circuit D4, a resistor R3, a resistor R4, and a resistor R5;
the power supply end of the voltage comparator circuit D4 is connected with +3.3V voltage; the input end of the voltage comparator circuit D4 is connected with the other end of the resistor R2; the differential input end of the voltage comparator circuit is connected with one ends of a resistor R3 and a resistor R4, the other end of the resistor R3 is grounded, and the other end of the resistor R4 is connected with + 3.3V; the output terminal of the voltage comparator circuit D4 is connected to one terminal of the resistor R5, and the other terminal of R5 outputs an enable signal.
Further, the voltage regulator D6 includes a voltage regulator circuit D6, a resistor R6, a capacitor C3;
the enable end of the voltage stabilizer circuit D6 is connected with an enable signal and one end of a resistor R6, and the other end of the resistor R6 is connected with the voltage + 5V; the input end of the voltage stabilizer circuit D6 is connected with the voltage +5V, the shunt end of the voltage stabilizer circuit D6 is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded; the output terminal of the voltage regulator circuit D6 outputs + 3.3V.
Furthermore, the first-stage power divider and the second-stage power divider are both ADP-2-1W + and have the isolation of 39dB @62 MHZ.
Further, the detector circuit D3 is an AD8310 detector, the voltage comparator circuit D4 is a MAX961ESA voltage comparator, and the voltage regulator circuit D6 is a MIC5323-3.3YD5 voltage regulator.
Compared with the prior art, the invention has the advantages that:
(1) the present invention can demodulate the frequency range from DC to 440 MHZ. The driving current of the grounding load can reach 25mA within 15ns, and the power consumption is extremely low. The AD8310 detector uses advanced compression techniques with a dynamic range of up to 95dB and an error of only +/-3 dB. The device has stable performance and is easy to use, and other important devices are not needed outside. The device integrates the advantages of low cost, small volume, low power consumption, high precision, high stability, wide dynamic range and the like, and the frequency range of the device can be from audio frequency to ultrahigh frequency. In addition, the circuit has the characteristics of quick response time, strong load driving capability and the like, and can be widely applied to circuits needing to attenuate signals to decibel level. The AD8310 detector is used in the industrial temperature range of-40 ℃ to +85 ℃. A logarithmic amplifier refers to an amplifying circuit in which the amplitude of an output signal is logarithmically related to the amplitude of an input signal. Mainly converting a signal into its equivalent logarithmic value involves a non-linear operation.
(2) The comparator chip MAX961 and the ultra-high-speed and ultra-swing comparator consume 350uA of power, the typical value of transmission delay reaches 4.5ns, the rise time is 2.3ns, and the fast response time of the circuit can be ensured.
(3) The single-point positioning is carried out by using a standby clock signal, and the precision is ten meters according to the requirement of a common receiver.
(4) And the orbit is determined by using a main clock signal, so that the precision reaches the decimeter level and the navigation precision is enhanced.
(5) The invention integrates each module in the navigation enhancement system, and powers on the GNSS receiving module in a normal mode, and the invention uses the standby clock signal to carry out single-point positioning; in the continuous test mode, the time frequency module works, and the invention uses the main clock signal to carry out orbit determination.
(6) The invention realizes the function of generating a low enable signal to close the standby clock signal when the main clock signal enters.
(7) The invention realizes the function that the circuit generates high enable signal to start the standby clock signal when the main clock signal is closed.
(8) The invention realizes the function that the clock signal power after the main clock signal is combined at the power of 8dBm conforms to the clock range of the navigation enhancement system.
(9) The invention realizes the function that the power of the clock signal after combination accords with the clock range of the navigation enhancement system when the main clock signal is closed.
Drawings
FIG. 1 is a block diagram of the circuit of the present invention;
FIG. 2 is a graph of the output level value of the detection circuit in relation to the amplitude of the input signal in accordance with the present invention;
fig. 3 is a detailed functional block diagram of the present invention.
Detailed Description
The invention is further explained and illustrated in the following figures and detailed description of the specification.
Referring to fig. 1, a clock self-checking circuit based on an AD8310 detector includes a clock generator, a primary power divider, a secondary power divider, a detector, a voltage comparator, and a linear regulator;
the primary power divider receives the main clock signal and outputs two paths of main clock signals;
the detector receives the first path of main clock signal, and outputs detection voltage to the voltage comparator after processing;
the voltage comparator receives the detection voltage and outputs an enable signal to the linear voltage stabilizer;
the linear voltage regulator is used for controlling the output clock supply voltage;
the clock generator receives the clock power supply voltage, outputs a standby clock signal, combines the standby clock signal with the second path of main clock signal, sends the standby clock signal and the second path of main clock signal into the second-stage power divider, obtains the combined clock signal, and outputs the combined clock signal to subsequent equipment.
Preferably, the frequency point of the master clock signal is 62MHz, the frequency point of the slave clock signal is 62MHz, and the frequency point of the combined clock signal is 62 MHz.
Preferably, as shown in fig. 3, the clock generator comprises a clock generator G1, a capacitor C4;
the power supply voltage end Vdd of the clock generator G1 is connected with the OUTPUT +3.3V _ OCXO of the linear voltage regulator (D6), one GND end of the clock generator G1 is grounded, the signal OUTPUT end OUTPUT of the clock generator G1 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is used as the OUTPUT of the clock generator G1.
Preferably, as shown in fig. 3, the primary power divider includes a power divider circuit D1, an attenuator D5, and a capacitor C1;
the synthesis end (SUM end) of the power divider circuit D1 is connected with a main clock signal (62MHZ _ W), one GND end of the power divider circuit D1 is grounded, the signal output end RF1 of the power divider circuit D1 is connected with one end of a capacitive attenuator D5, the other end of the attenuator D5 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with the input end of an AD8310 detector (D3); the other signal output terminal RF2 of the power divider circuit D1 is connected to the signal output terminal RF2 of the secondary power divider.
Preferably, as shown in fig. 3, the two-stage power divider includes a power divider circuit D2; the synthesis end (SUM end) of the power divider circuit D2 is connected to the clock signal (62MHZ _ OUT) after combination, one GND end of the power divider circuit D2 is grounded, the signal output end RF1 of the power divider circuit D2 is connected to the standby clock signal (62MHZ _ OCXO), and the signal output end RF2 of the power divider circuit D2 is connected to the signal output end RF2 of the primary power divider.
Preferably, as shown in fig. 3, the detector D3 includes an AD8310 detector D3, a resistor R2, a capacitor C2;
the input end of the AD8310 detector D3 is connected with the other end of the capacitor C1, the power supply end of the AD8310 detector D3 is connected with +5V voltage, and the voltage is circuit power supply voltage; the pin of the ground end 2 is connected with the whole board ground; the other input end of the D3 is connected with one end of the capacitor C2, and the other end of the C2 is grounded; the output end of the D3 is connected with one end of a resistor R2;
preferably, as shown in fig. 3, the voltage comparator D4 includes a voltage comparator circuit D4, resistors R3, R4, R5;
the power supply end of the voltage comparator circuit D4 is connected with +3.3V voltage which is the circuit power supply voltage; the input end of the voltage comparator circuit D4 is connected with the other end of the resistor R2; the differential input end is connected with one ends of a resistor R3 and a resistor R4, the other end of the resistor R3 is grounded, the other end of the resistor R4 is connected with +3.3V, and the voltage is circuit supply voltage; the output end of the voltage comparator circuit D4 is connected with one end of the resistor R5, and the other end of the resistor R5 outputs a clock enable signal 62MHZ _ EN;
preferably, as shown in fig. 3, the voltage regulator D6 includes a voltage regulator circuit D6, a resistor R6, a capacitor C3;
the enable end of the voltage stabilizer circuit D6 is connected with an enable signal 62MHZ _ EN and one end of a resistor R6, the other end of the resistor R6 is connected with a voltage +5V, the voltage is +5V connected with the input end of a circuit power supply voltage stabilizer circuit D6, the shunt end is connected with one end of a capacitor C3, and the other end of the capacitor C3 is grounded; the output end outputs a voltage +3.3V _ OXCO;
as shown in FIG. 2, the amplitude of the main clock signal (62MHZ _ W) is +8dBm, the main clock signal is attenuated to +5dBm after passing through the power divider circuit D1, the attenuator D5 is attenuated by 6dB, the main clock signal (62MHZ _ W) is reduced to-1 dBm, the main clock signal is converted to-14 dBV, and the corresponding detector outputs 2.3V;
after the voltage is input into the voltage comparator, the comparison voltage of the voltage comparator is set to be 1.5V, the input of the voltage comparator is low level when the voltage is less than 1.25V, the input of the voltage comparator is high level when the voltage is more than 2.05V, the low level is 0.52V, and the high level is 2.78V, so when the main clock signal (62MHZ _ W) is generated, the voltage comparator outputs low enabling voltage to the linear voltage stabilizer D6;
the high enabling voltage value of the linear voltage stabilizer is more than 1.2V, the low enabling voltage value is less than 0.2V,
in order to avoid interpretation errors, the two-stage power divider circuit D1 and the power divider circuit D2 are both used with ADP-2-1W (+), the isolation degree is 39dB @62MHZ, the amplitude of the standby clock signal 62MHZ _ OCXO is 10dBm, after the two-stage power divider circuit D1 and the power divider circuit D2 are isolated, the amplitude of the entrance of the detector is-74 dBm and is converted into-87 dBV, as shown in FIG. 2, the output level is far less than the interpretation level of the voltage comparator by 1.5V, so that the output of the voltage comparator is still a high enabling voltage signal, and interpretation errors are avoided.
Preferably, the first-stage power divider and the second-stage power divider are both ADP-2-1W + and have the isolation of 39dB @62 MHZ. The detector circuit D3 is an AD8310 detector, the voltage comparator circuit D4 is a MAX961ESA voltage comparator, and the voltage regulator circuit D6 is a MIC5323-3.3YD5 voltage regulator.
The working principle of the invention is as follows:
the main clock signal (62MHZ _ W) passes through the first-stage power divider, outputs the combined clock signal, and sends the combined clock signal to the detector, as can be seen from fig. 3, the detector outputs a detection voltage according to the amplitude of the combined clock signal, the output detection voltage changes linearly with the input end, i.e., the power of the combined clock signal, and the typical value is that when the power of the combined clock signal is-78 dBm, the output detection voltage is 0.4V; when the power of the clock signal after combination is 22dBm, the output detection voltage is 2.6V, the detection voltage is sent to a voltage comparator to output an enabling signal, the enabling signal is sent to a linear voltage stabilizer to control the output of the linear voltage stabilizer, when the enabling signal is at a high level, the linear voltage stabilizer outputs a clock supply voltage of 3.3V, when the enabling signal is at a low level, the linear voltage stabilizer outputs a clock supply voltage of 0V, when the clock supply voltage is sent to a clock generator, the output of the clock generator can be controlled, and when the clock supply voltage is 3.3V, the clock generator outputs a standby clock signal of 62 MHZ; when the clock supply voltage is 0V, the clock generator has no output. After passing through the primary power divider and the secondary power divider, the main clock signal is combined with the standby clock signal to output a combined clock signal.
The performance characteristics of the master clock signal are as follows:
output frequency: 62 MHz;
output amplitude: not less than 6 dBm;
frequency accuracy: less than or equal to 5 multiplied by 10 < -12 >;
short-term frequency instability: less than or equal to 2 multiplied by 10-10/1 s;
phase noise: less than or equal to-70 dBc/Hz @10 Hz;
≤-100dBc/Hz@100Hz；
≤-105dBc/Hz@1kHz；
the invention can realize the smooth switching function of the main clock signal and the standby clock signal. In order to realize non-blocking crossing of a transmitting and receiving system in satellite-borne communication, a clock self-checking circuit design based on an AD8310 detector is provided. The system uses a wave detector, a voltage comparator and a linear voltage stabilizer to realize the smooth switching function of a plurality of paths of input clocks, and the circuit has stable and reliable work and good performance.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (10)
1. A clock self-checking circuit based on an AD8310 detector is characterized in that: the power divider comprises a clock generator, a primary power divider, a secondary power divider, a detector, a voltage comparator and a linear voltage stabilizer;
the primary power divider receives the main clock signal and outputs two paths of main clock signals;
the detector receives the first path of main clock signal, and outputs detection voltage to the voltage comparator after processing;
the voltage comparator receives the detection voltage and outputs an enable signal to the linear voltage stabilizer;
the linear voltage regulator is used for controlling the output clock supply voltage;
the clock generator receives the clock power supply voltage, outputs a standby clock signal, combines the standby clock signal with the second path of main clock signal, sends the standby clock signal and the second path of main clock signal into the second-stage power divider, obtains the combined clock signal, and outputs the combined clock signal to subsequent equipment.
2. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the frequency point of the main clock signal is 62MHz, the frequency point of the standby clock signal is 62MHz, and the frequency point of the combined clock signal is 62 MHz.
3. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the clock generator comprises a clock generator G1 and a capacitor C4;
the supply voltage end Vdd of the clock generator G1 is connected to the output end +3.3V of the linear regulator, one GND end of the clock generator G1 is grounded, the signal output end of the clock generator G1 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is used as the output of the clock generator G1.
4. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the primary power divider comprises a power divider circuit D1, an attenuator D5 and a capacitor C1;
the synthesis end of the power divider circuit D1 receives a main clock signal, one GND end of the power divider circuit D1 is grounded, the signal output end RF1 of the power divider circuit D1 is connected with one end of a capacitive attenuator D5, the other end of the attenuator D5 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with the input end of a detector; the other signal output terminal RF2 of the power divider circuit D1 is connected to the signal output terminal RF2 of the secondary power divider.
5. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the secondary power divider comprises a power divider circuit D2;
the combined end of the power divider circuit D2 is connected to the clock signal after combination, one GND end of the power divider circuit D2 is grounded, the signal output end RF1 of the power divider circuit D2 is connected to the standby clock signal, and the signal output end RF2 of the power divider circuit D2 is connected to the signal output end RF2 of the primary power divider.
6. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the detector comprises a detector circuit D3, a resistor R2 and a capacitor C2;
the input end of the detector circuit D3 is connected with the other end of the capacitor C1, and the power supply end of the detector circuit D3 is connected with +5V voltage; the other input end of the detector circuit D3 is connected with one end of a capacitor C2, and the other end of C2 is grounded; the output end of the detector circuit D3 is connected with one end of a resistor R2, and the other end of the resistor R2 is connected with a voltage comparator.
7. The AD8310 detector-based clock self-test circuit of claim 6, wherein: the voltage comparator comprises a voltage comparator circuit D4, a resistor R3, a resistor R4 and a resistor R5;
the power supply end of the voltage comparator circuit D4 is connected with +3.3V voltage; the input end of the voltage comparator circuit D4 is connected with the other end of the resistor R2; the differential input end of the voltage comparator circuit is connected with one ends of a resistor R3 and a resistor R4, the other end of the resistor R3 is grounded, and the other end of the resistor R4 is connected with + 3.3V; the output terminal of the voltage comparator circuit D4 is connected to one terminal of the resistor R5, and the other terminal of R5 outputs an enable signal.
8. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the voltage stabilizer D6 comprises a voltage stabilizer circuit D6, a resistor R6 and a capacitor C3;
the enable end of the voltage stabilizer circuit D6 is connected with an enable signal and one end of a resistor R6, and the other end of the resistor R6 is connected with the voltage + 5V; the input end of the voltage stabilizer circuit D6 is connected with the voltage +5V, the shunt end of the voltage stabilizer circuit D6 is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded; the output terminal of the voltage regulator circuit D6 outputs + 3.3V.
9. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the first-stage power divider and the second-stage power divider are both ADP-2-1W + and have the isolation of 39dB @62 MHZ.
10. The AD8310 detector-based clock self-detection circuit of claim 1, wherein: the detector circuit D3 is an AD8310 detector, the voltage comparator circuit D4 is a MAX961ESA voltage comparator, and the voltage regulator circuit D6 is a MIC5323-3.3YD5 voltage regulator.
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