CN204967792U - High frequency over --horizon radar clock source produces circuit - Google Patents
High frequency over --horizon radar clock source produces circuit Download PDFInfo
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- CN204967792U CN204967792U CN201520782901.0U CN201520782901U CN204967792U CN 204967792 U CN204967792 U CN 204967792U CN 201520782901 U CN201520782901 U CN 201520782901U CN 204967792 U CN204967792 U CN 204967792U
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Abstract
The utility model discloses a high frequency over - -horizon radar clock source produces circuit includes in proper order that crystal oscillator, a low -noise amplifier, central frequency are f1's first narrowband band pass filter, the 2nd low -noise amplifier, a power distribution unit, later are divided into two the tunnel: the clock signal 1 branch road includes in proper order that central frequency is f1's second narrowband band pass filter, the controllable amplifier circuit of first gain and the first clock drive circuit, the clock signal 2 branch road includes in proper order that the 3rd low -noise amplifier, central frequency are f2's narrowband band pass filter, the second controllable amplifier circuit of gain and the 2nd clock driver circuit, still include control circuit, the controllable amplifier circuit of first gain, the controllable amplifier circuit of second gain, the first clock drive circuit and second clock drive circuit all are connected with control circuit. The utility model discloses it is simple to possess circuit structure, controls nimble characteristics of going with scalability, can produce high stability, low phase noise's clock signal, satisfies the in -service use demand.
Description
Technical field
The utility model relates to high frequency over the horizon radar technical field, particularly relates to a kind of high frequency over the horizon radar clock source generating circuit.
Background technology
High frequency over the horizon radar clock source is generally produced through frequency multiplication of phase locked loop circuit by high stability, low phase noise crystal oscillator or is produced through simulation frequency multiplier circuit.The phase noise of the clock signal phase noise ratio simulation frequency multiplier circuit that frequency multiplication of phase locked loop circuit exports is large, existing simulation frequency multiplier circuit many employings analogue device carries out the clockings such as amplification filtering, but analogue device long-time running easily produces the problems such as aging, whole circuit gain may be caused to decline, amplitude output signal diminishes, sometimes even can not clock signal, cause system cisco unity malfunction.
Utility model content
For the problems referred to above, the purpose of this utility model is to provide a kind of high frequency over the horizon radar clock source generating circuit, prior art Problems existing can be solved, there is circuit structure simple, control flexible and that extensibility is good feature, the clock signal of high stability, low phase noise can be produced, meet actual user demand.
For achieving the above object, the utility model takes following technical scheme:
A kind of high frequency over the horizon radar clock source generating circuit, comprise the crystal oscillator with high stability, low phase noise successively, first low noise amplifier, centre frequency is first narrow band filter of f1, second low noise amplifier, first power divider, is divided into two-way afterwards: the branch road for generation of clock signal 1 comprises the second narrow band filter, the first gain controllable amplifying circuit and the first clock driver circuit that centre frequency is f1 successively; The narrow band filter that branch road for generation of clock signal 2 comprises the 3rd low noise amplifier successively, centre frequency is f2, the second gain controllable amplifying circuit and second clock drive circuit; Also comprise control circuit, described first gain controllable amplifying circuit, the second gain controllable amplifying circuit, the first clock driver circuit and second clock drive circuit are all connected with control circuit.
Wherein, described control circuit comprises monitoring clock signal part and gain control section;
Described first clock driver circuit and second clock drive circuit can produce multipath clock signal, a wherein road clock signal incoming clock signal monitoring part, can Real-Time Monitoring clock signal state, and by the information feed back of monitoring clock signal state to gain control section, gain control section adjusts the gain of the first gain controllable amplifying circuit and the second gain controllable amplifying circuit according to feedback information, to ensure the stability that clock exports and adjustment duty ratio.
Wherein, if desired clock signal 3 is then add second power divider after the narrow band filter of f2 to be divided into two-way, a road clocking 2, another road clocking 3 in centre frequency; Circuit for generation of clock signal 3 comprises the 4th low noise amplifier successively and amplifies, and then accessing centre frequency is the narrow band filter of f3, then through the 3rd gain controllable amplifying circuit, finally accesses the 3rd clock driver circuit;
Described 3rd gain controllable amplifying circuit, the 3rd clock driver circuit are all connected with control circuit.
Wherein, described crystal oscillator output frequency is the reference clock signal of f0, and the frequency of the clock signal 1 finally exported, clock signal 2 and clock signal 3 is respectively f1, f2 and f3, and three is the integral multiple of f0.
Wherein, be not less than 20dB for the gain carrying out the crystal oscillator clock source signal of the high stability of input, low phase noise to be amplified to saturated described first low noise amplifier, noise factor is not more than 2dB.
Wherein, the second narrow band filter that centre frequency is first narrow band filter of f1, centre frequency is f1 and centre frequency are that the bandwidth of the narrow band filter of f2 is all not more than 5% of respective centre frequency, leach with the clock signal being f1 and f2 by required frequency, and inhibition zone external signal.
The utility model is owing to taking above technical scheme, and it has the following advantages:
1, circuit structure is simple, is easy to realize, and control flexibly, extensibility is strong, and clock signal quality meets practical application request;
2, control circuit can export by Real-Time Monitoring clock, if without clock signal output, system, by regulating the gain of gain controllable amplifying circuit, ensures that clock driver circuit input signal amplitude meets the demands because extraneous factor causes system gain not;
3, clock output signal stability is high, and phase noise is low.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of a kind of high frequency over the horizon radar clock source generating circuit that the utility model specific embodiment provides.
In figure:
1-crystal oscillator, the 2-the first low noise amplifier, 3-centre frequency is first narrow band filter of f1,4-the second low noise amplifier, 5-the first power divider, 6-centre frequency is second narrow band filter of f1, the 7-the first gain controllable amplifying circuit, 8-the first clock driver circuit, 9-the three low noise amplifier, 10-centre frequency is the narrow band filter of f2, the 11-the second gain controllable amplifying circuit, 12-second clock drive circuit, 13-control circuit.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in detail.
Fig. 1 is the structured flowchart of a kind of high frequency over the horizon radar clock source generating circuit that the utility model specific embodiment provides.As shown in Figure 1, a kind of high frequency over the horizon radar clock source generating circuit described in the utility model, comprise the crystal oscillator 1 with high stability, low phase noise successively, first low noise amplifier 2, centre frequency is first narrow band filter 3 of f1, second low noise amplifier 4, first power divider 5, is divided into two-way afterwards: the branch road for generation of clock signal 1 comprises the second narrow band filter 6, first gain controllable amplifying circuit 7 and the first clock driver circuit 8 that centre frequency is f1 successively; Narrow band filter 10, the second gain controllable amplifying circuit 11 that branch road for generation of clock signal 2 comprises the 3rd low noise amplifier 9 successively, centre frequency is f2 and second clock drive circuit 12; Also comprise control circuit 13, described first gain controllable amplifying circuit 7, second gain controllable amplifying circuit 11, first clock driver circuit 8 and second clock drive circuit 12 are all connected with control circuit 13.
It is simple that clock source generating circuit described in the utility model has circuit structure, controls flexible and that extensibility is good feature, can produce the clock signal of high stability, low phase noise, meet actual user demand.
Below the course of work of the utility model circuit is described as follows:
Crystal oscillator 1 clock source signals of the high stability of input, low phase noise is carried out being amplified to saturated by the first low noise amplifier 2; The clock signal of centre frequency to be first narrow band filter 3 of f1 by required frequency be f1 leaches, amplify by the second low noise amplifier 4, two-way is divided into: a road access centre frequency is amplify through the first gain controllable amplifying circuit 7, finally by the first clock driver circuit 8 clock signal 1 after second narrow band filter 6 filtering of f1 after accessing the first power divider 5; Another road access the 3rd low noise amplifier 9 amplifies, and amplifies, finally by second clock drive circuit 12 clock signal 2 after narrow band filter 10 filtering that centre frequency is f2 through the second gain controllable amplifying circuit 11.
In FIG, the first gain controllable amplifying circuit 7 and the second gain controllable amplifying circuit 11 can regulate gain according to feedback information.Described control circuit 13 comprises monitoring clock signal part and gain control section.Described first clock driver circuit 8 and second clock drive circuit 12 can produce multipath clock signal, a wherein road clock signal incoming clock signal monitoring part, can Real-Time Monitoring clock signal state, and by the information feed back of monitoring clock signal state to gain control section, gain control section adjusts the gain of the first gain controllable amplifying circuit 7 and the second gain controllable amplifying circuit 11 according to feedback information, to ensure the stability that clock exports and adjustment duty ratio.
In actual applications, if desired clock signal 3 is then add second power divider after the narrow band filter 10 of f2 to be divided into two-way, a road clocking 2, another road clocking 3 in centre frequency; Circuit for generation of clock signal 3 comprises the 4th low noise amplifier successively and amplifies, and then accessing centre frequency is the narrow band filter of f3, then through the 3rd gain controllable amplifying circuit, finally accesses the 3rd clock driver circuit; Described 3rd gain controllable amplifying circuit, the 3rd clock driver circuit are all connected with control circuit 13.
In FIG, described crystal oscillator 1 output frequency is the reference clock signal of f0, and the frequency of the clock signal 1 finally exported, clock signal 2 and clock signal 3 is respectively f1, f2 and f3, and three is the integral multiple of f0.
In FIG, be not less than 20dB for the gain carrying out crystal oscillator 1 clock source signals of the high stability of input, low phase noise to be amplified to saturated described first low noise amplifier 2, noise factor is not more than 2dB.
In FIG centre frequency be f1 first narrow band filter 3, the narrow band filter 10 of centre frequency to be second narrow band filter 6 of f1 and centre frequency the be f2 filter that should as far as possible select bandwidth less, ensure to leach required frequency signal and inhibition zone external signal.In the present embodiment, the second narrow band filter 6 that centre frequency is first narrow band filter 3 of f1, centre frequency is f1 and centre frequency are that the bandwidth of the narrow band filter 10 of f2 is all not more than 5% of respective centre frequency, leach with the clock signal being f1 and f2 by required frequency, and inhibition zone external signal.
Specific embodiment described herein is only to the utility model explanation for example.The utility model person of ordinary skill in the field can make various amendment or supplements or adopt similar mode to substitute to described specific embodiment, but can't depart from spirit of the present utility model or surmount the scope that appended claims defines.
Claims (6)
1. a high frequency over the horizon radar clock source generating circuit, it is characterized in that, comprise the crystal oscillator with high stability, low phase noise successively, first low noise amplifier, centre frequency is first narrow band filter of f1, second low noise amplifier, the first power divider, is divided into two-way afterwards: the branch road for generation of clock signal 1 comprises the second narrow band filter, the first gain controllable amplifying circuit and the first clock driver circuit that centre frequency is f1 successively; The narrow band filter that branch road for generation of clock signal 2 comprises the 3rd low noise amplifier successively, centre frequency is f2, the second gain controllable amplifying circuit and second clock drive circuit; Also comprise control circuit, described first gain controllable amplifying circuit, the second gain controllable amplifying circuit, the first clock driver circuit and second clock drive circuit are all connected with control circuit.
2. a kind of high frequency over the horizon radar clock source generating circuit according to claim 1, it is characterized in that, described control circuit comprises monitoring clock signal part and gain control section;
Described first clock driver circuit and second clock drive circuit can produce multipath clock signal, a wherein road clock signal incoming clock signal monitoring part, can Real-Time Monitoring clock signal state, and by the information feed back of monitoring clock signal state to gain control section, gain control section adjusts the gain of the first gain controllable amplifying circuit and the second gain controllable amplifying circuit according to feedback information, to ensure the stability that clock exports and adjustment duty ratio.
3. a kind of high frequency over the horizon radar clock source generating circuit according to claim 1 and 2, it is characterized in that, if desired clock signal 3, be then add second power divider after the narrow band filter of f2 to be divided into two-way in centre frequency, one road clocking 2, another road clocking 3; Circuit for generation of clock signal 3 comprises the 4th low noise amplifier successively and amplifies, and then accessing centre frequency is the narrow band filter of f3, then through the 3rd gain controllable amplifying circuit, finally accesses the 3rd clock driver circuit;
Described 3rd gain controllable amplifying circuit, the 3rd clock driver circuit are all connected with control circuit.
4. a kind of high frequency over the horizon radar clock source generating circuit according to claim 3, it is characterized in that, described crystal oscillator output frequency is the reference clock signal of f0, the frequency of the clock signal 1 finally exported, clock signal 2 and clock signal 3 is respectively f1, f2 and f3, three is the integral multiple of f0.
5. a kind of high frequency over the horizon radar clock source generating circuit according to claim 1, it is characterized in that, gain for carrying out the crystal oscillator clock source signal of the high stability of input, low phase noise to be amplified to saturated described first low noise amplifier is not less than 20dB, and noise factor is not more than 2dB.
6. a kind of high frequency over the horizon radar clock source generating circuit according to claim 1, it is characterized in that, the second narrow band filter that centre frequency is first narrow band filter of f1, centre frequency is f1 and centre frequency are that the bandwidth of the narrow band filter of f2 is all not more than 5% of respective centre frequency, leach with the clock signal being f1 and f2 by required frequency, and inhibition zone external signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520782901.0U CN204967792U (en) | 2015-10-10 | 2015-10-10 | High frequency over --horizon radar clock source produces circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520782901.0U CN204967792U (en) | 2015-10-10 | 2015-10-10 | High frequency over --horizon radar clock source produces circuit |
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| Publication Number | Publication Date |
|---|---|
| CN204967792U true CN204967792U (en) | 2016-01-13 |
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| CN201520782901.0U Expired - Fee Related CN204967792U (en) | 2015-10-10 | 2015-10-10 | High frequency over --horizon radar clock source produces circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110988931A (en) * | 2019-10-31 | 2020-04-10 | 北京遥测技术研究所 | Clock self-checking circuit based on AD8310 detector |
-
2015
- 2015-10-10 CN CN201520782901.0U patent/CN204967792U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110988931A (en) * | 2019-10-31 | 2020-04-10 | 北京遥测技术研究所 | Clock self-checking circuit based on AD8310 detector |
| CN110988931B (en) * | 2019-10-31 | 2022-03-04 | 北京遥测技术研究所 | Clock self-checking circuit based on AD8310 detector |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160113 Termination date: 20191010 |
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| CF01 | Termination of patent right due to non-payment of annual fee |