CN110983289B - Method for preparing passivation contact structure based on LPCVD secondary ion implantation - Google Patents

Method for preparing passivation contact structure based on LPCVD secondary ion implantation Download PDF

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CN110983289B
CN110983289B CN201911225719.4A CN201911225719A CN110983289B CN 110983289 B CN110983289 B CN 110983289B CN 201911225719 A CN201911225719 A CN 201911225719A CN 110983289 B CN110983289 B CN 110983289B
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type silicon
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林建伟
陈嘉
崔义乾
乔振聪
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Jiangsu Jietai Photoelectric Technology Co ltd
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Abstract

The method for preparing the passivation contact structure based on LPCVD secondary ion implantation can well solve the problem of preparing a heavily doped polysilicon layer by a tubular LPCVD ion implantation method, namely, the problem of increasing ions which are inevitably diffused to pass through a tunneling oxide layer while improving the surface ion concentration can be solved, the surface ion concentration of the polysilicon layer can be improved, the conductivity can be improved, the contact resistance can be reduced, and the cell filling factor can be improved; ions diffusing through the tunneling oxide layer are reduced, Auger recombination is reduced, the passivation effect of the structure is improved, and the open-circuit voltage and the short-circuit current are improved; the process is mature and can be finished by adopting the existing equipment and secondary process.

Description

Method for preparing passivation contact structure based on LPCVD secondary ion implantation
Technical Field
The invention relates to the technical field of solar cells, in particular to a method for preparing a passivation contact structure in an N-type TOPCon solar cell based on LPCVD secondary ion implantation.
Background
In the field of solar cell technology, the main factor affecting the improvement of cell efficiency is electron-hole pair recombination. In the whole battery structure, due to the disordered arrangement of silicon atoms, a large number of dangling bonds exist on the surface of the silicon wafer, and the dangling bonds can easily capture electrons, so that the surface recombination of the battery is increased. Metal-semiconductor contact regions are also more susceptible to recombination. In order to improve the efficiency of the solar cell and reduce the recombination between the surface and the gold half-contact region, a thin layer of dielectric or semiconductor material is usually deposited on the surface of the device, i.e. surface passivation treatment. However, the general passivation layer has poor conductivity, so that the series resistance of the entire battery increases. In recent years, researchers have introduced the concept of MOS structure in field effect transistors to extend the surface excellent passivation effect under the metal gate line, including both passivation and contact, and thus named as a passivation contact structure. The structure is that an ultra-thin tunneling oxide layer is combined with a heavily doped polysilicon layer, most carriers are transported to the metal in a tunneling mode, and minority carriers cannot pass through the oxide layer due to the bending of an energy band, so the selectivity is also called as a selective contact structure. Batteries manufactured using this structure include TOPCon, PERPoly, POLO, and the like.
The tunnel oxide layer may be deposited by thermal oxidation or liquid phase deposition, and the polysilicon layer may be deposited by LPCVD or PECVD, and may be doped with phosphorus in-situ in the deposition gas mixture, or the intrinsic polysilicon layer may be deposited and then ion implanted or furnace diffused. The conventional preparation method is LPCVD ion implantation, in which a tunnel oxide layer is deposited by LPCVD, intrinsic polysilicon is then deposited in a furnace, and then ion implantation, impurity cleaning, and annealing are performed. The structure prepared by the ion implantation method has the key point of well balancing the surface ion concentration and the ion concentration diffused through the tunneling oxide layer. In general, increasing the ion implantation dose increases the surface ion concentration, reduces the sheet resistance and thus increases the conductivity, but the inevitable diffusion of ions through the tunnel oxide layer correspondingly increases, resulting in increased auger recombination (centopodiacy: auger recombination, which is a recombination process corresponding to auger transition. auger effect is a three-particle effect, where electrons and holes recombine with each other by transferring energy or momentum to another electron or another hole through collision, causing the recombination process of the electron or hole transition to be auger recombination. The invention provides a secondary ion implantation method, which can improve the surface ion concentration of polycrystalline silicon and reduce phosphorus ions diffusing through a tunneling oxide layer under the condition of the same ion implantation dosage.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method for preparing a passivation contact structure based on LPCVD secondary ion implantation.
The invention discloses a method for preparing a passivation contact structure based on LPCVD secondary ion implantation, which comprises the following steps:
(1) selecting an N-type silicon substrate as a substrate to carry out double-sided texturing treatment;
(2) preparing a double-sided p + doped region on the N-type silicon surface subjected to texturing in the step (1) by using boron tribromide as a boron source;
(3) selecting one surface of the N-type silicon subjected to double-sided boron diffusion in the step (2) to be placed in HF and HNO3And H2SO4Etching treatment is carried out in the mixed solution to remove the p + doped region on the back surface, so that a smooth pyramid surface after etching is obtained;
(4) preparing an ultrathin tunneling oxide layer on the back of the etched N-type silicon in the step (3);
(5) preparing an intrinsic polycrystalline silicon film based on the step (4) by adopting LPCVD;
(6) doping the intrinsic polycrystalline silicon layer obtained in the step (5) in a manner of implanting phosphorus atoms by ions;
(7) carrying out RCA cleaning on the N-type silicon doped in the step (6) to remove surface metal ions;
(8) Carrying out rapid thermal annealing treatment on the N-type silicon subjected to RCA cleaning in the step (7);
(9) repeating the steps (6), (7) and (8);
(10) and (5) forming a high-quality fine-particle phosphorus-doped polycrystalline silicon film with smaller grain size on the surface of the N-type silicon annealed in the step (9), namely a back N + doped region.
The invention provides a method for preparing a passivation contact structure based on LPCVD secondary ion implantation, which further comprises the following subsidiary technical scheme:
in the step (2), the diffusion temperature during the preparation of the double-sided p + doped region is 850-1000 ℃, the time is 50-80 min, and the sheet resistance is 80-100 omega/sqr.
Wherein, in the step (3), HF and HNO3And H2SO4The molar ratio of HF to HNO in the mixed solution is3:H2SO4:H2O =1:4:0.6:3, HF mass fraction 20%.
In the step (4), the preparation method of the tunneling oxide layer is any one of high-temperature thermal oxidation, nitric acid oxidation and ozone oxidation; when high-temperature thermal oxidation is adopted, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of more than 1000 ℃, and the thickness of the tunneling oxide layer is 1-3 nm; wherein, when a nitric acid oxidation method is adopted, a nitric acid solution with the mass fraction of 45-60% is adopted to react for 4-10 min at the reaction temperature of 90-115 ℃.
In the step (5), the deposition temperature of the intrinsic polycrystalline silicon layer is 550-650 ℃, and the thickness is 50-400 nm.
In the step (6), when doping treatment is performed by ion implantation of phosphorus atoms, the radio frequency power is 500-2000W, the process pressure is 1E-7-8E-5 Torr, and the reaction time is 1-20 min.
Wherein, in the step (8), when annealing treatment is carried out, the annealing furnace is firstly vacuumized to 10 DEG-4pa, then filling nitrogen as protective gas; the vacuum degree of the annealing furnace in the annealing process is 500-950 mbar, the annealing time is 20-60 min, and the annealing temperature is 800-900 ℃.
Based on the technical scheme, the invention has the technical advantages that:
(1) the secondary ion implantation method can improve the surface ion concentration of the polycrystalline silicon, improve the conductivity and reduce the contact resistance, thereby improving the filling factor of the battery;
(2) ions diffusing through the tunneling oxide layer are reduced, Auger recombination is reduced, the passivation effect of the structure is improved, and open-circuit voltage and short-circuit current are improved;
(3) the process is mature and can be finished by adopting the existing equipment and secondary process.
Therefore, the invention can well solve the problem of the preparation of the heavily doped polysilicon layer by the tubular LPCVD ion implantation method, namely the problem of the increase of ions diffusing through a tunneling oxide layer inevitably caused while the surface ion concentration is improved.
In addition, in order to finally show the implementation effect of the embodiment in the manner of the solar cell structure, the invention also provides a complete preparation method of the solar cell with the N-type passivation contact structure, which comprises the steps (1) to (10) and further comprises the following steps:
(11) passivating the front surface and the rear surface of the N-type silicon annealed in the step (10);
(12) based on the surface passivation treatment in the step (11), a front p + metal electrode is printed on a p + doping area on the front side of the N-type silicon by silver-aluminum paste and sintered at high temperature, and a back N + metal electrode is printed on an N + doping area on the back side of the N-type silicon by silver paste and sintered at high temperature.
In the step (11), an N + doped region on the back surface of the N-type silicon adopts a single-layer passivation structure of a SiNx passivation film, then BOE cleaning is carried out on the silicon wafer, and POLY plating on the front surface is washed away; the p + doped region of the N-type silicon front surface adopts Al2O3And the passivation film and the SiNx passivation antireflection film are of a double-layer passivation structure.
In the step (12), the temperature range of high-temperature sintering is 800-900 ℃, and the number of the front and back fine grids is 106.
Drawings
Fig. 1 is a schematic cross-sectional view of a battery structure after texturing in step (1) of a method for manufacturing a passivated contact structure based on LPCVD secondary ion implantation according to an embodiment of the present invention;
Fig. 2 is a schematic cross-sectional view of a battery structure after double-sided boron diffusion in step (2) of a method for manufacturing a passivated contact structure based on LPCVD secondary ion implantation according to an embodiment of the invention;
fig. 3 is a schematic cross-sectional view of a cell structure after back etching in step (3) of a method for manufacturing a passivated contact structure based on LPCVD secondary ion implantation according to an embodiment of the invention;
fig. 4 is a schematic cross-sectional view of a cell structure after a tunnel oxide layer is deposited in step (4) of a method for manufacturing a passivation contact structure based on LPCVD secondary ion implantation according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a cell structure obtained in steps (5) to (10) of a method for manufacturing a passivated contact structure based on LPCVD secondary ion implantation according to an embodiment of the invention;
fig. 6 is a schematic diagram of a passivated cell in step (11) of a method for manufacturing an N-type passivated contact solar cell according to an embodiment of the invention;
fig. 7 is a schematic diagram of a metallized cell structure in step (12) of a method for manufacturing an N-type passivated contact solar cell according to an embodiment of the invention;
FIG. 8 is a schematic diagram showing a comparison of ECV curves of an LPCVD secondary ion implantation method of an example of the present invention and an ion implantation method of a comparative example LPCVD primary ion implantation method.
In the figure, 1-p + metal electrode, 2-SiNx passivation antireflection film and 3-Al2O3The structure comprises a passivation film, a 4-p + doping area, a 5-N type silicon substrate, a 6-tunneling oxide layer, a 7-back N + doping area, an 8-SiNx passivation film, a 9-N + metal electrode and a 10-POLY winding plating layer.
Detailed Description
The present invention will be described in detail with reference to examples. The specific embodiments are merely illustrative and not restrictive, and those skilled in the art who review this disclosure may make modifications to the embodiments without any inventive contribution, as desired, while remaining within the scope of the appended claims.
In the present embodiment, as shown in fig. 7, the N-type passivation contact structure solar cell includes, from top to bottom, a front p + metal electrode 1, a front SiNx passivation antireflection film 2, and a front Al2O3The structure comprises a passivation film 3, a p + doped region 4, an n-type silicon substrate 5, a tunneling oxide layer 6, a back n + doped region 7, a back SiNx passivation film 8 and a back n + metal electrode 9.
The method for preparing the solar cell with the N-type passivation contact structure comprises the following steps:
(1) selecting an N-type silicon substrate 5 with the thickness of 150-170 mu m, the resistivity of 0.3-2 omega ∙ cm and the size of 156.75mm multiplied by 156.75mm as a substrate to carry out double-sided texturing treatment, wherein the battery structure after the step is finished is shown in figure 1;
(2) Preparing a double-sided p + doped region 4 on the N-type silicon surface subjected to texturing in the step (1) by using boron tribromide as a boron source; wherein the diffusion temperature is 850-1000 ℃, the diffusion time is 50-80 min, the sheet resistance is 80-100 omega/sqr, and the battery structure after the step is finished is shown in figure 2;
(3) selecting one surface of the N-type silicon subjected to double-sided boron diffusion in the step (2) to be placed in HF and HNO3And H2SO4Etching treatment is carried out in the mixed solution to remove the p + doped region 4 on the back surface, so as to obtain the etched gentle pyramid surface; wherein, HF and HNO3And H2SO4The molar ratio of HF to HNO in the mixed solution is3:H2SO4:H2O =1:4:0.6:3, HF mass fraction 20%, the battery structure after completion of this step is shown in fig. 3;
(4) preparing an ultrathin tunneling oxide layer 6 on the back of the etched N-type silicon in the step (3) by adopting a high-temperature thermal oxidation method, a nitric acid oxidation method or an ozone oxidation method; wherein, when high-temperature thermal oxidation is adopted, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of more than 1000 ℃; wherein when a nitric acid oxidation method is adopted, a nitric acid solution with the mass fraction of 45-60% is adopted to react for 4-10 min at the reaction temperature of 90-115 ℃; obtaining the thickness of the tunneling oxide layer 6 to be 1-3 nm, wherein the battery structure after the step is finished is shown in fig. 4;
(5) Preparing an intrinsic polycrystalline silicon film 7 by LPCVD based on the battery structure obtained in the step (4); wherein the deposition temperature of the intrinsic polysilicon layer is 550-650 ℃, the thickness is 50-400 nm, and front POLY plating 10 can be generated on the front surface, as shown in fig. 5;
(6) doping the intrinsic polycrystalline silicon layer obtained in the step (5) in a manner of ion implantation of phosphorus atoms; wherein the radio frequency power is 500-2000W, the process pressure is 1E-7-8E-5 Torr, and the reaction time is 1-20 min;
(7) carrying out RCA cleaning on the doped N-type silicon to remove surface metal ions;
(8) after RCA cleaning in the step (7)The N-type silicon is subjected to rapid thermal annealing treatment, and an annealing furnace is vacuumized to 10 DEG-4pa, then filling nitrogen as protective gas; the vacuum degree of the annealing furnace in the annealing process is 500-950 mbar, the annealing time is 20-60 min, and the annealing temperature is 800-900 ℃;
(9) repeating the steps (6), (7) and (8);
(10) after annealing, the original amorphous structure of the N-type silicon is destroyed, and the doped phosphorus atoms are activated to form a high-quality fine-grained phosphorus-doped polycrystalline silicon thin film with a smaller grain size, which is called a back N + doped region 7 in the solar cell, as shown in fig. 5.
So far, the steps of preparing the passivation contact structure by adopting the LPCVD two-time ion implantation method are completely finished. In order to describe the implementation effect of the embodiment in more detail, step (11) and step (12) are added to the passivation contact structure in the embodiment, and finally, the implementation effect of the embodiment is completely presented in the form of a solar cell structure, which specifically includes:
(11) passivating the front surface and the rear surface of the N-type silicon annealed in the step (10); the N + doped region on the back surface of the N-type silicon adopts a single-layer passivation structure of a SiNx passivation film 8, then BOE cleaning is carried out on the silicon wafer, and front surface POLY winding plating 10 is washed away; the p + doped region 4 of the N-type silicon front surface adopts Al2O3A double-layer passivation structure of the passivation film 3 and the SiNx passivation antireflection film 2 is shown in fig. 6;
(12) based on the step (11), printing a front p + metal electrode 1 on a p + doping area 4 of the front surface of the N-type silicon by adopting silver-aluminum paste and sintering at a high temperature; printing a back N + metal electrode on the N + doped region 7 on the back of the N-type silicon by silver paste and sintering at high temperature; wherein the temperature range of the high-temperature sintering is 800-900 ℃, the number of the fine grids on the front surface and the back surface is 106, as shown in figure 7.
Referring to fig. 8, a schematic diagram comparing ECV curves of the LPCVD secondary ion implantation method of the example of the present invention and the LPCVD primary ion implantation method of the comparative example shows:
Firstly, the surface ion concentration is improved by improving the ion implantation dosage and the sheet resistance is reduced by the comparison example LPCVD one-time ion implantation method, so that the conductivity is improved, but the inevitable ions which diffuse through the tunneling oxide layer are correspondingly increased, and the Auger recombination is increased;
secondly, the LPCVD secondary ion implantation method of the embodiment of the invention not only improves the surface ion concentration of the polycrystalline silicon, but also effectively reduces the phosphorus ions diffusing and penetrating through the tunneling oxide layer under the condition of the same ion implantation dosage, thereby effectively balancing the surface ion concentration and the ion concentration diffusing and penetrating through the tunneling oxide layer and ensuring that the obtained battery has a good structure.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (10)

1. A method for preparing a passivation contact structure based on LPCVD secondary ion implantation is characterized in that: the method comprises the following steps:
(1) Selecting an N-type silicon substrate as a substrate to carry out double-sided texturing treatment;
(2) preparing a double-sided p + doped region on the N-type silicon surface subjected to texturing in the step (1) by using boron tribromide as a boron source;
(3) selecting one surface of the N-type silicon subjected to double-sided boron diffusion in the step (2) to be placed in HF and HNO3And H2SO4Etching treatment is carried out in the mixed solution to remove the p + doped region on the back surface, so that a smooth pyramid surface after etching is obtained;
(4) preparing an ultrathin tunneling oxide layer on the back of the etched N-type silicon in the step (3);
(5) preparing an intrinsic polycrystalline silicon film based on the step (4) by adopting LPCVD;
(6) doping the intrinsic polycrystalline silicon layer obtained in the step (5) in a manner of ion implantation of phosphorus atoms;
(7) carrying out RCA cleaning on the N-type silicon doped in the step (6) to remove surface metal ions;
(8) carrying out rapid thermal annealing treatment on the N-type silicon subjected to RCA cleaning in the step (7);
(9) repeating the steps (6), (7) and (8);
(10) and (4) forming a phosphorus-doped polycrystalline silicon film with small grain size and high quality fine particles on the surface of the N-type silicon annealed in the step (9), namely a back N + doped region.
2. The method for preparing the passivation contact structure based on LPCVD secondary ion implantation, according to the step (2), the diffusion temperature during the preparation of the double-sided p + doped region is 850-1000 ℃, the diffusion time is 50-80 min, and the sheet resistance is 80-100 Ω/sqr.
3. The method for preparing a passivated contact structure based on LPCVD secondary ion implantation according to claim 1, characterized in that in step (3), HF and HNO3And H2SO4The molar ratio of HF to HNO in the mixed solution is3:H2SO4:H2O =1:4:0.6:3, HF mass fraction 20%.
4. The method for preparing the passivation contact structure based on LPCVD secondary ion implantation is characterized in that in the step (4), the preparation method of the tunneling oxide layer is any one of a high-temperature thermal oxidation method, a nitric acid oxidation method or an ozone oxidation method; when high-temperature thermal oxidation is adopted, the reaction is carried out for 10-20 min under the conditions of normal pressure, pure oxygen and the temperature of more than 1000 ℃, and the thickness of the tunneling oxide layer is 1-3 nm; wherein when the nitric acid oxidation method is adopted, a nitric acid solution with the mass fraction of 45-60% is adopted to react for 4-10 min at the reaction temperature of 90-115 ℃.
5. The method for preparing the passivation contact structure based on LPCVD secondary ion implantation of claim 1, characterized in that in step (5), the deposition temperature of the intrinsic polysilicon layer is 550-650 ℃ and the thickness is 50-400 nm.
6. The method for preparing a passivation contact structure based on LPCVD secondary ion implantation of claim 1, characterized in that, in the step (6), when doping treatment is performed by ion implantation of phosphorus atoms, the RF power is 500-2000W, the process pressure is 1E-7-8E-5 Torr, and the reaction time is 1-20 min.
7. A method for preparing passivated contact structure based on LPCVD secondary ion implantation according to claim 1, characterized in that in step (8), the annealing furnace is first evacuated to 10 degrees of vacuum during the annealing process-4pa, then filling nitrogen as protective gas; in the annealing process, the vacuum degree of the annealing furnace is 500-950 mbar, the annealing time is 20-60 min, and the annealing temperature is 800-900 ℃.
8. A preparation method of an N-type passivation contact structure solar cell is characterized by comprising the steps (1) to (10) in claim 1, and further comprising the following steps:
(11) passivating the front surface and the rear surface of the N-type silicon annealed in the step (10);
(12) based on the surface passivation treatment in the step (11), a front p + metal electrode is printed on a p + doping area on the front side of the N-type silicon by silver-aluminum paste and sintered at high temperature, and a back N + metal electrode is printed on an N + doping area on the back side of the N-type silicon by silver paste and sintered at high temperature.
9. The method for preparing the solar cell with the N-type passivation contact structure according to the claim 8, wherein in the step (11), an N + doped region on the back surface of the N-type silicon adopts a single-layer passivation structure of a SiNx passivation film, then BOE cleaning is carried out on the silicon wafer, and POLY plating on the front surface is washed away; the p + doped region of the N-type silicon front surface adopts Al2O3And the passivation film and the SiNx passivation antireflection film are of a double-layer passivation structure.
10. The method for preparing a solar cell with an N-type passivated contact structure according to claim 8, characterized in that in the step (12), the temperature range of the high-temperature sintering is 800-900 ℃, and the number of the front and back fine grids is 106.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684237A (en) * 2004-04-14 2005-10-19 中芯国际集成电路制造(上海)有限公司 High operation voltage double spreading drain MOS device using twice ion injection
CN107195699A (en) * 2017-07-12 2017-09-22 泰州中来光电科技有限公司 One kind passivation contact solar cell and preparation method
CN110197855A (en) * 2019-05-29 2019-09-03 西安理工大学 For Topcon battery production poly-Si around plating minimizing technology

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1684237A (en) * 2004-04-14 2005-10-19 中芯国际集成电路制造(上海)有限公司 High operation voltage double spreading drain MOS device using twice ion injection
CN107195699A (en) * 2017-07-12 2017-09-22 泰州中来光电科技有限公司 One kind passivation contact solar cell and preparation method
CN110197855A (en) * 2019-05-29 2019-09-03 西安理工大学 For Topcon battery production poly-Si around plating minimizing technology

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