CN210040232U - Battery piece - Google Patents
Battery piece Download PDFInfo
- Publication number
- CN210040232U CN210040232U CN201920920532.5U CN201920920532U CN210040232U CN 210040232 U CN210040232 U CN 210040232U CN 201920920532 U CN201920920532 U CN 201920920532U CN 210040232 U CN210040232 U CN 210040232U
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- silicon wafer
- thin film
- layer
- film layer
- polished
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 180
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 180
- 239000010703 silicon Substances 0.000 claims abstract description 180
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 114
- 238000002161 passivation Methods 0.000 claims abstract description 76
- 238000005498 polishing Methods 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 239000010409 thin film Substances 0.000 claims description 98
- 229920005591 polysilicon Polymers 0.000 claims description 68
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910003087 TiOx Inorganic materials 0.000 claims description 5
- 238000010521 absorption reaction Methods 0.000 abstract description 6
- 230000006378 damage Effects 0.000 abstract description 5
- 150000001875 compounds Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 description 26
- 238000000137 annealing Methods 0.000 description 15
- 238000000151 deposition Methods 0.000 description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 14
- 239000010408 film Substances 0.000 description 11
- GETQZCLCWQTVFV-UHFFFAOYSA-N trimethylamine Chemical compound CN(C)C GETQZCLCWQTVFV-UHFFFAOYSA-N 0.000 description 10
- 229910004205 SiNX Inorganic materials 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000012876 topography Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910052755 nonmetal Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- -1 silver aluminum Chemical compound 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The utility model relates to a battery piece, this battery piece include the silicon chip, the sensitive surface and/or the backlight surface of silicon chip include polishing region and non-polishing region, the sensitive surface side and/or the side from interior to exterior of being shaded of silicon chip have set gradually passivation dielectric layer, doped polycrystalline silicon thin layer and metal electrode, the polishing region of silicon chip corresponds the thickness on doped polycrystalline silicon thin layer is greater than non-polishing region corresponds the thickness on doped polycrystalline silicon thin layer, metal electrode with the polishing region of silicon chip is corresponding. According to the utility model discloses the battery piece has reduced the compound destruction to the passivation dielectric layer of metal contact, and has reduced the absorption that the polycrystalline silicon thin layer of doping is to light to open circuit voltage and short-circuit current of this battery piece have been improved, and then the performance of this battery piece has been promoted.
Description
Technical Field
The utility model relates to a solar cell technical field, concretely relates to battery piece.
Background
In order to obtain high efficiency of the crystalline silicon solar cell, the surface of the crystalline silicon substrate of the crystalline silicon solar cell must have good passivation to control the surface recombination rate of minority carriers to be minimum, so that higher open voltage, current and filling factor are obtained. In recent years, passivation contact is gradually applied to the field of crystalline silicon solar cells, and the basic method is to separate passivation from electrical contact, grow an ultrathin oxide layer on the back of a silicon substrate, prepare a doped polycrystalline silicon thin film layer on the oxide layer as a buffer layer of metal electrical contact, and use tunneling effect electrons to penetrate through the ultrathin oxide layer to enter the doped polycrystalline silicon thin film layer and then be collected to an external circuit by a metal electrode. However, in large-scale industrial production, silver paste or silver aluminum paste is screen-printed, and then metal electrical contact is realized by a high-temperature sintering method. In the high-temperature sintering process, the metal slurry can penetrate through the doped polycrystalline silicon thin film layer to have certain damage effect on an oxide layer between the silicon substrate and the doped polycrystalline silicon thin film layer, certain influence is generated on the passivation effect of the oxide layer, and the open-circuit voltage is reduced. In order to reduce the influence of the metal recombination to improve the efficiency of the cell, increasing the thickness of the doped polysilicon thin film layer is a good choice, but the doped polysilicon thin film layer has a certain absorption effect on light, and the absorption effect of the doped polysilicon thin film layer becomes more serious with the increase of the thickness.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, an object of the present invention is to provide a battery piece, which reduces the damage of metal contact to passivation dielectric layer, and reduces the absorption of doped polysilicon thin layer to light, thereby improving the open-circuit voltage and short-circuit current of the battery piece, and further improving the performance of the battery piece.
Another object of the present invention is to provide a method for manufacturing the above battery cell.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
according to the utility model discloses battery piece of first aspect embodiment, including the silicon chip, the sensitive surface and/or the backlight surface of silicon chip include polishing region and non-polishing region, the sensitive surface side and/or the side from interior to exterior of being shaded of silicon chip have set gradually passivation dielectric layer, doped polycrystalline silicon thin layer and metal electrode, the polishing region of silicon chip corresponds the thickness of doped polycrystalline silicon thin layer is greater than non-polishing region corresponds the thickness of doped polycrystalline silicon thin layer, metal electrode with the polishing region of silicon chip is corresponding.
Preferably, the light receiving surface and/or the back surface of the silicon wafer comprise a plurality of polished regions and non-polished regions, and the plurality of polished regions and the non-polished regions are uniformly and alternately distributed.
Preferably, the non-polished area is a textured or wet etched surface.
Preferably, a passivation layer is further disposed on the outer side of the doped polysilicon thin film layer.
Preferably, the passivation dielectric layer is one or more of a SiOx layer, a TiOx layer and a SiOxN1-X layer.
Preferably, the thickness of the passivation dielectric layer is 0.5-2.5 nm.
Preferably, the thickness of the doped polysilicon thin film layer is 5-300 nm.
According to the utility model discloses preparation method of battery piece of second aspect embodiment includes following step:
step S1, providing a silicon chip, and arranging a polishing area and a non-polishing area on a light receiving surface and/or a backlight surface of the silicon chip;
step S2, a passivation dielectric layer and a doped polycrystalline silicon thin film layer are sequentially arranged on the light receiving side and/or the backlight side of the silicon wafer from inside to outside, wherein the thickness of the doped polycrystalline silicon thin film layer corresponding to the polished area of the silicon wafer is larger than that of the doped polycrystalline silicon thin film layer corresponding to the non-polished area;
and step S3, arranging metal electrodes on the light receiving side and/or the backlight side of the silicon chip, wherein the metal electrodes correspond to the polished areas of the silicon chip.
Preferably, the step S1 specifically includes:
step S11, providing a silicon wafer, and arranging a mask on the light receiving side and/or the backlight side of the silicon wafer;
step S12, opening the film on the appointed area of the mask to expose partial area of the light receiving surface and/or the backlight surface of the silicon chip;
step S13, polishing the exposed partial area of the light receiving surface and/or the backlight surface of the silicon wafer to form a polishing area;
and step S14, removing the mask of other areas except the exposed partial area of the light receiving surface and/or the backlight surface of the silicon wafer to form a non-polished area.
Preferably, the step S2 further includes:
and arranging a passivation layer on the outer side of the doped polycrystalline silicon thin film layer.
Preferably, the step S2 further includes:
and after the passivation dielectric layer and the doped polycrystalline silicon thin film layer are sequentially arranged on the light receiving side and/or the backlight side of the silicon wafer from inside to outside, annealing treatment is carried out on the silicon wafer.
Preferably, the step S2 includes:
step S21, arranging a passivation dielectric layer and an undoped polysilicon film layer on the light receiving side and/or the backlight side of the silicon wafer from inside to outside in sequence;
step S22, ion implantation doping or diffusion doping is performed on the surface of the undoped polysilicon thin film layer to form a doped polysilicon thin film layer.
The beneficial effects of the utility model reside in that:
the light receiving surface and/or the backlight surface of the silicon wafer used for forming the cell piece comprises a polishing area and a non-polishing area, when the film is coated, the thickness of the doped polycrystalline silicon thin film layer corresponding to the polishing area of the silicon wafer is larger than that of the doped polycrystalline silicon thin film layer corresponding to the non-polishing area, and the metal electrode corresponds to the polishing area of the silicon wafer, namely the metal contact area of the doped polycrystalline silicon thin film layer is thicker and the non-metal contact area is thinner, so that the damage of metal contact compounding to a passivation dielectric layer is reduced, the open-circuit voltage of the cell piece is improved, the absorption of the doped polycrystalline silicon thin film layer to light is reduced, the short-circuit current of the cell piece is improved, and the performance of the cell piece is further improved.
The above description is only an overview of the technical solution of the present invention, and in order to make the technical means of the present invention clearer and can be implemented according to the content of the description, the following detailed description is made with reference to the preferred embodiments of the present invention and accompanying drawings.
Drawings
Fig. 1 is a partial side view of a battery cell according to an embodiment of the present invention;
fig. 2 is a partial side view of a battery piece according to another embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing a battery plate according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for manufacturing a silicon wafer having a polished region and a non-polished region on a light-receiving surface and/or a back-light surface according to an embodiment of the present invention;
FIG. 5 is a partial side view of a silicon wafer according to an embodiment of the present invention;
FIG. 6 is a partial side view of the silicon wafer of FIG. 5 with a mask disposed on the backlight side;
FIG. 7 is a partial side view of a designated area of the mask disposed on the backlight side of the silicon wafer of FIG. 6 being opened to expose a partial area of the backlight side of the silicon wafer;
FIG. 8 is a partial side view of the exposed portion of the back side of the silicon wafer of FIG. 7 polished to form a polished region;
FIG. 9 is a partial side view of a silicon wafer having a back side provided with polished and non-polished regions in accordance with an embodiment of the present invention;
FIG. 10 is a profile of a back surface of a silicon wafer according to example 1 of the present invention, the back surface being provided with polished regions and non-polished regions;
fig. 11 is a profile of a back surface of a silicon wafer according to example 2 of the present invention, the back surface being provided with a polished region and a non-polished region;
FIG. 12 is a profile of a back-light surface with polished regions and non-polished regions of a silicon wafer according to example 3 of the present invention;
fig. 13 is a profile of a back surface of a silicon wafer according to example 4 of the present invention, the back surface being provided with polished regions and non-polished regions;
fig. 14 is a partial side view of a silicon wafer according to an embodiment of the present invention with a passivation dielectric layer disposed on the backlight side;
FIG. 15 is a partial side view of the silicon wafer of FIG. 14 with the doped polysilicon film layer disposed on the backlight side;
FIG. 16 is a partial side view of the silicon wafer of FIG. 15 with a passivation layer disposed on the backlight side.
Detailed Description
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.
As shown in fig. 1, the battery piece 10 according to the embodiment of the present invention includes a silicon wafer 20, the light receiving surface and/or the back light surface of the silicon wafer 20 includes a polished area 21 and a non-polished area 22, the light receiving side and/or the back light side of the silicon wafer 20 is sequentially provided with a passivation dielectric layer 30, a doped polysilicon thin film layer 40 and a metal electrode 50 from inside to outside, the thickness of the doped polysilicon thin film layer 40 corresponding to the polished area 21 of the silicon wafer 20 is greater than the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished area 22, and the metal electrode 50 corresponds to the polished area 21 of the silicon wafer 20. The doped property of the doped polysilicon thin film layer 40 may be hole doping or electron doping.
By forming the polished area 21 and the non-polished area 22 on the light receiving surface and/or the backlight surface of the silicon wafer 20 of the cell 10, the thickness of the doped polysilicon thin film layer 40 corresponding to the polished area 21 of the silicon wafer 20 is greater than the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished area 22, and the metal electrode 50 corresponds to the polished area 21 of the silicon wafer 20, that is, the metal contact area of the doped polysilicon thin film layer 40 is thicker, and the non-metal contact area is thinner, so that the cell 10 reduces the damage of metal contact recombination to the passivation dielectric layer 30, improves the open-circuit voltage of the cell 10, reduces the absorption of the doped polysilicon thin film layer 40 to light, improves the short-circuit current of the cell 10, and further improves the performance of the cell 10.
According to some embodiments of the present invention, the light receiving surface and/or the back surface of the silicon wafer 20 includes a plurality of polished regions 21 and non-polished regions 22, and the plurality of polished regions 21 and non-polished regions 22 are uniformly and alternately distributed.
According to some embodiments of the present invention, the non-polished area 22 is a textured or wet-etched surface.
As shown in fig. 2, the doped polysilicon thin film layer 40 is further provided with a passivation layer 60 on the outer side according to some embodiments of the present invention. The surface of the doped polysilicon thin film layer 40 is passivated to further improve the performance of the cell piece 10.
According to some embodiments of the present invention, the passivation dielectric layer 30 is SiOxLayer, TiOxLayer and SiOXN1-XOne or more of the layers.
According to some embodiments of the present invention, the thickness of the passivation dielectric layer 30 is 0.5-2.5 nm.
According to some embodiments of the present invention, the doped polysilicon thin film layer 40 has a thickness of 5-300 nm.
As shown in fig. 3, the method for manufacturing the battery piece 10 according to the embodiment of the present invention includes the following steps:
step S1, providing a silicon wafer 20, and arranging a polishing region 21 and a non-polishing region 22 on the light-receiving surface and/or the back surface of the silicon wafer 20;
as shown in fig. 4, according to some embodiments of the present invention, step S1 specifically includes:
step S11, as shown in fig. 5, providing the silicon wafer 20, as shown in fig. 6, disposing a mask 70 on the light receiving side and/or the backlight side of the silicon wafer 20;
step S12, as shown in fig. 7, opening the film on the designated area of the mask 70 to expose partial area of the light receiving surface and/or the backlight surface of the silicon wafer 20;
step S13, as shown in FIG. 8, polishing the exposed partial area of the light receiving surface and/or the back surface of the silicon wafer 20 to form a polished area 21;
in step S14, as shown in fig. 9, the mask 70 is removed from the regions of the silicon wafer 20 other than the exposed partial regions of the light-receiving surface and/or the back-light surface, thereby forming the non-polished regions 22.
In step S12, a picosecond, sub-second, or nanosecond laser is preferably used to open the designated area of the mask 70.
Step S2, as shown in fig. 14 and 15, a passivation dielectric layer 30 and a doped polysilicon thin film layer 40 are sequentially disposed on the light receiving side and/or the backlight side of the silicon wafer 20 from inside to outside, wherein the thickness of the doped polysilicon thin film layer 40 corresponding to the polishing region 21 of the silicon wafer 20 is greater than the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polishing region 22;
preferably, the passivation dielectric layer 30 may be disposed on the light receiving side and/or the backlight side of the silicon wafer 20 by a low-temperature furnace tube oxidation process, a nitric acid oxidation process, an ozone oxidation process, an atomic layer deposition process, a low-pressure chemical vapor deposition method, or a plasma-enhanced chemical vapor deposition method.
Preferably, the doped polysilicon thin film layer 40 may be deposited on the outer side of the passivation dielectric layer 30 by a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.
According to some embodiments of the invention, step S2 further comprises: as shown in fig. 16, a passivation layer 60 is disposed on the outer side of the doped polysilicon thin film layer 40. Preferably, a passivation layer 60 may be deposited on the outside of the doped polysilicon thin film layer 40 using a tube or plate plasma enhanced chemical vapor deposition method.
According to some embodiments of the invention, step S2 further comprises: after the light receiving side and/or the backlight side of the silicon wafer 20 are sequentially provided with the passivation dielectric layer 30 and the doped polycrystalline silicon thin film layer 40 from inside to outside, the silicon wafer 20 is annealed. The doped polycrystalline silicon thin film layer 40 is activated, and the doped polycrystalline silicon thin film layer 40 is crystallized, so that the performance of the doped polycrystalline silicon thin film layer 40 is further improved.
According to some embodiments of the invention, step S2 includes:
step S21, arranging a passivation dielectric layer 30 and an undoped polysilicon film layer 40 on the light receiving side and/or the backlight side of the silicon wafer 20 from inside to outside in sequence;
in step S22, ion implantation doping or diffusion doping is performed on the surface of the undoped polysilicon thin film layer 40 to form the doped polysilicon thin film layer 40.
In step S3, metal electrodes 50 are disposed on the light receiving side and/or the backlight side of the silicon wafer 20, and the metal electrodes 50 correspond to the polishing regions 21 of the silicon wafer 20.
The invention is described below by means of specific embodiments.
Example 1
The utility model discloses cell 10, including silicon chip 20, the backlight of silicon chip 20 is taken turns to including polishing region 21 and non-polishing region 22, and the side of being shaded of silicon chip 20 has set gradually passivation dielectric layer 30, doped polycrystalline silicon thin layer 40, passivation layer 60 and metal electrode 50 from interior to exterior, and the polishing region 21 of silicon chip 20 is corresponding with metal electrode 50.
The back surface of the silicon wafer 20 includes a plurality of polished regions 21 and non-polished regions 22, the polished regions 21 and the non-polished regions 22 are uniformly and alternately distributed, and the non-polished regions 22 are wet etched surfaces.
The passivation dielectric layer 30 is SiOxA layer having a thickness of 1.5 nm.
The thickness of the doped polysilicon thin film layer 40 corresponding to the polished region 21 of the silicon wafer 20 is 192nm, and the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished region 22 of the silicon wafer 20 is 156 nm.
The passivation layer 60 is SiNxAnd (3) a layer.
Above-mentioned the utility model discloses a preparation method of battery piece 10 of embodiment includes following steps:
A. the back surface of the silicon wafer 20 is provided with a polished region 21 and a non-polished region 22: after the silicon wafer 20 is cleaned, 50nm thick SiO is deposited on the back surface of the silicon wafer 20 by using a plasma enhanced chemical vapor deposition methodxA mask 70; then, opening the film on the designated area of the mask 70 by using laser to expose partial area of the backlight surface of the silicon wafer 20; then, putting the silicon wafer 20 into a trimethylamine solution, and performing chemical polishing treatment on the exposed partial area of the back surface of the silicon wafer 20 to form a polishing area 21; finally, the mask 70 is removed from the areas of the wafer 20 other than the exposed portion of the back side of the wafer using an HF solution to form the non-polished areas 22, and the topography of the back side of the wafer 20 is shown in FIG. 10.
B. Setting a passivation dielectric layer 30: depositing SiO with the thickness of 1.5nm on the backlight surface of the silicon wafer 20 by adopting low-pressure chemical vapor deposition equipmentxA passivation dielectric layer 30;
C. setting the doped polysilicon thin film layer 40: depositing a P-doped polycrystalline silicon thin film layer 40 on the back surface of the silicon wafer 20 at 620 ℃ by using low-pressure chemical vapor deposition equipment, wherein the thickness of the P-doped polycrystalline silicon thin film layer 40 corresponding to the polishing region 21 of the silicon wafer 20 is 192nm, and the thickness of the P-doped polycrystalline silicon thin film layer 40 corresponding to the non-polishing region 22 of the silicon wafer 20 is 156 nm.
D. Annealing: annealing the silicon wafer 20 at 850 ℃ to activate the doped P and realize crystallization heat treatment of the doped polysilicon thin film layer 40, thereby further improving the performance of the doped polysilicon thin film layer 40;
E. the passivation layer 60 is provided: removing the oxide layer grown on the doped polysilicon thin film layer 40 after annealing by using HF solution, and depositing SiN on the backlight surface of the silicon wafer 20 by using a plate-type plasma enhanced chemical vapor deposition methodxPassivation layer 60, as shown in fig. 10;
F. setting the metal electrode 50: and arranging a metal electrode 50 on the backlight surface of the silicon chip 20 by adopting a screen printing mode, wherein the metal electrode 50 corresponds to the polishing region 21 of the silicon chip 20.
Example 2
The utility model discloses cell 10, including silicon chip 20, the backlight of silicon chip 20 is taken turns to including polishing region 21 and non-polishing region 22, and the side of being shaded of silicon chip 20 has set gradually passivation dielectric layer 30, doped polycrystalline silicon thin layer 40, passivation layer 60 and metal electrode 50 from interior to exterior, and the polishing region 21 of silicon chip 20 is corresponding with metal electrode 50.
The back surface of the silicon wafer 20 includes a plurality of polished regions 21 and non-polished regions 22, the polished regions 21 and the non-polished regions 22 are uniformly and alternately distributed, and the non-polished regions 22 are wet etched surfaces.
The passivation dielectric layer 30 is SiOxA layer having a thickness of 1.0 nm.
The thickness of the doped polysilicon thin film layer 40 corresponding to the polished region 21 of the silicon wafer 20 is 151nm, and the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished region 22 of the silicon wafer 20 is 125 nm.
The passivation layer 60 is SiNxAnd (3) a layer.
Above-mentioned the utility model discloses a preparation method of battery piece 10 of embodiment includes following steps:
A. the back surface of the silicon wafer 20 is provided with a polished region 21 and a non-polished region 22: after the silicon wafer 20 is cleaned, SiN with a thickness of 30nm is deposited on the back light surface of the silicon wafer 20 by using a plasma enhanced chemical vapor deposition methodxA mask 70; then, opening the film on the designated area of the mask 70 by using laser to expose partial area of the backlight surface of the silicon wafer 20; then, putting the silicon wafer 20 into a trimethylamine solution, and performing chemical polishing treatment on the exposed partial area of the back surface of the silicon wafer 20 to form a polishing area 21; finally, the mask 70 is removed from the areas of the wafer 20 other than the exposed portion of the back side of the wafer using an HF solution to form the non-polished areas 22, and the topography of the back side of the wafer 20 is shown in FIG. 11.
B. Setting a passivation dielectric layer 30: growing SiO with the thickness of 1.0nm on the backlight surface of the silicon wafer 20 by adopting low-temperature furnace tube equipmentxA passivation dielectric layer 30;
C. setting the doped polysilicon thin film layer 40: depositing a P-doped polycrystalline silicon thin film layer 40 on the back surface of the silicon wafer 20 at 610 ℃ by adopting plasma enhanced chemical vapor deposition equipment, wherein the thickness of the P-doped polycrystalline silicon thin film layer 40 corresponding to the polishing region 21 of the silicon wafer 20 is 151nm, and the thickness of the P-doped polycrystalline silicon thin film layer 40 corresponding to the non-polishing region 22 of the silicon wafer 20 is 125 nm.
D. Annealing: annealing the silicon wafer 20 at 875 ℃, so as to activate the doped P, and to perform crystallization heat treatment on the doped polysilicon thin film layer 40, thereby further improving the performance of the doped polysilicon thin film layer 40;
E. the passivation layer 60 is provided: removing the oxide layer grown on the doped polysilicon thin film layer 40 after annealing by using HF solution, and depositing SiN on the backlight surface of the silicon wafer 20 by using a plate-type plasma enhanced chemical vapor deposition methodxPassivation layer 60, as shown in fig. 10;
F. setting the metal electrode 50: and arranging a metal electrode 50 on the backlight surface of the silicon chip 20 by adopting a screen printing mode, wherein the metal electrode 50 corresponds to the polishing region 21 of the silicon chip 20.
Example 3
The utility model discloses cell 10, including silicon chip 20, the backlight of silicon chip 20 is taken turns to including polishing region 21 and non-polishing region 22, and the side of being shaded of silicon chip 20 has set gradually passivation dielectric layer 30, doped polycrystalline silicon thin layer 40, passivation layer 60 and metal electrode 50 from interior to exterior, and the polishing region 21 of silicon chip 20 is corresponding with metal electrode 50.
The back surface of the silicon wafer 20 includes a plurality of polished regions 21 and non-polished regions 22, the polished regions 21 and the non-polished regions 22 are uniformly and alternately distributed, and the non-polished regions 22 are wet etched surfaces.
The passivation dielectric layer 30 is SiOxA layer having a thickness of 1.0 nm.
The thickness of the doped polysilicon thin film layer 40 corresponding to the polished region 21 of the silicon wafer 20 is 105nm, and the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished region 22 of the silicon wafer 20 is 72 nm.
The passivation layer 60 is SiNxAnd (3) a layer.
Above-mentioned the utility model discloses a preparation method of battery piece 10 of embodiment includes following steps:
A. the back surface of the silicon wafer 20 is provided with a polished region 21 and a non-polished region 22: after the silicon wafer 20 is cleaned, SiO with a thickness of 100nm is deposited on the back light surface of the silicon wafer 20 by using a plasma enhanced chemical vapor deposition methodxA mask 70; then, opening the film on the designated area of the mask 70 by using laser to expose partial area of the backlight surface of the silicon wafer 20; then, putting the silicon wafer 20 into a trimethylamine solution, and performing chemical polishing treatment on the exposed partial area of the back surface of the silicon wafer 20 to form a polishing area 21; finally, the mask 70 is removed from the areas of the wafer 20 other than the exposed portion of the back side of the wafer using an HF solution to form the non-polished areas 22, and the topography of the back side of the wafer 20 is shown in FIG. 12.
B. Setting a passivation dielectric layer 30: oxidizing and growing SiO with the thickness of 1.0nm on the backlight surface of the silicon wafer 20 by adopting nitric acidxA passivation dielectric layer 30;
C. setting the doped polysilicon thin film layer 40: depositing a P-doped polycrystalline silicon thin film layer 40 on the back surface of the silicon wafer 20 at 630 ℃ by using low-pressure chemical vapor deposition equipment, wherein the thickness of the P-doped polycrystalline silicon thin film layer 40 corresponding to the polishing region 21 of the silicon wafer 20 is 105nm, and the thickness of the P-doped polycrystalline silicon thin film layer 40 corresponding to the non-polishing region 22 of the silicon wafer 20 is 72 nm.
D. Annealing: annealing the silicon wafer 20 at 860 ℃ to activate the doped P and realize crystallization heat treatment of the doped polysilicon thin film layer 40, thereby further improving the performance of the doped polysilicon thin film layer 40;
E. the passivation layer 60 is provided: removing the oxide layer grown on the doped polycrystalline silicon thin film layer 40 after annealing by using an HF solution, and depositing a SiNx passivation layer 60 on the backlight surface of the silicon wafer 20 by using a tubular plasma enhanced chemical vapor deposition method;
F. setting the metal electrode 50: and arranging a metal electrode 50 on the backlight surface of the silicon chip 20 by adopting a screen printing mode, wherein the metal electrode 50 corresponds to the polishing region 21 of the silicon chip 20.
Example 4
The utility model discloses cell 10, including silicon chip 20, the backlight of silicon chip 20 is taken turns to including polishing region 21 and non-polishing region 22, and the side of being shaded of silicon chip 20 has set gradually passivation dielectric layer 30, doped polycrystalline silicon thin layer 40, passivation layer 60 and metal electrode 50 from interior to exterior, and the polishing region 21 of silicon chip 20 is corresponding with metal electrode 50.
The back surface of the silicon wafer 20 includes a plurality of polished regions 21 and non-polished regions 22, the polished regions 21 and the non-polished regions 22 are uniformly and alternately distributed, and the non-polished regions 22 are wet etched surfaces.
The passivation dielectric layer 30 is SiOxLayer and TiOxThe thickness of the layer stack, passivation dielectric layer 30, was 2.0 nm.
The thickness of the doped polysilicon thin film layer 40 corresponding to the polished region 21 of the silicon wafer 20 is 125nm, and the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished region 22 of the silicon wafer 20 is 92 nm.
The passivation layer 60 is a SiNx layer.
Above-mentioned the utility model discloses a preparation method of battery piece 10 of embodiment includes following steps:
A. the back surface of the silicon wafer 20 is provided with a polished region 21 and a non-polished region 22: after the silicon wafer 20 is cleaned, SiO with a thickness of 20nm is deposited on the back light surface of the silicon wafer 20 by using a plasma enhanced chemical vapor deposition methodxAnd 20nm thick SiNxThe stack mask 70; then, opening the film on the designated area of the mask 70 by using laser to expose partial area of the backlight surface of the silicon wafer 20; then, putting the silicon wafer 20 into a trimethylamine solution, and performing chemical polishing treatment on the exposed partial area of the back surface of the silicon wafer 20 to form a polishing area 21; finally, the mask 70 is removed from the areas of the wafer 20 other than the exposed portion of the back side of the wafer using an HF solution to form the non-polished areas 22, and the topography of the back side of the wafer 20 is shown in FIG. 13.
B. Setting a passivation dielectric layer 30: depositing SiO 2.0nm thick on the back surface of the silicon wafer 20 by adopting atomic deposition equipmentxLayer and TiOxA passivation dielectric layer 30 of a stack of layers;
C. setting the doped polysilicon thin film layer 40: depositing an undoped polysilicon thin film layer 40 on the back surface of the silicon wafer 20 at 630 ℃ by using a low pressure chemical vapor deposition device, wherein the thickness of the undoped polysilicon thin film layer 40 corresponding to the polished region 21 of the silicon wafer 20 is 125nm, the thickness of the undoped polysilicon thin film layer 40 corresponding to the non-polished region 22 of the silicon wafer 20 is 92nm, and then implanting 4E15atoms/cm2 of boron impurities into the surface of the undoped polysilicon thin film layer 40 to form the doped polysilicon thin film layer 40.
D. Annealing: annealing the silicon wafer 20 at 1000 ℃ to activate the doped B, and to perform crystallization heat treatment on the doped polysilicon thin film layer 40, thereby further improving the performance of the doped polysilicon thin film layer 40;
E. the passivation layer 60 is provided: removing the oxide layer grown on the doped polysilicon thin film layer 40 after annealing by using HF solution, and depositing SiN on the backlight surface of the silicon wafer 20 by using a tubular plasma enhanced chemical vapor deposition methodx A passivation layer 60;
F. setting the metal electrode 50: and arranging a metal electrode 50 on the backlight surface of the silicon chip 20 by adopting a screen printing mode, wherein the metal electrode 50 corresponds to the polishing region 21 of the silicon chip 20.
Example 5
The utility model discloses cell 10, including silicon chip 20, the backlight of silicon chip 20 is taken turns to including polishing region 21 and non-polishing region 22, and the side of being shaded of silicon chip 20 has set gradually passivation dielectric layer 30, doped polycrystalline silicon thin layer 40, passivation layer 60 and metal electrode 50 from interior to exterior, and the polishing region 21 of silicon chip 20 is corresponding with metal electrode 50.
The back surface of the silicon wafer 20 includes a plurality of polished regions 21 and non-polished regions 22, the polished regions 21 and the non-polished regions 22 are uniformly and alternately distributed, and the non-polished regions 22 are texturing surfaces.
The passivation dielectric layer 30 is a SiOx layer with a thickness of 1.0 nm.
The thickness of the doped polysilicon thin film layer 40 corresponding to the polished region 21 of the silicon wafer 20 is 105nm, and the thickness of the doped polysilicon thin film layer 40 corresponding to the non-polished region 22 of the silicon wafer 20 is 58 nm.
The passivation layer 60 is a SiNx layer.
Above-mentioned the utility model discloses a preparation method of battery piece 10 of embodiment includes following steps:
A. the back surface of the silicon wafer 20 is provided with a polished region 21 and a non-polished region 22: after cleaning the silicon wafer 20, depositing a SiOx mask 70 with a thickness of 100nm on the backlight surface of the silicon wafer 20 by using a plasma enhanced chemical vapor deposition method; then, opening the film on the designated area of the mask 70 by using laser to expose partial area of the backlight surface of the silicon wafer 20; then, putting the silicon wafer 20 into a trimethylamine solution, and performing chemical polishing treatment on the exposed partial area of the back surface of the silicon wafer 20 to form a polishing area 21; finally, the mask 70 is removed from the areas of the wafer 20 other than the exposed portion of the back side of the wafer using an HF solution to form the non-polished areas 22, and the topography of the back side of the wafer 20 is shown in FIG. 12.
B. Setting a passivation dielectric layer 30: adopting nitric acid to oxidize and grow a SiOx passivation dielectric layer 30 with the thickness of 1.0nm on the backlight surface of the silicon chip 20;
C. setting the doped polysilicon thin film layer 40: depositing an undoped polysilicon thin film layer 40 on the back surface of the silicon wafer 20 at 630 ℃ by using low-pressure chemical vapor deposition equipment, wherein the thickness of the undoped polysilicon thin film layer 40 corresponding to the polishing region 21 of the silicon wafer 20 is 105nm, the thickness of the undoped polysilicon thin film layer 40 corresponding to the non-polishing region 22 of the silicon wafer 20 is 58nm, and then performing phosphorus diffusion doping on the surface of the undoped polysilicon thin film layer 40 at 860 ℃ to form a doped polysilicon thin film layer 40;
D. annealing: the silicon wafer 20 is annealed while phosphorus diffusion doping is carried out on the undoped polycrystalline silicon thin film layer 40 at 860 ℃, so that on one hand, doped P is activated, on the other hand, crystallization heat treatment is carried out on the doped polycrystalline silicon thin film layer 40, and the performance of the doped polycrystalline silicon thin film layer 40 is further improved;
E. the passivation layer 60 is provided: removing the oxide layer grown on the doped polycrystalline silicon thin film layer 40 after annealing by using an HF solution, and depositing a SiNx passivation layer 60 on the backlight surface of the silicon wafer 20 by using a tubular plasma enhanced chemical vapor deposition method;
F. setting the metal electrode 50: and arranging a metal electrode 50 on the backlight surface of the silicon chip 20 by adopting a screen printing mode, wherein the metal electrode 50 corresponds to the polishing region 21 of the silicon chip 20.
Example 6
This embodiment 6 is substantially the same as embodiment 1, and this embodiment 6 is different from embodiment 1 in that: the backlight surface of the silicon wafer 20 in the battery piece 10 of the embodiment of the present invention is not provided with the passivation layer 60.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (7)
1. The cell (10) is characterized by comprising a silicon wafer (20), wherein a light receiving surface and/or a backlight surface of the silicon wafer (20) comprises a polishing region (21) and a non-polishing region (22), a passivation dielectric layer (30), a doped polycrystalline silicon thin film layer (40) and a metal electrode (50) are sequentially arranged on the light receiving side and/or the backlight side of the silicon wafer (20) from inside to outside, the thickness of the doped polycrystalline silicon thin film layer (40) corresponding to the polishing region (21) of the silicon wafer (20) is larger than that of the doped polycrystalline silicon thin film layer (40) corresponding to the non-polishing region (22), and the metal electrode (50) corresponds to the polishing region (21) of the silicon wafer (20).
2. The cell (10) according to claim 1, wherein the light receiving surface and/or the back surface of the silicon wafer (20) comprises a plurality of the polished regions (21) and the non-polished regions (22), and the plurality of the polished regions (21) and the non-polished regions (22) are uniformly and alternately distributed.
3. The cell (10) of claim 1, wherein the non-polished regions (22) are textured or wet etched surfaces.
4. Cell sheet (10) according to claim 1, wherein the doped polysilicon thin film layer (40) is further provided with a passivation layer (60) on the outer side.
5. The battery piece (10) of claim 1, wherein the passivation dielectric layer (30) is SiOxLayer, TiOxLayer and SiOXN1-XOne or more of the layers.
6. The battery piece (10) of claim 1, wherein the thickness of the passivation dielectric layer (30) is 0.5-2.5 nm.
7. Cell sheet (10) according to claim 1, wherein the thickness of the doped polysilicon thin film layer (40) is 5-300 nm.
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| CN201920920532.5U CN210040232U (en) | 2019-06-18 | 2019-06-18 | Battery piece |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920920532.5U CN210040232U (en) | 2019-06-18 | 2019-06-18 | Battery piece |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110120434A (en) * | 2019-06-18 | 2019-08-13 | 合肥晶澳太阳能科技有限公司 | Cell piece and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120434A (en) * | 2019-06-18 | 2019-08-13 | 合肥晶澳太阳能科技有限公司 | Cell piece and preparation method thereof |
| CN110120434B (en) * | 2019-06-18 | 2024-03-26 | 合肥晶澳太阳能科技有限公司 | Battery piece and preparation method thereof |
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