CN110970562A - Perovskite/crystalline silicon laminated solar cell and preparation method thereof - Google Patents

Perovskite/crystalline silicon laminated solar cell and preparation method thereof Download PDF

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CN110970562A
CN110970562A CN201811141867.3A CN201811141867A CN110970562A CN 110970562 A CN110970562 A CN 110970562A CN 201811141867 A CN201811141867 A CN 201811141867A CN 110970562 A CN110970562 A CN 110970562A
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crystalline silicon
perovskite
silicon substrate
thickness
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许吉林
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Zishi Energy Co.,Ltd.
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Dongtai Hi Tech Equipment Technology Co Ltd
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Abstract

The invention relates to a perovskite/crystalline silicon tandem solar cell which comprises a crystalline silicon cell, a composite junction and a perovskite cell, wherein the composite junction is arranged between the crystalline silicon cell and the perovskite cell, the crystalline silicon cell comprises a crystalline silicon substrate, one surface of the crystalline silicon substrate, which is close to the composite junction, is a suede surface, and the composite junction is made of nc-Si: H (p+)/nc‑Si:H(n+). The laminated cell is of a suede structure, so that light reflection can be effectively reduced, spectral absorption efficiency and current density are increased, and photoelectric conversion efficiency is improved. The adopted material is nc-Si: H (p)+)/nc‑Si:H(n+) The composite junction can avoid the deposition of the perovskite cell in a suede structure, prepare a uniform thin layer, and increase the spectral absorption efficiency and the current density, thereby improving the photoelectric conversion efficiency.

Description

Perovskite/crystalline silicon laminated solar cell and preparation method thereof
Technical Field
The invention relates to the field of solar cells, in particular to a perovskite/crystalline silicon tandem solar cell and a preparation method thereof.
Background
The crystalline silicon solar cell technology is the most mature commercial photovoltaic power generation technology at present, the theoretical limit efficiency of the crystalline silicon solar cell technology is about 29%, and the efficiency of the crystalline silicon solar cell is difficult to greatly improve.
A new heterojunction cell with upper and lower double absorption layers formed by materials with excellent optical and electrical properties and silicon is searched, and the heterojunction cell has important significance for improving the spectral absorption rate and further improving the efficiency of the solar cell.
Organic/inorganic hybrid perovskites (e.g. CH)3NH3PbI3) Materials are the hot spot of recent years of research in the field of solar cells. The perovskite battery has the advantages of continuously adjustable forbidden band width, high light absorption coefficient, photon cyclability, excellent charge transport property and the like. Because the band gap of the perovskite material is adjustable (1.5-2.3eV), a very high band gap can be generally obtained through doping, the carrier mobility is high, the diffusion length is long, the crystal defects are few, the process is relatively simple, the perovskite material is easy to compound with other battery materials, the perovskite material can well complement the short plate of the crystalline silicon battery, and the perovskite material is an ideal material for preparing the crystalline silicon laminated battery.
The solar cell with the textured structure can improve the efficiency of the cell. However, since the textured structure surface forms irregularities, the irregularities are easily accumulated in the recesses on the surface in the process of continuously depositing the hole transport layer of the perovskite battery on the surface, and a uniform thin layer cannot be prepared. Therefore, the prior art cannot prepare crystalline silicon/perovskite composite batteries with higher efficiency.
Disclosure of Invention
The invention aims to provide a perovskite/crystalline silicon tandem solar cell, which comprises a crystalline silicon cell, a composite junction and a perovskite cell, wherein the composite junction is arranged between the crystalline silicon cell and the perovskite cell, the crystalline silicon cell comprises a crystalline silicon substrate, one surface of the crystalline silicon substrate, which is close to the composite junction, is a suede surface, and the composite junction is made of nc-Si: H (p+)/nc-Si:H(n+)。
Aiming at the crystalline silicon cell with the textured surface on the surface of the crystalline silicon substrate, the material deposited on the surface is nc-Si: H (p)+)/nc-Si:H(n+) The composite junction can avoid the accumulation of perovskite cell material on the surface of the crystalline silicon cell, and the solar cell with excellent layered structure and higher light conversion efficiency is obtained.
In the use process of the solar cell, the crystalline silicon cell is arranged at the lower part, and the perovskite cell is arranged at the upper part, so that the effect of improving the efficiency can be achieved by arranging one surface of the crystalline silicon substrate into a suede structure, and the efficiency can be further improved if the other surface of the crystalline silicon substrate is also arranged into the suede structure.
Preferably, the suede structure is a suede pyramid structure.
More preferably, the suede structure is obtained by treating a silicon wafer with a strong alkaline solution.
Preferably, the crystalline silicon battery further comprises p+poly-Si layer, first tunneling layer SiOxA second tunneling layer SiOx and n+A poly-Si layer, the first tunneling layer SiOxThe second tunneling layer SiO is arranged on the first surface of the crystal silicon substratexThe second surface of the crystal silicon substrate is oppositely arranged with the first surface of the crystal silicon substrate, and p+A poly-Si layer arranged on the SiO of the first tunneling layerxA surface far away from the crystal silicon substrate, n+A poly-Si layer arranged on the SiO of the second tunneling layerxAnd between the composite junctions.
Double-sided tunneling layer SiOxCombined with the polysilicon matrix, the silicon-based composite material has the functions of surface passivation and selective carrier (electrons and holes) passing, and can greatly reduce the carrier recombination phenomenon generated by the contact of the metal electrode and the silicon surface.
Preferably, the first surface of the crystalline silicon substrate is a textured surface.
Preferably, in said p+The poly-Si layer is far away from the SiO of the tunneling layerxThe other side is laminated with a transparent conductive film a. More preferably, the material of the transparent conductive film a is Indium Tin Oxide (ITO) or fluorine-doped SnO2(FTO), Indium Zinc Oxide (IZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or graphene thin film.
Preferably, the tunneling layer is SiOxThe thickness of (A) is 1.0 to 2.0 nm. Tunneling layer SiOxToo thin a thickness does not serve a passivation function, and too thick a thickness affects carrier transport, and is most suitable for the above thickness. Preferably, said n+The thickness of the poly-Si layer is 100 to 300 nm.
Preferably, said p is+The thickness of the poly-Si layer is 100 to 300 nm.
Preferably, the thickness of the crystalline silicon substrate is 200-300 mm;
preferably, the thickness of the transparent conductive film a is 100-200 nm;
more preferably, the material of the transparent conductive film a is ITO, the thickness is 110nm and p+The thickness of the poly-Si layer is 150nm, and the tunneling layer is SiOxHas a thickness of 1.7nm, a thickness of the crystalline silicon substrate of 240mm, n+The thickness of the poly-Si layer was 150 nm.
Or the material of the transparent conductive film a is ITO, and the thickness of the transparent conductive film a is 180nm and p+The thickness of the poly-Si layer is 100nm, and the tunneling layer is SiOxHas a thickness of 1.5nm, a thickness of the crystalline silicon substrate of 260 microns, n+The thickness of the poly-Si layer was 100 nm.
Or the material of the transparent conductive film a is ITO, and the thickness of the transparent conductive film a is 180nm and p+The thickness of the poly-Si layer is 200nm, and the tunneling layer is SiOxIs 1.8nm, the thickness of the crystalline silicon substrate is 280nm, n+The thickness of the poly-Si layer was 200 nm.
Preferably, the perovskite battery comprises a hole transport layer, a perovskite layer, an electron transport layer and a buffer layer; the hole transport layer is arranged on one surface, far away from the crystalline silicon battery, of the composite junction, the perovskite layer is arranged on the first surface of the electron transport layer, the buffer layer is arranged on the second surface of the electron transport layer, the hole transport layer is arranged on one surface, far away from the electron transport layer, of the perovskite layer, and the first surface and the second surface of the electron transport layer are arranged oppositely.
Preferably, the material of the buffer layer is titanium dioxide (TiO)2) Tin dioxide (SnO)2) Or aluminum doped zinc oxide (Al doped ZnO).
Preferably, in the perovskite battery, the band gap of the perovskite layer material is 1.5-1.75 Ev. The material can absorb light with the wavelength of 300-750nm, is matched with the band gap of the crystalline silicon battery, and can effectively make up the defects of the crystalline silicon battery.
Preferably, the perovskite layer material is MAPbI3、MAPbBr3Or CsxFA1-xPb(I,Br)3Wherein MA is methylamine, FA is formamidine, and x is not less than 0 and not more than 0.5; the band gap width of the material meets the requirement, and the material hasHas better stability.
Preferably, a transparent conductive film b and an antireflection layer are stacked on the buffer layer on the side away from the electron transport layer.
Preferably, the material of the hole transport layer is 2,2',7,7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino]-9,9 '-spirobifluorene (Spiro-OMeTAD), 2',7,7 '-tetrakis (di-p-tolylamino) Spiro-9, 9' -bifluorene (Spiro-TTB), poly (3, 4-ethylenedioxythiophene) -poly (styrenesulfonic acid) (PEDOT-PSS), graphene, nickel oxide (NiO), cuprous thiocyanate (CuSCN), copper iodide (CuI)2) Molybdenum vapor (MoO)x) Or nickel cobaltate (NiCo)2O4)。
Preferably, the material of the electron transport layer is titanium dioxide (TiO)2) Zinc oxide (ZnO), fullerene derivative (PCBM), lithium fluoride-loaded graphene (LiF/C)60) Or tin oxide (SnO)2)；
Preferably, the material of the transparent conductive film b is Indium Tin Oxide (ITO), fluorine-doped tin oxide (FTO), Indium Zinc Oxide (IZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or a graphene thin film; (ii) a
Preferably, the material of the antireflection layer is magnesium fluoride (MgF)2) Or silicon nitride (Si)3N4)；
Preferably, the thickness of the hole transport layer is 100-500 nm;
preferably, the thickness of the perovskite layer is 50-1000nm, more preferably 200-500 nm;
preferably, the thickness of the electron transport layer is 5-50 nm;
preferably, the thickness of the buffer layer is 5-50 nm;
preferably, the thickness of the transparent conductive film b is 50 to 200 nm;
preferably, the thickness of the antireflection layer is 50 to 100 nm.
Further preferably, the hole transport layer is a Spiro-OMeTAD with a thickness of 300 nm;
the perovskite layer is made of Cs0.5FA0.5Pb(I,Br)3The thickness of the film is 350 nm;
the material of the electron transport layer is LiF/C60The thickness of the film is 80 nm;
the buffer layer is made of SnO2The thickness of the film is 10 nm;
the transparent conductive film b is made of IZO and has a thickness of 100 nm;
the material of the antireflection layer is MgF2The thickness is 100 nm.
Or the hole transport layer is PEDOT-PSS with the thickness of 400 nm;
the perovskite layer is made of MAPbI3The thickness was 450 nm.
The electron transport layer is made of PCBM, and the thickness of the PCBM is 100 nm;
the buffer layer is made of TiO2The thickness of the film is 15 nm;
the transparent conductive film b is made of FTO, and the thickness of the FTO is 50 nm;
the material of the antireflection layer is Si3N4The thickness was 85 nm.
Or the hole transport layer is NiO, and the thickness of the hole transport layer is 200 nm;
the perovskite layer is made of MAPbBr3The thickness is 400 nm.
The electron transport layer is made of PCBM, and the thickness of the PCBM is 100 nm;
the buffer layer is made of Al-doped ZnO, and the thickness of the buffer layer is 15 nm;
the transparent conductive film b is made of FTO, and the thickness of the FTO is 50 nm;
the material of the antireflection layer is Si3N4And the thickness is 80 nm.
Preferably, the thickness of the composite junction is 1-10 nm.
Preferably, the battery of the present invention has a structure comprising:
the solar cell comprises a crystalline silicon cell, a composite junction and a perovskite cell, wherein the composite junction is arranged between the crystalline silicon cell and the perovskite cell;
the crystalline silicon battery comprises a transparent conductive film a,p+poly-Si layer, tunneling layer SiOxCrystalline silicon substrate and tunneling layer SiOxAnd n+A poly-Si layer;
the first tunneling layer SiOxThe second tunneling layer SiO is arranged on the first surface of the crystal silicon substratexThe second surface of the crystal silicon substrate is oppositely arranged with the first surface of the crystal silicon substrate, and p+A poly-Si layer arranged on the SiO of the first tunneling layerxA surface far away from the crystal silicon substrate, n+A poly-Si layer arranged on the SiO of the second tunneling layerxAnd between said recombination junctions, in said p+The poly-Si layer is far away from the SiO of the tunneling layerxA transparent conductive film a is laminated on the other side of the substrate;
the second surface of the crystalline silicon substrate is a suede surface, or both the first surface and the second surface are suede surfaces;
the perovskite battery comprises a hole transport layer, a perovskite layer, an electron transport layer, a buffer layer transparent conductive film b and an antireflection layer; the hole transport layer is arranged on one surface, far away from the crystalline silicon battery, of the recombination junction, the perovskite layer is arranged on the first surface of the electron transport layer, the buffer layer is arranged on the second surface of the electron transport layer, the surface, far away from the electron transport layer, of the perovskite layer is the hole transport layer, the first surface and the second surface of the electron transport layer are oppositely arranged, the second surface side, far away from the electron transport layer, of the buffer layer is provided with a transparent conductive film b, and the surface, far away from the electron transport layer, of the transparent conductive film b is provided with an antireflection layer.
Preferably, electrodes are respectively arranged on the outer surface of the transparent conductive film a and the outer surface of the antireflection layer;
further preferably, the electrode material in the invention is one or more of gold (Au), silver (Ag), copper (Cu), aluminum (Al) and nickel (Ni), and the thickness is 100-500 nm.
Another object of the present invention is to provide a method for manufacturing a solar cell according to the present invention, comprising:
preparing a crystalline silicon battery comprising a crystalline silicon substrate, wherein at least one surface of the crystalline silicon substrate is a textured surface;
preparing nc-Si: H (p) on the surface of the crystalline silicon battery close to one side of the suede of the crystalline silicon substrate+)/nc-Si:H(n+) The composite junction of (1);
and preparing the perovskite battery on the composite junction.
Preferably, the manufacturing of the crystalline silicon cell includes:
etching the silicon wafer by using an alkaline solution to obtain the crystalline silicon substrate with one surface or two opposite surfaces being suede;
preparing a first tunneling layer SiO on the first surface of the crystalline silicon substrate by adopting a nitric acid oxidation method, an ozone oxidation method, a steam oxidation method or a thermal oxidation methodxPreparing SiO on the second surface and the second tunneling layerxThe first surface of the crystal silicon substrate is a surface far away from the composite junction, and the second surface is a suede surface and is close to the surface of the composite junction;
SiO in the first tunneling layer by low-pressure chemical vapor depositionxSurface deposition of a layer p+poly-Si layer, SiO layer in the second tunneling layerxSurface deposition of a layer n+A poly-Si layer;
and annealing the battery to obtain the crystalline silicon battery.
Preferably, in p+And depositing a transparent conductive film a on the surface of the poly-Si layer by magnetron sputtering.
The method has simple steps, and the SiO is preparedxThe thickness of the layer is appropriate and meets the requirement; p deposited by low pressure chemical vapor deposition+The poly-Si layer is more compact and uniform.
Preferably, the strong alkali solution is potassium hydroxide or sodium hydroxide solution with the concentration of 10-15%;
more preferably, in the nitric acid oxidation method, the concentration of nitric acid is 10 to 20 percent;
further preferably, the temperature of oxidation is 200-500 ℃ by the thermal oxidation method;
further preferably, the annealing temperature is 850-.
Preferably, the gas phase is plasma-enhanced chemicalA deposition method (plasma chemical vapor deposition PECVD) on the silicon crystal cell near n+The outer surface of the poly-Si layer is laminated with nc-Si: H (p)+)/nc-Si:H(n+) The composite junction of (1).
Preferably, preparing the perovskite battery comprises:
preparing a hole transport layer on the recombination junction;
depositing a lead or cesium halide on the surface of the hole transport layer by a co-evaporation method;
spin coating methylamine or formamidine halide on the surface of the hole transport layer by adopting a spin coating method;
annealing the structure to obtain a perovskite layer;
and sequentially preparing an electron transport layer and a buffer layer on the perovskite layer.
Preferably, the transparent conductive film b and the antireflection layer are sequentially prepared on the surface of the buffer layer.
Preferably, the annealing temperature is 100-.
The perovskite layer is prepared by adopting a two-step method, and the perovskite layer prepared on the concave-convex suede surface is free of accumulation and pores and is more compact and uniform.
Preferably, the hole transport layer is prepared by a solution spin coating method, a thermal evaporation method, a co-evaporation method or a vapor deposition method;
preparing an electron transmission layer by adopting a thermal evaporation method, preparing a buffer layer by adopting an atomic layer deposition method, preparing a transparent conductive film b by adopting a magnetron sputtering method, and preparing an antireflection layer by adopting the thermal evaporation method.
As a preferable scheme, the preparation method of the battery of the invention comprises the following steps:
etching the silicon wafer by using an alkaline solution to obtain the crystalline silicon substrate with one surface or two opposite surfaces being suede;
preparing a first tunneling layer SiO on the first surface of the crystalline silicon substrate by adopting a nitric acid oxidation method, an ozone oxidation method, a steam oxidation method or a thermal oxidation methodxPreparing SiO on the second surface and the second tunneling layerxThe first surface of the crystal silicon substrate is far away from the compoundThe second surface is a suede surface and is close to the composite junction;
SiO in the first tunneling layer by low-pressure chemical vapor depositionxSurface deposition of a layer p+poly-Si layer, SiO layer in the second tunneling layerxSurface deposition of a layer n+A poly-Si layer;
annealing the battery;
at p+A transparent conductive film a is arranged on the surface of the poly-Si layer through magnetron sputtering;
by PECVD method, at said n+The surface preparation material of the poly-Si layer is nc-Si: H (p)+)/nc-Si:H(n+) The composite junction of (1);
preparing a hole transport layer on the recombination junction;
depositing a lead or cesium halide on the surface of the hole transport layer by a co-evaporation method;
spin coating methylamine or formamidine halide on the surface of the hole transport layer by adopting a spin coating method;
annealing the structure to obtain a perovskite layer;
preparing an electron transport layer and a buffer layer on the perovskite layer in sequence;
and sequentially preparing a transparent conductive film b and an antireflection layer on the surface of the buffer layer.
More preferably, the strong alkali solution is a potassium hydroxide or sodium hydroxide solution with the concentration of 10-15%;
in the nitric acid oxidation method, the concentration of nitric acid is 10-20%;
in the thermal oxidation method, the oxidation temperature is 200-500 ℃;
preparation completion n+The annealing temperature after the poly-Si layer is 850-1200 ℃.
After the perovskite layer is prepared, the annealing temperature is 100-200 ℃.
Preparing a hole transport layer by adopting a solution spin coating method, a thermal evaporation method, a co-evaporation method or a vapor deposition method;
preparing an electron transmission layer by adopting a thermal evaporation method, preparing a buffer layer by adopting an atomic layer deposition method, preparing a transparent conductive film b by adopting a magnetron sputtering method, and preparing an antireflection layer by adopting the thermal evaporation method.
The invention has the following beneficial effects:
1) the laminated cell can improve the efficient and sufficient absorption of solar spectrum, realizes that the perovskite thin film absorbs light with the wavelength of 300-750nm, and the crystalline silicon absorbs light with the wavelength of 750-1200nm, thereby enabling the laminated cell to have a wider spectral response value;
2) the laminated cell is of a suede structure, so that light reflection can be effectively reduced, spectral absorption efficiency and current density are increased, photoelectric conversion efficiency is improved, the composite junction material can ensure that the composite cell has an ideal layered structure, and the conductive efficiency of the cell is further improved.
Drawings
Fig. 1 is a schematic diagram of a perovskite/crystalline silicon tandem cell structure.
Wherein 1 is a p-type crystalline silicon substrate, and 2 is a first tunneling layer SiOxAnd 3 is a second tunneling layer SiOxAnd 4 is p+A poly-Si layer, 5 being n+A poly-Si layer 6 is a transparent conductive film a; 7 is a composite junction, 8 is a hole transport layer, 9 is a perovskite layer, 10 is an electron transport layer, 11 is a buffer layer, 12 is a transparent conductive film b, and 13 is an antireflection film; 14 is a front electrode; and 15, a back electrode.
Detailed Description
The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Example 1
The embodiment relates to a perovskite/crystalline silicon tandem solar cell, the specific structure of which is shown in figure 1:
the solar cell comprises a crystalline silicon cell, a composite junction and a perovskite cell, wherein the composite junction 7 is arranged between the crystalline silicon cell and the perovskite cell;
the crystalline silicon battery comprises a crystalline silicon substrate 1 and transparent conductive films a 6 and p+poly-Si layer 4, first tunneling layer SiO x2. Second tunneling layer SiO x3. And said n+A poly-Si layer 5;
the first tunneling layer SiOxIs provided withThe second tunneling layer SiO is arranged on the first surface of the crystal silicon substratexThe second surface of the crystal silicon substrate is oppositely arranged with the first surface of the crystal silicon substrate, and p+A poly-Si layer arranged on the SiO of the first tunneling layerxA surface far away from the crystal silicon substrate, n+A poly-Si layer arranged on the SiO of the second tunneling layerxAnd between said recombination junctions, in said p+The poly-Si layer is far away from the SiO of the tunneling layerxThe other side of the crystal silicon substrate is laminated with a transparent conductive film a, and the first surface and the second surface of the crystal silicon substrate are both suede surfaces.
The transparent conductive film a is made of ITO with the thickness of 110nm and p+The thickness of the poly-Si layer is 150nm, and the first and second tunneling layers are SiOxHas a thickness of 1.7nm, a thickness of the crystalline silicon substrate of 240mm, n+The thickness of the poly-Si layer was 150 nm.
The perovskite battery comprises a hole transport layer 8, a perovskite layer 9, an electron transport layer 10, a buffer layer 11, a transparent conductive film b 12 and an antireflection layer 13; the hole transport layer is arranged on one surface, far away from the crystalline silicon battery, of the recombination junction, the perovskite layer is arranged on the first surface of the electron transport layer, the buffer layer is arranged on the second surface of the electron transport layer, the surface, far away from the electron transport layer, of the perovskite layer is the hole transport layer, the first surface and the second surface of the electron transport layer are oppositely arranged, the second surface side, far away from the electron transport layer, of the buffer layer is provided with a transparent conductive film b, and the surface, far away from the electron transport layer, of the transparent conductive film b is provided with an antireflection layer.
The hole transport layer is Spiro-OMeTAD, and the thickness of the hole transport layer is 300 nm;
the perovskite layer is made of Cs0.5FA0.5Pb(I,Br)3The thickness is 350 nm.
The material of the electron transport layer is LiF/C60The thickness of the film is 80 nm;
the buffer layer is made of SnO2The thickness of the film is 10 nm;
the transparent conductive film b is made of IZO and has a thickness of 100 nm;
the material of the antireflection layer is MgF2The thickness is 100 nm.
And respectively arranging a front electrode 14 and a back electrode 15 on the outer surface of the transparent conductive film a and the outer surface of the antireflection layer, wherein the electrodes are made of Ag and have the thickness of 150 nm.
The above is a specific embodiment of the present invention, which is not intended to limit the present invention, and the same layered structure as the above embodiment is included, which is the scope of the present invention.
In another alternative example, the second surface (i.e. the surface near the composite junction only) of the crystalline silicon substrate is a textured structure;
alternatively, the perovskite layer material may be replaced with MAPbI3。
Alternatively, the material of the transparent conductive film may be replaced with AZO.
And Ag electrodes are respectively arranged on the outer surface of the transparent conductive film a and the outer surface of the antireflection layer, and the thicknesses of the Ag electrodes and the antireflection layer are 150 nm.
Example 2
The present embodiment relates to a perovskite/crystalline silicon tandem solar cell, which has the same layered structure as that of embodiment 1, and is different only in specific selection of materials and thickness of each layer, specifically:
the transparent conductive film a is made of ITO, and the thickness of the transparent conductive film a is 180nm and p+The thickness of the poly-Si layer is 100nm, and the first and second tunneling layers are SiOxHas a thickness of 1.5nm, a thickness of the crystalline silicon substrate of 260 microns, n+The thickness of the poly-Si layer was 100 nm.
The hole transport layer is PEDOT-PSS, and the thickness of the hole transport layer is 400 nm;
the perovskite layer is made of MAPbI3The thickness was 450 nm.
The electron transport layer is made of PCBM, and the thickness of the PCBM is 100 nm;
the buffer layer is made of TiO2The thickness of the film is 15 nm;
the transparent conductive film b is made of FTO, and the thickness of the FTO is 50 nm;
the material of the antireflection layer is Si3N4The thickness was 85 nm.
And respectively arranging Cu electrodes on the outer surface of the transparent conductive film a and the outer surface of the antireflection layer, wherein the thicknesses of the Cu electrodes and the antireflection layer are all 180 nm.
Example 3
The present embodiment relates to a perovskite/crystalline silicon tandem solar cell, which has the same layered structure as that of embodiment 1, and is different only in specific selection of materials and thickness of each layer, specifically:
the transparent conductive film a is made of ITO, and the thickness of the transparent conductive film a is 180nm and p+The thickness of the poly-Si layer is 200nm, and the first and second tunneling layers are SiOxThe thickness of the silicon substrate is 1.8nm, the thickness of the crystalline silicon substrate is 280nm, n+The thickness of the poly-Si layer was 200 nm.
The hole transport layer is NiO, and the thickness of the hole transport layer is 200 nm;
the perovskite layer is made of MAPbBr3The thickness is 400 nm.
The electron transport layer is made of PCBM, and the thickness of the PCBM is 100 nm;
the buffer layer is made of Al-doped ZnO, and the thickness of the buffer layer is 15 nm;
the transparent conductive film b is made of FTO, and the thickness of the FTO is 50 nm;
the material of the antireflection layer is Si3N4And the thickness is 80 nm.
And respectively arranging Al electrodes on the outer surface of the transparent conductive film a and the outer surface of the antireflection layer, wherein the thicknesses of the Al electrodes are 200 nm.
In a specific embodiment of the present invention, there is also provided a method of manufacturing a solar cell, which can be used to manufacture the solar cells of the above-described examples 1, 2 and 3.
Example 4
This example relates to a method of making the cell of example 1, comprising the steps of:
1) taking an n-type silicon wafer with the thickness of 240 microns, cleaning the n-type silicon wafer in an ultrasonic container by using a cleaning solution, and then sequentially cleaning the n-type silicon wafer for ten minutes by using deionized water, acetone and ethanol;
2) texturing the first surface and the second surface of the cleaned silicon wafer by using a KOH solution with the concentration of 15% to form a crystal silicon substrate with a pyramid structure;
3) putting a crystalline silicon substrate into an oxidation furnace tube, performing thermal oxidation by using high-purity oxygen at the temperature of 400 ℃, and preparing a first tunneling layer SiO with the thickness of 1.7nm on the first surface of the crystalline silicon substratexPreparing a second tunneling layer SiO with the thickness of 1.7nm on the second surfacex；
4) SiO in the first tunneling layer by Low Pressure Chemical Vapor Deposition (LPCVD)xSurface deposition of p+A poly-Si layer on the first tunneling layer SiOxSurface deposition of n+The thickness of the poly-Si layer is 150nm, and then annealing is carried out, wherein the annealing temperature is 980 ℃;
5) on the back side (p) of the crystalline silicon substrate+poly-Si layer) is formed, and a layer of transparent conductive film ITO with the thickness of 110nm is formed through magnetron sputtering;
6) at n+The poly-Si layer is close to the surface of the crystalline silicon substrate, and a PECVD method is adopted to prepare a nc-Si: H (p +)/nc-Si: H (n +) composite junction with the thickness of 10 nm;
7) preparing a hole transport layer Spiro-OMeTAD on the surface of the composite junction by adopting a solution spin coating method, wherein the thickness of the hole transport layer Spiro-OMeTAD is 300 nm;
8) preparing a perovskite layer on the hole transport layer by adopting a continuous two-step method;
Cs0.5FA0.5Pb(I,Br)3first, PbI is co-evaporated2CsBr is deposited on the surface, in which PbI is provided2The evaporation temperature is 350 ℃, the CsBr evaporation temperature is 450 ℃, and the substrate temperature is 50 ℃; then, adopting a solution spin-coating method to spin FAI and FABr on the surface; finally, annealing is carried out, the annealing temperature is 150 ℃, and the annealing time is 30 minutes;
9) preparing an electron transport layer LiF/C on the perovskite layer by adopting a thermal evaporation method in sequence60The thickness is 80 nm; preparation of buffer layer SnO by adopting atomic layer deposition method2The thickness is 10 nm; preparing transparent conductive film IZO with the thickness of 100nm by a magnetron sputtering method; thermal evaporation methodPreparing an antireflection layer MgF2The thickness is 100 nm;
10) and finally preparing Ag electrodes with the thickness of 150nm on two sides of the laminated cell by adopting an evaporation method.
Example 5
This example relates to a method of making the cell of example 2, comprising the steps of:
1) taking an n-type silicon wafer with the thickness of 260 microns, cleaning the n-type silicon wafer in an ultrasonic container by using a cleaning solution, and then sequentially cleaning the n-type silicon wafer for ten minutes by using deionized water, acetone and ethanol;
2) putting the cleaned silicon wafer into a 10% NaOH solution, and texturing the first surface and the second surface of the cleaned silicon wafer to form a crystal silicon substrate with a pyramid structure;
3) oxidizing the surface of the crystalline silicon by using high-pressure steam, and preparing a tunneling layer SiO with the thickness of 1.5nm on the first surfacexPreparing a second tunneling SiO film with a thickness of 1.5nm on the second surfacex；
4) SiO in the first tunneling layer by Low Pressure Chemical Vapor Deposition (LPCVD)xSurface preparation of (p)+poly-Si layer, SiO layer in the second tunneling layerxSurface preparation of (1)+The thickness of the poly-Si layer is 100nm, and then annealing is carried out, wherein the annealing temperature is 1000 ℃;
5) on the back side (p) of the crystalline silicon substrate+poly-Si layer) is formed, and a layer of transparent conductive film ITO with the thickness of 180nm is formed through magnetron sputtering;
6) at n+The poly-Si layer is close to the surface of the crystalline silicon substrate, and a PECVD method is adopted to prepare a nc-Si: H (p +)/nc-Si: H (n +) composite junction with the thickness of 8 nm;
7) preparing a hole transport layer PEDOT-PSS with the thickness of 400nm on the surface of the composite junction by adopting a solution spin-coating method;
8) preparing perovskite MAPbI on hole transport layer by continuous two-step method3First, PbI is evaporated by thermal evaporation2Deposited on the surface, in which PbI is provided2The evaporation temperature is 350 ℃, and the substrate temperature is 50 ℃; then, adopting a solution spin-coating method to spin the MAI on the surface; finally, annealing is carried out, wherein the annealing temperature is 200 ℃, and the annealing time is 20 minutes;
9) on the perovskite layerPreparing an electron transport layer PCBM with a thickness of 100nm by adopting a thermal evaporation method in sequence; preparing buffer layer TiO by adopting atomic layer deposition method2The thickness is 15 nm; preparing a transparent conductive film FTO with the thickness of 50nm by a magnetron sputtering method; preparation of antireflection layer Si by thermal evaporation method3N4The thickness is 85 nm;
10) and finally, preparing Cu electrodes with the thickness of 180nm on two sides of the laminated cell by adopting an evaporation method.
Example 6
This example relates to a method of making the cell of example 3, comprising the steps of:
1) taking an n-type silicon wafer with the thickness of 280 microns, cleaning the n-type silicon wafer in an ultrasonic container by using a cleaning solution, and then sequentially cleaning the n-type silicon wafer for ten minutes by using deionized water, acetone and ethanol;
2) etching the first surface and the second surface of the cleaned silicon wafer by adopting a NaOH solution with the concentration of 10% to form a crystal silicon substrate with a pyramid structure;
3) oxidizing a crystalline silicon substrate by ozone, and forming a first tunneling layer SiO with the thickness of 1.8nm on the first surface of the crystalline silicon substratexForming a second tunneling layer SiO with the thickness of 1.8nm on the second surface of the crystal silicon substratex；
4) Using Low Pressure Chemical Vapor Deposition (LPCVD) to form SiO layer on the first tunneling layerxSurface deposition of p+poly-Si layer, SiO layer in the second tunneling layerxSurface deposition of (2)+The thickness of the poly-Si layer is 200nm, and then annealing is carried out, wherein the annealing temperature is 850 ℃;
5) on the back side (p) of the crystalline silicon substrate+poly-Si layer) is formed, and a layer of transparent conductive film ITO with the thickness of 180nm is formed through magnetron sputtering;
6) at n+The poly-Si layer is close to the surface of the crystalline silicon substrate, and a PECVD method is adopted to prepare a nc-Si: H (p +)/nc-Si: H (n +) composite junction with the thickness of 6 nm;
7) preparing a hole transport layer NiO on the surface of the composite junction by adopting a vapor deposition method, wherein the thickness of the hole transport layer NiO is 200 nm;
8) preparing perovskite layer MAPbBr on hole transport layer by continuous two-step method3First, PbBr is evaporated by thermal evaporation2Deposited on the surface, in which PbBr is arranged2The evaporation temperature is 320 ℃, and the substrate temperature is 50 ℃; then, adopting a solution spin-coating method to spin MABr on the surface; finally, annealing is carried out, wherein the annealing temperature is 120 ℃, and the annealing time is 60 minutes;
9) preparing an electron transport layer PCBM on the perovskite layer by a thermal evaporation method in sequence, wherein the thickness of the electron transport layer PCBM is 100 nm; preparing Al-doped ZnO buffer layer with thickness of 15nm by using an atomic layer deposition method; preparing a transparent conductive film FTO with the thickness of 50nm by a magnetron sputtering method; preparation of antireflection layer Si by thermal evaporation method3N4The thickness is 80 nm;
10) and finally preparing Al electrodes with the thickness of 200nm on two sides of the laminated cell by adopting an evaporation method.
The above examples of the preparation method should not be construed as limiting the present invention, as long as the core steps in the preparation method of the present invention are involved, such as preparing tunneling SiO on both sides of the silicon wafer by ozone oxidation, water vapor oxidation or thermal oxygen oxidation (temperature 200-xThe layer is prepared by a PECVD method to prepare nc-Si: H (p +)/nc-Si: H (n +), and the perovskite layer is prepared by a two-step method, which are all the protection ranges of the invention. And examples 1 to 3 relate to SiOxThe method of layer preparation can also be substituted between the different embodiments.
Comparative example 1
The difference from example 1 is that the step does not provide a tunneling layer nc-Si: H (p +)/nc-Si: H (n +) recombination junction, and a transparent conductive film ITO layer is provided.
Examples of the experiments
The experimental example relates to the determination of the battery performance, and adopts an I-V test method and test conditions: at 25 ℃, AM1.5G, 100mW cm～2(ii) a The main test equipment: the efficiency of the cell was measured using a solar simulator, standard silicon detector, Keithley 2400 source meter, IV tester, etc. The specific test results are shown in table 1:
TABLE 1
Figure BDA0001815987900000161
As can be seen from the data in the above table, the photoelectric conversion efficiency of the perovskite/crystalline silicon tandem cell in examples 1, 2 and 3 is greatly improved compared with that of the existing monocrystalline silicon high efficiency cell. The perovskite cell and the crystalline silicon cell have the forbidden band width distribution which keeps better matching with the spectrum of the solar cell, and the composite junction can lead the perovskite cell and the crystalline silicon cell to be combined ideally, so that the solar spectrum can be better utilized compared with a monocrystalline silicon high-efficiency cell, and the efficiency of the laminated cell based on the structure can be improved to more than 26 percent.
Although the invention has been described in detail hereinabove by way of general description, specific embodiments and experiments, it will be apparent to those skilled in the art that many modifications and improvements can be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (15)

1. The perovskite/crystalline silicon tandem solar cell is characterized by comprising a crystalline silicon cell, a composite junction and a perovskite cell, wherein the composite junction is arranged between the crystalline silicon cell and the perovskite cell, the crystalline silicon cell comprises a crystalline silicon substrate, one surface of the crystalline silicon substrate, which is close to the composite junction, is a suede surface, and the composite junction is made of nc-Si: H (p+)/nc-Si:H(n+)。
2. The solar cell of claim 1, wherein the crystalline silicon cell further comprises p+poly-Si layer, first tunneling layer SiOxA second tunneling layer SiOxAnd n+A poly-Si layer, the first tunneling layer SiOxThe second tunneling layer SiO is arranged on the first surface of the crystal silicon substratexThe second surface of the crystal silicon substrate is oppositely arranged with the first surface of the crystal silicon substrate, and p+A poly-Si layer arranged on the SiO of the first tunneling layerxA surface far away from the crystal silicon substrate, n+A poly-Si layer arranged on the SiO of the second tunneling layerxAnd between the composite junctions.
3. The solar cell of claim 2, wherein the first surface of the crystalline silicon substrate is textured.
4. The solar cell of claim 2 or 3, wherein the tunneling layer is SiOxThe thickness of (A) is 1.0-2.0 nm; and/or, said n+The thickness of the poly-Si layer is 100 to 300nm, and/or, the p+The thickness of the poly-Si layer is 100 to 300 nm.
5. The solar cell according to any one of claims 1 to 4, wherein the perovskite cell comprises a hole transport layer, a perovskite layer, an electron transport layer and a buffer layer; the hole transport layer is arranged on one surface, far away from the crystalline silicon battery, of the composite junction, the perovskite layer is arranged on the first surface of the electron transport layer, the buffer layer is arranged on the second surface of the electron transport layer, the hole transport layer is arranged on one surface, far away from the electron transport layer, of the perovskite layer, and the first surface and the second surface of the electron transport layer are arranged oppositely.
6. The solar cell of claim 5, wherein the buffer layer is made of titanium dioxide or tin dioxide or aluminum-doped zinc oxide.
7. The solar cell according to claim 5 or 6, characterized in that the band gap of the perovskite layer material is 1.5-1.75 eV.
8. The solar cell according to any one of claims 5 to 7, wherein the perovskite layer is formed of MAPbI3Or MAPbBr3Or CsxFA1-xPb(I,Br)3，0≤x≤0.5。
9. The solar cell according to any one of claims 1 to 8, wherein the thickness of the recombination junction is 1 to 10 nm.
10. A method of fabricating a perovskite/crystalline silicon tandem solar cell, the method comprising:
preparing a crystalline silicon battery comprising a crystalline silicon substrate, wherein at least one surface of the crystalline silicon substrate is a textured surface;
preparing nc-Si: H (p) on the surface of the crystalline silicon battery close to one side of the suede of the crystalline silicon substrate+)/nc-Si:H(n+) The composite junction of (1);
and preparing the perovskite battery on the composite junction.
11. The method of claim 10, wherein preparing the crystalline silicon cell comprising the crystalline silicon substrate comprises:
etching the silicon wafer by using an alkaline solution to obtain the crystalline silicon substrate with one surface or two opposite surfaces being suede;
preparing a first tunneling layer SiO on the first surface of the crystalline silicon substrate by adopting a nitric acid oxidation method, an ozone oxidation method, a steam oxidation method or a thermal oxidation methodxPreparing a second tunneling layer SiO on the second surfacexThe first surface of the crystal silicon substrate is a surface far away from the composite junction, and the second surface is a suede surface and is close to the composite junction;
SiO in the first tunneling layer by low-pressure chemical vapor depositionxSurface deposition of a layer p+poly-Si layer, SiO layer in the second tunneling layerxSurface deposition of a layer n+A poly-Si layer;
and annealing the battery to obtain the crystalline silicon battery.
12. The method according to claim 10 or 11, wherein the surface preparation material of the crystalline silicon battery on the side close to the suede of the crystalline silicon substrate is nc-Si: H (p)+)/nc-Si:H(n+) The composite knot of (1), comprising:
the material prepared by adopting a plasma enhanced chemical vapor deposition method is nc-Si: H (p)+)/nc-Si:H(n+) The composite junction of (1).
13. The method according to any one of claims 10 to 12, wherein preparing the perovskite battery comprises:
preparing a hole transport layer on the recombination junction;
depositing a lead or cesium halide on the surface of the hole transport layer by a co-evaporation method;
spin coating methylamine or formamidine halide on the surface of the hole transport layer by adopting a spin coating method;
annealing the structure to obtain a perovskite layer;
and sequentially preparing an electron transport layer and a buffer layer on the perovskite layer.
14. The method as claimed in claim 13, wherein the annealing temperature is 100-200 ℃.
15. The method according to claim 11, wherein the alkaline solution is a 10-15% strength potassium hydroxide or sodium hydroxide solution;
and/or, in the nitric acid oxidation method, the concentration of nitric acid is 10-20%;
and/or the temperature of oxidation is 200-500 ℃ by the thermal oxidation method;
and/or the annealing temperature is 850-.
CN201811141867.3A 2018-09-28 2018-09-28 Perovskite/crystalline silicon laminated solar cell and preparation method thereof Pending CN110970562A (en)

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