CN111540791A - Solar cell and manufacturing method thereof - Google Patents
Solar cell and manufacturing method thereof Download PDFInfo
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- CN111540791A CN111540791A CN202010387616.4A CN202010387616A CN111540791A CN 111540791 A CN111540791 A CN 111540791A CN 202010387616 A CN202010387616 A CN 202010387616A CN 111540791 A CN111540791 A CN 111540791A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0687—Multiple junction or tandem solar cells
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
- H10K30/10—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising heterojunctions between organic semiconductors and inorganic semiconductors
- H10K30/15—Sensitised wide-bandgap semiconductor devices, e.g. dye-sensitised TiO2
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E10/546—Polycrystalline silicon PV cells
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- Y02E10/00—Energy generation through renewable energy sources
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- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Computer Hardware Design (AREA)
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- Sustainable Development (AREA)
- Manufacturing & Machinery (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention relates to a solar cell comprising a bottom cell and a top cell, wherein the bottom cell comprises: a substrate; the emitter layer is arranged on the surface of the substrate; the tunneling oxide layer is arranged on the back surface of the substrate; the polycrystalline silicon layer is arranged on the surface of the tunneling oxide layer; the front passivation layer is arranged on the surface of the emitter layer; the back passivation layer is arranged on the surface of the polycrystalline silicon layer; the back electrode is arranged on the surface of the back passivation layer; wherein at least a portion of the emitter layer is not in contact with the front passivation layer, and at least a portion of the back electrode penetrates through the back passivation layer and is in contact with the polysilicon layer.
Description
Technical Field
The invention relates to a solar cell, which has a wider spectral response range, higher photoelectric conversion efficiency, simple process and lower cost.
Background
The theoretical photoelectric conversion efficiency of the crystalline silicon solar cell technology, which is taken as the leading force of the photovoltaic market, is close to the limit after years of development. The method takes the crystalline silicon solar cell as a substrate to prepare the solar cell with the two laminated ends, and is an effective way for improving the efficiency of a photovoltaic device and reducing the cost of a photovoltaic system.
The inorganic-organic halide perovskite solar cell has achieved breakthrough progress in the last decade by virtue of the advantages of high light absorption coefficient, high carrier mobility, adjustable band gap, simple preparation, low cost and the like. The perovskite solar cell with wide band gap is prepared by taking the crystalline silicon solar cell as a substrate, so that the solar cell with two laminated ends is formed, the spectral response range of the device can be widened, and the energy conversion efficiency of the device is effectively improved. Currently, the tandem solar cell with such a structure mainly adopts a heterojunction silicon solar cell technology, such as a tandem solar cell with an hit (heterojunction with Intrinsic thin layer) structure. However, the technology still has the problems of high production equipment and manufacturing cost and the like.
Disclosure of Invention
The invention aims to provide a solar cell, which has a wider spectral response range, higher photoelectric conversion efficiency, simple process and lower cost.
The present invention adopts a technical solution to solve the above technical problems, and provides a solar cell, including a bottom cell and a top cell, wherein the bottom cell includes: a substrate; the emitter layer is arranged on the surface of the substrate; the tunneling oxide layer is arranged on the back surface of the substrate; the polycrystalline silicon layer is arranged on the surface of the tunneling oxide layer; the front passivation layer is arranged on the surface of the emitter layer; the back passivation layer is arranged on the surface of the polycrystalline silicon layer; the back electrode is arranged on the surface of the back passivation layer; wherein at least a portion of the emitter layer is not in contact with the front passivation layer, and at least a portion of the back electrode penetrates through the back passivation layer and is in contact with the polysilicon layer.
In an embodiment of the invention, the tunneling oxide layer includes silicon oxide and has a thickness of 1-15 nm.
In an embodiment of the invention, the material of the polysilicon layer comprises phosphorus-doped polysilicon, and the thickness is 10-1000 nm.
In one embodiment of the invention, the material of the substrate comprises N-type monocrystalline silicon, and the resistivity is 0.1-20ohm cm; the emitter layer is boron doped.
In an embodiment of the present invention, the solar cell further includes a composite layer disposed on a surface of the bottom cell, the top cell is connected to the bottom cell through the composite layer, and the top cell includes: the electron transmission layer is arranged on the surface of the composite layer; the perovskite layer is arranged on the surface of the electron transport layer; the hole transport layer is arranged on the surface of the perovskite layer; the electrode buffer layer is arranged on the surface of the hole transport layer; the transparent electrode layer is arranged on the surface of the electrode buffer layer; the front electrode is arranged on the surface of the transparent electrode layer; and an antireflection layer provided on a surface of the transparent electrode layer in a region not in contact with the front electrode.
Another aspect of the present invention provides a method for fabricating a solar cell, including forming a bottom cell and a top cell, wherein the step of forming the bottom cell includes: providing a substrate; forming an emitter layer on the surface of the substrate; forming a tunneling oxide layer on the back surface of the substrate; forming a polycrystalline silicon layer on the surface of the tunneling oxide layer; forming a front passivation layer on the surface of the emitter layer; forming a back passivation layer on the surface of the polycrystalline silicon layer; and providing a back electrode on a surface of the back passivation layer; wherein at least a portion of the emitter layer is not in contact with the front passivation layer and at least a portion of the back electrode penetrates the back passivation layer and is in contact with the polysilicon layer; the method of forming the front passivation layer on the surface of the emitter layer includes forming the front passivation layer using an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method, and patterning the front passivation layer to expose at least a portion of the emitter layer; the method for forming the back passivation layer on the surface of the polycrystalline silicon layer comprises an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method; the method for disposing the back electrode on the surface of the back passivation layer includes a thermal evaporation method or a screen printing method.
In an embodiment of the invention, a method of forming the tunnel oxide layer on the back surface of the substrate includes a thermal oxidation method, a wet chemical method, a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, or an atmospheric pressure chemical vapor deposition method; the tunneling oxide layer is made of silicon oxide and has a thickness of 1-15 nm.
In an embodiment of the invention, a method for forming the polysilicon layer on the surface of the tunneling oxide layer includes a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or an atmospheric pressure chemical vapor deposition method; the polycrystalline silicon layer is made of phosphorus-doped polycrystalline silicon and has a thickness of 10-1000 nm.
In one embodiment of the invention, the material of the substrate comprises N-type monocrystalline silicon, and the resistivity is 0.1-20ohm cm; the method of forming the emitter layer on the surface of the substrate includes boron diffusion.
In one embodiment of the present invention, the method further comprises forming a composite layer on a surface of the bottom cell, and forming the top cell on a surface of the composite layer; wherein the step of forming the top cell further comprises: forming an electron transport layer on the surface of the composite layer; forming a perovskite layer on the surface of the electron transport layer; forming a hole transport layer on the surface of the perovskite layer; forming an electrode buffer layer on the surface of the hole transport layer; forming a transparent electrode layer on the surface of the electrode buffer layer; arranging a front electrode on the surface of the transparent electrode layer; and forming an antireflection layer on a region of the surface of the transparent electrode layer not in contact with the front electrode; the method for forming the composite layer on the surface of the bottom battery comprises one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a magnetron sputtering method and a thermal evaporation method; the method for forming the electron transport layer on the surface of the composite layer comprises one or more of a spin coating method, a magnetron sputtering method, a spray pyrolysis method, a thermal evaporation method, an atomic layer deposition method, a blade coating method, a coating method and a printing method; the method for forming the perovskite layer on the surface of the electron transport layer comprises one or more of a spin coating method, a spray pyrolysis method, a thermal evaporation method, a blade coating method, a coating method and a printing method; a method of forming the hole transport layer on the surface of the perovskite layer includes one or more of a spin coating method, a thermal evaporation method, a blade coating method, a coating method, and a printing method; the method for forming the electrode buffer layer on the surface of the hole transport layer comprises one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a spin coating method, a sputtering method and a thermal evaporation method; the method for forming the transparent electrode layer on the surface of the electrode buffer layer comprises one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a spin coating method, a sputtering method and a thermal evaporation method; the method for arranging the front electrode on the surface of the transparent electrode layer comprises a thermal evaporation method or a screen printing method; the method of forming the anti-reflection layer on the surface of the transparent electrode layer in the region not in contact with the front electrode includes one or more of evaporation, sputtering, and atomic layer deposition.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
the solar cell of the invention can play a good passivation effect by sequentially arranging the tunneling oxide layer and the polysilicon layer on the back surface of the substrate. The solar cell has the advantages of wide spectral response range, high photoelectric conversion efficiency, simple process and low cost.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the invention;
fig. 2 is a flowchart of a method for fabricating a solar cell according to an embodiment of the invention;
fig. 3 is a flowchart of forming a top cell according to a method for manufacturing a solar cell of an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, references to the structure of a first feature being "on/under" or "over/under" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
In order to overcome the defects in the prior art, the following embodiments of the present invention provide a solar cell, which has a wider spectral response range and higher photoelectric conversion efficiency, and is simple in process and low in cost.
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the invention. The structure of the solar cell will be described with reference to fig. 1. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Referring to fig. 1, a solar cell 100 includes a bottom cell 110 and a top cell 120. The bottom cell 110 includes a substrate 111, an emitter layer 112, a tunnel oxide layer 113, a polysilicon layer 114, a front passivation layer 115, a back passivation layer 116, and a back electrode 117.
The emitter layer 112 is disposed on the surface of the substrate 111. The tunnel oxide layer 113 is disposed on the back surface of the substrate 111. The polysilicon layer 114 is disposed on the surface of the tunnel oxide layer 113. The front passivation layer 115 is disposed on the surface of the emitter layer 112. A backside passivation layer 116 is disposed on the surface of the polysilicon layer 114. The back electrode 117 is provided on the surface of the back passivation layer 116. Wherein at least a portion of the emitter layer 112 is not in contact with the front passivation layer 115 and at least a portion of the back electrode 117 penetrates the back passivation layer 116 and is in contact with the polysilicon layer 114.
The substrate 111 may be made of various semiconductor materials (e.g., silicon Si). In one embodiment of the present invention, the material of the substrate 111 includes N-type single crystal silicon.
In some examples, the resistivity of the substrate 111 may be 0.1-20 ohm-cm.
Illustratively, an N-type single crystal silicon wafer may be pre-treated and/or surface topographically processed to form the substrate 111. In some embodiments, the pretreatment process further comprises polishing, and the surface of the substrate 111 is a polished surface, but the invention is not limited thereto.
In one embodiment of the present invention, the emitter layer 112 is boron doped. For example, a substrate 111 of N-type single crystal silicon may be subjected to conventional boron diffusion to form a boron-doped emitter layer 112.
In an embodiment of the present invention, the material of the tunnel oxide layer 113 includes silicon oxide.
In some examples, the tunnel oxide layer 113 may be 1-15nm thick. Preferably, the tunneling oxide layer 113 of silicon oxide has a thickness of 1.5 nm.
In one embodiment of the present invention, the material of the polysilicon layer 114 includes phosphorus doped polysilicon.
In some examples, the thickness of the polysilicon layer 114 may be 10-1000 nm. Preferably, the phosphorus doped polysilicon layer 114 has a thickness of 200 nm.
The material of the front passivation layer 115 and the back passivation layer 116 includes, but is not limited to, a passivation dielectric film material such as silicon nitride. Referring to fig. 1, the front passivation layer 115 on the surface of the emitter layer 112 may be patterned to expose at least a portion of the emitter layer 112.
In one embodiment of the present invention, at least a portion of the back electrode 117 penetrates the back passivation layer 116 and contacts the polysilicon layer 114.
The material of the back electrode 117 may be metal. Illustratively, the material of the back electrode 117 may be one or more of gold (Au), silver (Ag), aluminum (Al), and copper (Cu).
With continued reference to fig. 1, in one embodiment of the invention, the solar cell 100 further includes a composite layer 130. The composite layer 130 is provided on the surface of the bottom cell 110. The top cell 120 is connected to the bottom cell 110 by a composite layer 130. Wherein the top battery 120 includes: an electron transport layer 121, a perovskite layer 122, a hole transport layer 123, an electrode buffer layer 124, a transparent electrode layer 125, a front electrode 126, and an antireflection layer 127.
The electron transport layer 121 is disposed on the surface of the composite layer 130. The perovskite layer 122 is provided on the surface of the electron transport layer 121. The hole transport layer 123 is provided on the surface of the perovskite layer 122. The electrode buffer layer 124 is provided on the surface of the hole transport layer 123. The transparent electrode layer 125 is disposed on a surface of the electrode buffer layer 124. The front electrode 126 is disposed on the surface of the transparent electrode layer 125. The antireflection layer 127 is provided on the surface of the transparent electrode layer 125 in a region not in contact with the front electrode 126.
In one example shown in fig. 1, a composite layer 130 may be provided on the surface of at least a portion of the emitter layer 112 and the front passivation layer 115 of the bottom cell 110.
In one embodiment of the invention, compoundingThe material of layer 130 may be tin oxide (SnO)2) Titanium dioxide (TiO)2) Zinc peroxide (ZnO)2) One or more of Indium Tin Oxide (ITO), fluorine-doped tin oxide (FTO), Indium Zinc Oxide (IZO), and aluminum-doped zinc oxide (AZO). Preferably, the material of the composite layer 130 is tin oxide (SnO)2)。
In some examples, composite layer 130 may be 0-500nm thick.
In an embodiment of the present invention, the material of the electron transport layer 121 may be SnO2、TiO2、ZnO2ITO, FTO, IZO, fullerene and derivatives (C60, C70, PCBM), BaSnO3And one or more of AZO. Preferably, the material of the electron transport layer 121 is tin oxide.
In some examples, the electron transport layer 121 may have a thickness of 0-500 nm.
In one embodiment of the invention, the material of the perovskite layer 122 may be ABX3A compound of the formula (I). Wherein A is selected from potassium (K), cesium (Cs), rubidium (Rb), methylamino (CH)3NH3) Or amidino (CH)2(NH2)2) B may be one or more divalent cations of lead (Pb) and tin (Sn), and X may be one or more monovalent anions of iodine (I), bromine (Br), and chlorine (Cl). It should be understood that the content of each component in the above compounds can be adjusted according to actual needs by those skilled in the art, and the present invention is not limited thereto.
In some examples, the thickness of the perovskite layer 122 may be 100-1000 nm.
In one embodiment of the present invention, the material of the hole transport layer 123 may be Sprio-OMeTAD (2,2',7,7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino)]-9,9' -spirobifluorene), PTAA (polyethylene terephthalate), NiOx、P3HT (polymer of 3-hexylthiophene), PEDOT PSS, CuSCN, CuAlO2And Spiro-TTB.
In some examples, the hole transport layer 123 may have a thickness of 0-500 nm.
In an embodiment of the present invention, the material of the electrode buffer layer 124 may be MoOx、LiF、SnO2、TiO2、SiO2And amorphous silicon.
In some examples, the electrode buffer layer 124 may have a thickness of 0-500 nm. Preferably, the thickness of the electrode buffer layer 124 is 2 nm.
In an embodiment of the invention, the material of the transparent electrode layer 125 may be SnO2、TiO2One or more of IZO, ITO, AZO, graphene and silver nanowires.
In some examples, the thickness of the transparent electrode layer 125 may be 0-500 nm. Preferably, the thickness of the transparent electrode layer 125 is 100 nm.
In an embodiment of the present invention, the material of the front electrode 126 may be metal. Illustratively, the material of the front electrode 126 may be one or more of gold (Au), silver (Ag), aluminum (Al), and copper (Cu).
In some examples, the front electrode 126 may be 0-500nm thick. Preferably, the thickness of the front electrode 126 is 60 nm.
In an embodiment of the invention, the material of the anti-reflection layer 127 may be LiF, MgF2、Si3N4、SiO2And one or more of suede flexible films.
In some examples, the thickness of the antireflective layer 127 may be 0-5 mm. Preferably, the thickness of the antireflective layer 127 is 150 nm.
The solar cell 100 of the present invention has the advantages that the tunnel oxide layer 113 and the polysilicon layer 114 (for example, the tunnel oxide layer 113 of silicon oxide and the polysilicon layer 114 doped with phosphorus) are sequentially disposed on the back surface of the substrate 111, so that a good passivation effect can be achieved, and the cell conversion efficiency is greatly improved. Compared with the heterojunction silicon solar cell technology, the solar cell 100 of the invention not only has a wider spectral response range and higher photoelectric conversion efficiency, but also has simple process and lower cost, and simultaneously has the potential of commercial mass production and wide commercial application prospect.
The above embodiments of the present invention provide a solar cell, which has a wider spectral response range and higher photoelectric conversion efficiency, and is simple in process and low in cost.
The invention provides a manufacturing method of a solar cell, which is suitable for preparing the solar cell with wider spectral response range and higher photoelectric conversion efficiency, and has simple process and lower cost.
The manufacturing method of the solar cell comprises the steps of forming a bottom cell and a top cell. Wherein the step of forming the bottom cell comprises: providing a substrate; forming an emitter layer on the surface of the substrate; forming a tunneling oxide layer on the back surface of the substrate; forming a polycrystalline silicon layer on the surface of the tunneling oxide layer; forming a front passivation layer on the surface of the emitter layer; forming a back passivation layer on the surface of the polycrystalline silicon layer; and disposing a back electrode on a surface of the back passivation layer.
Wherein at least a part of the emitter layer is not in contact with the front passivation layer, and at least a part of the back electrode penetrates through the back passivation layer and is in contact with the polysilicon layer; a method of forming a front passivation layer on a surface of a substrate includes forming the front passivation layer using an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method, and patterning the front passivation layer to expose at least a portion of an emitter layer; the method for forming the back passivation layer on the surface of the polycrystalline silicon layer comprises an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method; methods of providing the back electrode on the surface of the back passivation layer include a thermal evaporation method or a screen printing method.
Fig. 2 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the invention. The manufacturing method will be described with reference to fig. 1 and 2. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
Referring to fig. 1 and 2, the method of fabricating the solar cell includes forming a bottom cell 110 and a top cell 120. Wherein the step of forming the bottom cell 110 comprises:
The substrate 111 may be made of various semiconductor materials (e.g., silicon Si). In one embodiment of the present invention, the material of the substrate 111 includes N-type single crystal silicon.
In some examples, the resistivity of the substrate 111 may be 0.1-20 ohm-cm.
Illustratively, an N-type single crystal silicon wafer may be pre-treated and/or surface topographically processed to form the substrate 111. In some embodiments, the pretreatment process further comprises polishing, and the surface of the substrate 111 is a polished surface, but the invention is not limited thereto.
Preferably, the N-type single crystal silicon wafer may be pretreated by an alkali solution and/or an additive to remove the cutting line mark. The surface is then polished such that the surface of the substrate 111 is a polished surface, but the invention is not limited thereto.
In step 220, an emitter layer 112 is formed on the surface of the substrate 111.
In an embodiment of the present invention, the method of forming the emitter layer 112 on the surface of the substrate 111 includes boron diffusion. For example, a substrate 111 of N-type single crystal silicon may be subjected to conventional boron diffusion to form a boron-doped (boron-doped) emitter layer 112. Preferably, the polished substrate 111 may be subjected to boron diffusion using a diffusion furnace.
In some embodiments of the present invention, step 220 may be followed by removing the borosilicate glass layer from the back side of substrate 111. Preferably, the borosilicate glass layer on the back surface of the substrate 111 may be removed on one side by a chain type cleaning apparatus, but the present invention is not limited thereto.
In step 230, a tunnel oxide layer 113 is formed on the back surface of the substrate 111.
In an embodiment of the present invention, a method of forming the tunnel Oxide layer 113 on the back surface of the substrate 111 includes a thermal oxidation (TGO), a wet Chemical method, a Plasma Enhanced Chemical Vapor Deposition (PECVD), a Low Pressure Chemical Vapor Deposition (LPCVD), or an Atmospheric Pressure Chemical Vapor Deposition (APCVD). Preferably, the tunnel oxide layer 113 may be grown on the back surface of the substrate 111 using a thermal oxidation method.
In an embodiment of the present invention, the material of the tunnel oxide layer 113 includes silicon oxide.
In some examples, the tunnel oxide layer 113 may be 1-15nm thick. Preferably, the tunneling oxide layer 113 of silicon oxide has a thickness of 1.5 nm.
In some embodiments of the present invention, step 230 may also be preceded by a topographical treatment of the backside of substrate 111. Illustratively, the backside of the substrate 111 may be topographically processed using an acid and/or base solution. Preferably, the backside profile treatment can be a single-sided texturing process, but the invention is not limited thereto. In step 240, a polysilicon layer 114 is formed on the surface of the tunnel oxide layer 113.
In an embodiment of the invention, the method for forming the polysilicon layer 114 on the surface of the tunnel oxide layer 113 includes a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or an atmospheric pressure chemical vapor deposition method. Preferably, the polysilicon layer 114 may be deposited on the surface of the tunnel oxide layer 113 by using a low pressure chemical vapor deposition method.
In some embodiments of the present invention, the material of the polysilicon layer 114 comprises phosphorus doped polysilicon.
In some examples, the thickness of the polysilicon layer 114 may be 10-1000 nm. Preferably, the phosphorus doped polysilicon layer 114 has a thickness of 200 nm.
In some embodiments of the present invention, step 240 may also be followed by a high temperature anneal.
It should be noted that in other examples of the present invention, the polysilicon layer 114 in step 240 may also be an intrinsic polysilicon layer. When the polysilicon layer 114 is made of intrinsic polysilicon, the intrinsic polysilicon layer needs to be phosphorus-doped by high-temperature phosphorus diffusion and/or ion implantation in the subsequent process to form the phosphorus-doped polysilicon layer 114. For example, after the high temperature annealing step, the intrinsic polysilicon layer may be subjected to phosphorus diffusion by using a diffusion furnace, but the invention is not limited thereto.
In step 250, a front passivation layer 115 is formed on the surface of the emitter layer 112.
Referring to fig. 1, in an embodiment of the present invention, a method of forming the front passivation Layer 115 on the surface of the emitter Layer 112 includes forming the front passivation Layer 115 using an Atomic Layer Deposition (ALD) method and/or a plasma enhanced chemical vapor Deposition (pecvd) method, and patterning/patterning the front passivation Layer 115 to expose at least a portion of the emitter Layer 112. Illustratively, the front passivation layer 115 may be patterned by laser, Photolithography (Photolithography), slurry etching, or mask.
Preferably, the front passivation layer 115 may be deposited on the surface of the emitter layer 112 by using an atomic layer deposition method and a plasma enhanced chemical vapor deposition method in sequence, and then a portion of the front passivation layer 115 covering the surface of the emitter layer 112 may be patterned and stripped by using a laser to expose at least a portion of the emitter layer 112.
The material of the front passivation layer 115 includes, but is not limited to, a passivation dielectric film material such as silicon nitride.
In some embodiments of the present invention, step 250 may be preceded by cleaning the substrate 111. Preferably, the polycrystalline silicon residue on the surface of the emitter layer 112 may be removed on one side by a chain type cleaning apparatus, and RCA cleaning and dehydration treatment may be performed, but the present invention is not limited thereto.
In step 260, a back passivation layer 116 is formed on the surface of the polysilicon layer 114.
In an embodiment of the present invention, the method of forming the back passivation layer 116 on the surface of the polysilicon layer 114 includes an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method.
Preferably, a back passivation layer 116 may be deposited on the surface of the polysilicon layer 114 using a plasma enhanced chemical vapor deposition method.
The material of the back passivation layer 116 includes, but is not limited to, a passivation dielectric film material such as silicon nitride.
In step 270, a back electrode 117 is disposed on the surface of the back passivation layer 116.
In an embodiment of the present invention, a method of providing the back electrode 117 on the surface of the back passivation layer 116 includes a thermal evaporation method or a screen printing method. Preferably, the back electrode 116 may be provided by a screen printing method.
In one embodiment of the present invention, at least a portion of the back electrode 117 penetrates the back passivation layer 116 and contacts the polysilicon layer 114.
The material of the back electrode 117 may be metal. Illustratively, the material of the back electrode 117 may be one or more of gold (Au), silver (Ag), aluminum (Al), and copper (Cu).
Tunnel oxide layer with continued reference to fig. 1, in an embodiment of the present invention, the method for fabricating the solar cell further includes forming a composite layer 130 on the surface of the bottom cell 110, and forming a top cell 120 on the surface of the composite layer 130.
In one example shown in fig. 1, a composite layer 130 may be formed on the surface of the front passivation layer 115 and at least a portion of the emitter layer 112 of the bottom cell 110.
In an embodiment of the present invention, the method for forming the composite layer 130 on the surface of the bottom cell 110 includes one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a magnetron sputtering method, and a thermal evaporation method.
The material of the composite layer 130 may be SnO2、TiO2、ZnO2One or more of ITO, FTO, IZO and AZO. Preferably, the material of the composite layer 130 is tin oxide (SnO)2)。
In some examples, composite layer 130 may be 0-500nm thick.
Fig. 3 is a flowchart of forming a top cell according to a method for manufacturing a solar cell of an embodiment of the invention. Referring to fig. 3, the step of forming the top cell 120 further includes:
in step 310, an electron transport layer 121 is formed on the surface of the composite layer 130.
In an embodiment of the present invention, the method of forming the electron transport layer 121 on the surface of the composite layer 130 includes one or more of a spin coating method, a magnetron sputtering method, a spray pyrolysis method, a thermal evaporation method, an atomic layer deposition method, a blade coating method, a coating method, and a printing method.
The electron transport layer 121 material may be SnO2、TiO2、ZnO2ITO, FTO, IZO, fullerene and derivatives (C60, C70, PCBM), BaSnO3And one or more of AZO.
In some examples, the electron transport layer 121 may have a thickness of 0-500 nm.
It is to be understood that when the materials of composite layer 130 and electron transport layer 121 are the same, e.g., both are SnO2In this case, the composite layer 130 and the electron transport layer 121 may be simultaneously formed using one process. It is understood, however, that the use of two or more process steps to form the composite layer 130 and the electron transport layer 121, respectively, is still an alternative embodiment in other examples of the invention.
Illustratively, the treatment may be performed for 10 minutes using an ultraviolet light washer. SnO with an Alfa mass fraction of 15% is then used2Aqueous solution, diluted to 5% concentration. 100 microliters of the aqueous solution was dropped thereon and spin-coated on a spin coater at 3000rpm for 30 seconds. And then transferred to a heating stage, and treated at 150 c for 30 minutes to complete the preparation of the composite layer 130 and the electron transport layer 121.
In step 320, a perovskite layer 122 is formed on the surface of the electron transport layer 121.
In an embodiment of the present invention, the method of forming the perovskite layer 122 on the surface of the electron transport layer 121 includes one or more of a spin coating method, a spray pyrolysis method, a thermal evaporation method, a blade method, a coating method, and a printing method.
The material of the perovskite layer 122 may be ABX3A compound of the formula (I). Wherein A is potassium (K), cesium (Cs), rubidium (Rb) and methylamino (CH)3NH3) Or amidino (CH)2(NH2)2) B is one or more divalent cations of lead (Pb) and tin (Sn), and X is one or more monovalent anions of iodine (I), bromine (Br), and chlorine (Cl).
In some examples, the thickness of the perovskite layer 122 may be 100-1000 nm.
Illustratively, the perovskite precursor solution may be prepared by first preparing 232.16mg FAI, 31.92mg CsBr, 414.9mg PbI2And 220.2mg PbBr2Dissolved in a mixed solvent of 800. mu.l DMF and 200. mu.l DMSO, and stirred for 2 hours to completely dissolve.
The perovskite layer 122 may be prepared by a spin coating method using a uv washer for 10 minutes and then transferred to a glove box before the perovskite layer 122 is prepared. 80 microliters of the perovskite precursor solution was dropped thereon, and after 10 seconds of spin coating at 1000rpm, accelerated to 3000rpm, and spin coated for 30 seconds. At this speed, 110. mu.l of chlorobenzene was rapidly added dropwise during 10 seconds of spin coating. After the spin coating is finished, the perovskite layer 122 is prepared by placing the perovskite layer on a heating table at 100 ℃ and carrying out heat treatment for 30 minutes.
In step 330, a hole transport layer 123 is formed on the surface of the perovskite layer 122.
In an embodiment of the present invention, the method of forming the hole transport layer 123 on the surface of the perovskite layer 122 includes one or more of a spin coating method, a thermal evaporation method, a blade coating method, a coating method, and a printing method.
The material of the hole transport layer 123 may be Sprio-OMeTAD (2,2',7,7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino group)]-9,9' -spirobifluorene), PTAA (polyethylene terephthalate), NiOx、P3HT (polymer of 3-hexylthiophene), PEDOT PSS, CuSCN, CuAlO2And Spiro-TTB.
In some examples, the hole transport layer 123 may have a thickness of 0-500 nm.
Illustratively, the preparation of the hole transport layer 123 may be performed in a glove box. First, a 72.3 mg/ml solution of Sprio-OMeTAD was prepared and a 2.9% 300 mg/ml solution of Co (III) salt in acetonitrile was added dropwise. Then, a solution of 2.85% 4-tert-butylpyridine and 1.75% 520 mg/ml of LITFSI acetonitrile was added dropwise and stirred for 3 hours. Thereafter, 30. mu.l of a Spiro-OMeTAD solution was dropped onto the perovskite layer 122, and spin-coating was performed at 4000rpm for 30 seconds, completing the preparation of the hole transport layer 123.
In step 340, an electrode buffer layer 124 is formed on the surface of the hole transport layer 123.
In an embodiment of the present invention, a method of forming the electrode buffer layer 124 on the surface of the hole transport layer 123 includes one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a spin coating method, a sputtering method, and a thermal evaporation method.
The material of the electrode buffer layer 124 may be MoOx、LiF、SnO2、TiO2、SiO2And amorphous silicon.
In some examples, the electrode buffer layer 124 may have a thickness of 0-500 nm. Preferably, the thickness of the electrode buffer layer 124 is 2 nm.
For example, the electrode buffer layer 124 may be prepared in a thermal evaporator by weighing 100mg LiF into an evaporation boat for evaporation at a vacuum of 5 × 10-4Pa, heating current of 30A, evaporation rate maintained at
After completion of the evaporation, an electrode buffer layer 124 having a film thickness of 2nm was formed.
In step 350, a transparent electrode layer 125 is formed on the surface of the electrode buffer layer 124.
In an embodiment of the present invention, the method of forming the transparent electrode layer 125 on the surface of the electrode buffer layer 124 includes one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a spin coating method, a sputtering method, and a thermal evaporation method.
The material of the transparent electrode layer 125 may be SnO2、TiO2One or more of IZO, ITO, AZO, graphene and silver nanowires.
In some examples, the thickness of the transparent electrode layer 125 may be 0-500 nm. Preferably, the thickness of the transparent electrode layer 125 is 100 nm.
Illustratively, the transparent electrode layer 125 of the ITO material may be prepared by magnetron sputtering, wherein the distance between the ITO target and the substrate is 6 cm, and during the preparation process, a mechanical pump and a molecular pump are sequentially used to pump the vacuum degree of the chamber to 5 × 10-4Pa, followed by argon gas flow, maintaining the gas flow at 35 mL/min. After 10 minutes, the working pressure is adjusted to 0.5Pa, and the ITO film starts to be deposited after the presputtering is carried out for 15 minutes, wherein the deposition time is 5 minutes. Taking out after the deposition is finished to formAnd a transparent electrode layer 125 having a film thickness of 100 nm.
In step 360, the front electrode 126 is disposed on the surface of the transparent electrode layer 125.
In an embodiment of the present invention, the method of providing the front electrode 126 on the surface of the transparent electrode layer 125 includes a thermal evaporation method or a screen printing method.
The material of the front electrode 126 may be a metal. Illustratively, the material of the front electrode 126 may be one or more of gold (Au), silver (Ag), aluminum (Al), and copper (Cu).
In some examples, the front electrode 126 may be 0-500nm thick. Preferably, the thickness of the front electrode 126 is 60 nm.
Illustratively, the front electrode 126 may be prepared by covering the surface with a mask and transferring to a thermal evaporator, weighing 1g of gold (Au) into an evaporation boat, and evaporating under a vacuum of 5 × 10-4Pa, heating current of 55A, evaporation rate maintained at
After completion of the evaporation, the front electrode 126 was formed to have a film thickness of 60 nm.
In step 370, the antireflection layer 127 is formed on the surface of the transparent electrode layer 125 in a region not in contact with the front electrode 126.
In an embodiment of the present invention, the method of forming the anti-reflection layer 127 on the surface of the transparent electrode layer 125 in the region not in contact with the front electrode 126 includes one or more of evaporation, sputtering, and atomic layer deposition.
The material of the anti-reflection layer 127 can be LiF or MgF2、Si3N4、SiO2And one or more of suede flexible films.
In some examples, the thickness of the antireflective layer 127 may be 0-5 mm. Preferably, the thickness of the antireflective layer 127 is 150 nm.
Illustratively, the mask plate can be replaced and sent to a thermal evaporator for MgF2Preparation of the antireflective layer 127. Weighing 100mg MgF2In the evaporation boat, the vacuum degree in the evaporation process is 5 × 10-4Pa, heating current of 50A,the evaporation rate is maintained at
After completion of the evaporation, the antireflection layer 127 having a film thickness of 150nm was formed.
According to the manufacturing method of the solar cell, the tunneling oxide layer 113 and the polycrystalline silicon layer 114 (such as the silicon oxide tunneling oxide layer 113 and the phosphorus-doped polycrystalline silicon layer 114) are sequentially arranged on the back surface of the substrate 111, so that a good passivation effect can be achieved, and the cell conversion efficiency is greatly improved. Compared with the heterojunction silicon solar cell technology, the manufacturing method of the solar cell can be used for preparing the solar cell (such as the solar cell 100) with wider spectral response range and higher photoelectric conversion efficiency, has simple process and lower cost, and simultaneously has the potential of commercial mass production and wide commercial application prospect.
The flowcharts shown in fig. 2 and 3 are used herein to illustrate the steps/operations performed by a fabrication method according to an embodiment of the present application. It should be understood that the above or below steps/operations are not necessarily performed exactly in order. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
It is understood that the above-described method for fabricating a solar cell is suitable for fabricating the solar cell 100 shown in fig. 1, but the invention is not limited thereto.
Other implementation details of the method for manufacturing a solar cell of the present embodiment can refer to the embodiment described in fig. 1, and are not further expanded herein. The priority of the specific operation steps of the manufacturing method can be appropriately adjusted according to the actual needs by those skilled in the art, and the present invention is not limited thereto.
The above embodiment of the present invention provides a method for manufacturing a solar cell, which is suitable for manufacturing a solar cell having a wider spectral response range and higher photoelectric conversion efficiency, and has a simple process and a lower cost.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (10)
1. A solar cell comprising a bottom cell and a top cell, wherein the bottom cell comprises:
a substrate;
the emitter layer is arranged on the surface of the substrate;
the tunneling oxide layer is arranged on the back surface of the substrate;
the polycrystalline silicon layer is arranged on the surface of the tunneling oxide layer;
the front passivation layer is arranged on the surface of the emitter layer;
the back passivation layer is arranged on the surface of the polycrystalline silicon layer; and
the back electrode is arranged on the surface of the back passivation layer;
wherein at least a portion of the emitter layer is not in contact with the front passivation layer, and at least a portion of the back electrode penetrates through the back passivation layer and is in contact with the polysilicon layer.
2. The solar cell of claim 1, wherein the tunneling oxide layer comprises silicon oxide and has a thickness of 1-15 nm.
3. The solar cell of claim 1, wherein the material of the polysilicon layer comprises phosphorus doped polysilicon and has a thickness of 10-1000 nm.
4. The solar cell of claim 1, wherein the substrate comprises N-type single crystal silicon and has a resistivity of 0.1-20 ohm-cm; the emitter layer is boron doped.
5. The solar cell of claim 1, further comprising a recombination layer disposed on a surface of the bottom cell, wherein the top cell is connected to the bottom cell via the recombination layer, and wherein the top cell comprises:
the electron transmission layer is arranged on the surface of the composite layer;
the perovskite layer is arranged on the surface of the electron transport layer;
the hole transport layer is arranged on the surface of the perovskite layer;
the electrode buffer layer is arranged on the surface of the hole transport layer;
the transparent electrode layer is arranged on the surface of the electrode buffer layer;
the front electrode is arranged on the surface of the transparent electrode layer; and
and the antireflection layer is arranged on the surface of the transparent electrode layer in a region which is not in contact with the front electrode.
6. A method of fabricating a solar cell, comprising forming a bottom cell and a top cell, wherein forming the bottom cell comprises:
providing a substrate;
forming an emitter layer on the surface of the substrate;
forming a tunneling oxide layer on the back surface of the substrate;
forming a polycrystalline silicon layer on the surface of the tunneling oxide layer;
forming a front passivation layer on the surface of the emitter layer;
forming a back passivation layer on the surface of the polycrystalline silicon layer; and
arranging a back electrode on the surface of the back passivation layer;
wherein at least a portion of the emitter layer is not in contact with the front passivation layer and at least a portion of the back electrode penetrates the back passivation layer and is in contact with the polysilicon layer;
the method of forming the front passivation layer on the surface of the emitter layer includes forming the front passivation layer using an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method, and patterning the front passivation layer to expose at least a portion of the emitter layer; the method for forming the back passivation layer on the surface of the polycrystalline silicon layer comprises an atomic layer deposition method and/or a plasma enhanced chemical vapor deposition method; the method for disposing the back electrode on the surface of the back passivation layer includes a thermal evaporation method or a screen printing method.
7. The method of claim 6, wherein the method of forming the tunnel oxide layer on the back surface of the substrate comprises a thermal oxidation method, a wet chemical method, a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, or an atmospheric pressure chemical vapor deposition method; the tunneling oxide layer is made of silicon oxide and has a thickness of 1-15 nm.
8. The method according to claim 6, wherein the method for forming the polysilicon layer on the surface of the tunnel oxide layer comprises a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or an atmospheric pressure chemical vapor deposition method; the polycrystalline silicon layer is made of phosphorus-doped polycrystalline silicon and has a thickness of 10-1000 nm.
9. The method of claim 6, wherein the substrate comprises N-type single crystal silicon and has a resistivity of 0.1-20 ohm-cm; the method of forming the emitter layer on the surface of the substrate includes boron diffusion.
10. The method of manufacturing according to claim 6, further comprising forming a composite layer on a surface of the bottom cell, and forming the top cell on a surface of the composite layer; wherein the step of forming the top cell further comprises:
forming an electron transport layer on the surface of the composite layer;
forming a perovskite layer on the surface of the electron transport layer;
forming a hole transport layer on the surface of the perovskite layer;
forming an electrode buffer layer on the surface of the hole transport layer;
forming a transparent electrode layer on the surface of the electrode buffer layer;
arranging a front electrode on the surface of the transparent electrode layer; and
forming an antireflection layer on a surface of the transparent electrode layer in a region not in contact with the front electrode;
the method for forming the composite layer on the surface of the bottom battery comprises one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a magnetron sputtering method and a thermal evaporation method; the method for forming the electron transport layer on the surface of the composite layer comprises one or more of a spin coating method, a magnetron sputtering method, a spray pyrolysis method, a thermal evaporation method, an atomic layer deposition method, a blade coating method, a coating method and a printing method; the method for forming the perovskite layer on the surface of the electron transport layer comprises one or more of a spin coating method, a spray pyrolysis method, a thermal evaporation method, a blade coating method, a coating method and a printing method; a method of forming the hole transport layer on the surface of the perovskite layer includes one or more of a spin coating method, a thermal evaporation method, a blade coating method, a coating method, and a printing method; the method for forming the electrode buffer layer on the surface of the hole transport layer comprises one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a spin coating method, a sputtering method and a thermal evaporation method; the method for forming the transparent electrode layer on the surface of the electrode buffer layer comprises one or more of an atomic layer deposition method, a plasma enhanced chemical vapor deposition method, a spin coating method, a sputtering method and a thermal evaporation method; the method for arranging the front electrode on the surface of the transparent electrode layer comprises a thermal evaporation method or a screen printing method; the method of forming the anti-reflection layer on the surface of the transparent electrode layer in the region not in contact with the front electrode includes one or more of evaporation, sputtering, and atomic layer deposition.
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