CN117412616B - Photovoltaic module containing perovskite/TOPCON laminated battery and preparation method thereof - Google Patents
Photovoltaic module containing perovskite/TOPCON laminated battery and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
- H10K39/10—Organic photovoltaic [PV] modules; Arrays of single organic PV cells
- H10K39/15—Organic photovoltaic [PV] modules; Arrays of single organic PV cells comprising both organic PV cells and inorganic PV cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Abstract
The application belongs to the technical field of photovoltaic modules, and in particular relates to a photovoltaic module containing perovskite/TOPCON laminated cells and a preparation method thereof, wherein the photovoltaic module comprises a supporting mechanism and a photovoltaic panel; the supporting mechanism comprises a base, wherein the base is provided with symmetrical mounting beams, and the mounting beams are provided with supporting beams; the supporting beam is provided with a pressing block through a guide post; the pressing block and the supporting beam are respectively provided with a corresponding first through hole, and the pressing block is connected with the supporting beam through a first bolt penetrating through the first through holes; the pressing block is used for fixing the photovoltaic panel; the cell sheets in the photovoltaic panel are perovskite/TOPCon laminate cells. The perovskite/TOPCon laminated battery prepared by the method can rapidly improve the conversion efficiency, open-circuit voltage, short-circuit current and other performances of the solar battery.
Description
Technical Field
The invention relates to the technical field of photovoltaic modules, in particular to a photovoltaic module containing perovskite/TOPCO laminated cells and a preparation method thereof.
Background
Solar cells, also known as photovoltaic cells or cells, are devices that convert light energy into electrical energy using the photovoltaic effect, and are also the smallest unit of photoelectric conversion. Since the current and voltage of the single solar cell are small and the electrodes of the cell are easily oxidized when directly exposed to air, the solar cell cannot be generally used alone as a power source. The manufacturing of the photovoltaic module is to firstly connect the battery pieces in series to obtain high voltage and then connect the battery pieces in parallel to obtain high current, and then package the battery pieces in the frame to form the photovoltaic module. A photovoltaic module consists of tens of battery pieces. The conversion efficiency of the battery piece directly influences the power generation efficiency of the photovoltaic module, and the production process of the battery piece directly influences the service life of the photovoltaic module.
The existence of single junction C-Si solar cells because of the schottky-nyquist limit means that the photovoltaic industry must consider a multi-junction tandem scheme to break the single junction efficiency limitations of silicon cells to achieve long-term growth and sustainability and further reduce the cost of single crystal silicon photovoltaic cells. At the same time, single crystal silicon has a weak response in the short-wave section due to its narrower band gap characteristics, while perovskite can just compensate for this short-wave plate because of its wide and tunable band gap characteristics.
The perovskite and crystalline silicon stacked cell has higher conversion efficiency due to the wider spectrum range which can be captured and converted. The continuously adjustable band gap width enables the perovskite to be suitable for being used as a laminated multi-junction battery, and sunlight with a wider spectral range can be captured and converted after being integrated with other batteries, so that the photoelectric conversion efficiency is higher than that of a pure crystal silicon battery or a perovskite battery. EcoMat research shows that the theoretical efficiency limit of the perovskite/silicon serial solar cell is 46% and is far higher than that of the traditional crystalline silicon cell; according to the latest laboratory data of NREL statistics, the perovskite/crystalline silicon lamination conversion efficiency is rapidly improved, and the perovskite/crystalline silicon lamination conversion efficiency exceeds that of a monocrystalline silicon battery.
The laminated cell takes a monocrystalline silicon cell as the bottom of the cell to absorb sunlight with the wavelength of more than 600 nanometers; and then taking the perovskite battery as the top of the battery to absorb sunlight with the wavelength of 200-850 nanometers, and connecting the perovskite battery and the monocrystalline silicon battery together in series through a composite layer.
In the prior art, as in chinese patent CN111525037B, a method for preparing a perovskite/N-type TOPCon/perovskite stacked solar cell is disclosed, which comprises: (1) Preparing a p+ doped region on the two sides of the silicon substrate after double-sided texturing; (2) Etching one side of the silicon substrate in an acid solution to remove the p+ doped region on the back side; (3) Preparing a tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the silicon substrate; (4) Doping the intrinsic crystal silicon layer of the silicon substrate, and cleaning; (5) Annealing the silicon substrate to form a doped polysilicon film; and removing the borosilicate glass layer on the front surface; (6) preparing a composite layer on the two sides of the silicon substrate; (7) Sequentially preparing a front electron transport layer, a front perovskite light absorption layer and a front hole transport layer on the front composite layer of the silicon matrix; sequentially preparing a back hole transport layer, a back perovskite light absorption layer and a back electron transport layer on the back composite layer of the silicon substrate; (8) preparing metal electrodes on the two sides of the silicon substrate.
The perovskite/TOPCon laminated cell prepared in the prior art is subjected to one-step annealing only when preparing the perovskite light absorption layer, as in Chinese patent CN111525037B, by co-evaporating PbCl on the back hole transport layer by co-evaporation 2 And KB to obtain PbCl 2 After the KB film layer, the ethanol mixed solution of FAI and FABr is spin-coated on the KB film layer, and finally, the annealing is carried out only at 160 ℃. The laminated battery prepared by the preparation method has insufficient adhesion degree of the perovskite light absorption layer and the silicon wafer and more defects, so that the transmission of photo-generated carriers is influenced, and the battery efficiency is influenced.
Disclosure of Invention
In order to solve the problems pointed out in the background art, the invention aims to provide a photovoltaic module containing perovskite/TOPCO laminated cells and a preparation method thereof.
The technical scheme provided by the invention is as follows:
in a first aspect, a photovoltaic module comprising a perovskite/TOPCon laminate cell comprises a support mechanism and a photovoltaic panel;
the supporting mechanism comprises a base, wherein the base is provided with symmetrical mounting beams, and the mounting beams are provided with supporting beams; the supporting beam is provided with a pressing block through a guide post;
the pressing block and the supporting beam are respectively provided with a corresponding first through hole, and the pressing block is connected with the supporting beam through a first bolt penetrating through the first through holes;
the pressing block is used for fixing the photovoltaic panel;
the cell in the photovoltaic panel is a perovskite/TOPCon laminated cell.
In a second aspect, a method for preparing a photovoltaic module comprising a perovskite/TOPCon laminate cell, comprises the steps of:
After the height of the supporting beam is adjusted, the supporting beam is connected with the mounting beam;
placing a photovoltaic panel between the pressing block and the supporting beam;
tightening the first bolt to enable the pressing block to fix the photovoltaic panel;
the preparation method of the perovskite light absorption layer of the perovskite/TOPCON laminated cell in the photovoltaic panel comprises the following steps of:
after an electron transmission layer is manufactured on the front surface of the silicon wafer, a perovskite light absorption layer is deposited;
the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min;
t1 < T2, and T1 < T2.
As an optional technical scheme of the second aspect, the value range of the T1 is 50-70 ℃; the value range of T2 is 90-100 ℃.
As an alternative solution of the second aspect, t1 is less than 0.5t2.
Further, the value range of t1 is 2-3 minutes, and the value range of t2 is 5-20 minutes.
As an optional technical solution of the first aspect, the preparation method of the electron transport layer includes: depositing a football alkene layer with the thickness of H1 on the surface of a silicon wafer, and then depositing SnO with the thickness of H2 on the football alkene layer by adopting an atomic layer deposition method 2 A layer;
wherein H1 > H2.
Further, the value range of H1 is 25-30 nanometers; the value range of H2 is 7-12 nanometers.
As an alternative technical scheme of the second aspect, the perovskite light-absorbing layer is formed on SnO by a one-step spin coating method 2 Deposition of Cs with thickness H3 on layer x (MA/FA) 1-x Pb(I y Br 1-y ) 3 Obtained by, among other things, cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 DMSO was evaporated by spin coating: ACN: 2-me=1: 3:2 as a solvent.
Further, the value range of H3 is 1000-1200 nanometers.
In a third aspect, a perovskite/TOPCon laminate cell comprises a silicon wafer layer;
one side of the silicon wafer layer is sequentially laminated with a boron doped layer, a first conductive glass layer, an electron transport layer, a perovskite light absorption layer, a hole transport layer, a second conductive glass layer and a front electrode;
the other side of the silicon wafer layer is sequentially provided with a first tunneling oxide layer, a first Poly layer, a second tunneling oxide layer, a second Poly layer, a silicon nitride anti-reflection layer and a back electrode in a laminated mode.
In a fourth aspect, a method for preparing a perovskite/TOPCon laminate battery comprises the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer;
s3, pickling to remove the edge and the back BSG of the silicon wafer, and performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer;
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process;
s5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer;
s6, performing a phosphorus expansion procedure by face-to-face double insertion;
s7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Wherein the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min;
T1 < T2, and T1 < T2.
As an optional technical scheme of the fourth aspect, in S1, the silicon wafer is an N-type silicon wafer with resistivity of 0.4-1.6Ω·cm; the pile height is 0.45-0.85 micrometers.
As an optional technical solution of the fourth aspect, in S2, the boron source is BCl 3 The sheet resistance after boron diffusion is 142-172 ohm/sq.
As an alternative technical scheme of the fourth aspect, in S3, the weight of the product after alkali polishing is reduced by 0.12-0.28 mg, and the reflectivity is greater than 38%.
As an optional technical solution of the fourth aspect, in S4 and S5, the first tunneling oxide layer and the second tunneling oxide layer are both SiO 2 The tunneling oxide layer has a thickness of 1-2 nm.
Further, in S4 and S5, the thickness of the first Poly layer and the second Poly layer is 55-65 nanometers.
As an alternative to the fourth aspect, in S8, the SiH is controlled 4 And NH 3 To form silicon nitride antireflection layers with different refractive indexes, and the film thickness of the silicon nitride antireflection layers is 67-91 nanometers.
Further, in S8, siH 4 ：NH 3 =0.099-0.265。
As an alternative solution of the fourth aspect, in S12, a hole transporting layer is prepared by spin coating PTAA of 5-9 nm on the perovskite surface by spin coating, and then annealing at 50 ℃ for 1-2 minutes.
As an optional technical solution of the fourth aspect, in S9 and S13, the first conductive glass layer and the second conductive glass layer are both ITO transparent conductive films manufactured by a magnetron sputtering method, the thickness of the first conductive glass layer is 15-20 nm, and the thickness of the second conductive glass layer is 120-150 nm.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
the invention comprises the following steps: 1. by superposing the two battery pieces, sunlight is fully utilized, and the conversion efficiency, open-circuit voltage, short-circuit current and other parameters of the solar battery can be rapidly improved. 2. The method can break through the conversion efficiency limit of TOPCON monocrystalline silicon and realize sustainable development of the solar cell. 3. For N + The layered design of the Poly layer can effectively lead the concentration between the Poly layers to form obvious decreasing gradient, can effectively improve the open voltage and the current of the battery and eliminate N + Carrier recombination within Poly layer; at the same time SiO 2 The existence of the oxide layer can effectively adsorb and deposit other metal elements in the Poly process, so as to jointly achieve the obvious advantage of improving the conversion efficiency of the battery piece. 4. The perovskite light absorption layer film layer crystal grains are redistributed and then uniformly grown, the degree of connection and matching between the perovskite light absorption layer film layer crystal grains and a monocrystalline silicon wafer is improved, a film with higher quality is formed, the corresponding light is improved, and unnecessary loss of photo-generated carriers is reduced.
Drawings
FIG. 1 is a schematic diagram of a perovskite/TOPCon stacked cell configuration in one embodiment of the application;
FIG. 2 is a film formation after one annealing of the perovskite light absorbing layer according to one embodiment of the application;
FIG. 3 is a film formation after secondary annealing of the perovskite light absorbing layer according to one embodiment of the present application;
FIG. 4 is a graph showing the formation of a perovskite light absorbing layer when two anneals are performed and T1> T2 and T1> T2 in one embodiment of the present application;
FIG. 5 is a graph showing the formation of a perovskite light absorbing layer when T1< T2 and 0.5t2 < T1< T2 are annealed twice in one embodiment of the application;
FIG. 6 is a graph showing the formation of a perovskite light absorbing layer when T1< T2 and T1<0.5t2 are annealed twice in one embodiment of the application;
FIG. 7 is a graph showing the formation of a perovskite light absorbing layer when two anneals are performed with T1< T2 and T1<0.5T2, and the two anneals are performed 24 hours apart, in one embodiment of the present application.
FIG. 8 is a schematic structural view of a photovoltaic module according to an embodiment of the present disclosure;
fig. 9 is a structural exploded view of a photovoltaic panel in one embodiment of the present application.
Reference numerals in the schematic drawings illustrate:
perovskite/TOPCon laminated cell 100, silicon wafer layer 101, boron doped layer 102, first conductive glass layer 103, electron transport layer 104, perovskite light absorbing layer 105, hole transport layer 106, second conductive glass layer 107, front electrode 108, first tunneling oxide layer 109, back electrode 110, first Poly layer 111, second tunneling oxide layer 112, second Poly layer 113, silicon nitride anti-reflection layer 114;
The photovoltaic panel 200, an upper cover plate 201, a frame 202, a lower cover plate 203, an encapsulating material 204 and a junction box 205;
base 301, mounting beam 302, third through-hole 303, second bolt 304, supporting beam 305, briquetting 306, first bolt 307, guide pillar 308.
Detailed Description
For a further understanding of the present invention, the present invention will be described in detail with reference to the drawings and examples.
The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and are not intended to limit the scope of the invention, since any modification, variation in proportions, or adjustment of the size, etc. of the structures, proportions, etc. should be considered as falling within the spirit and scope of the invention, without affecting the effect or achievement of the objective. Also, the terms "upper", "lower", "left", "right", "middle", and the like are used herein for descriptive purposes only and are not intended to limit the scope of the invention for modification or adjustment of the relative relationships thereof, as they are also considered within the scope of the invention without substantial modification to the technical context.
A perovskite/TOPCon laminate cell-containing photovoltaic module, as shown in fig. 8-9, includes a support mechanism and a photovoltaic panel 200.
The support mechanism includes a base 301, where the base 301 is configured to be coupled to a mounting platform, such as by welding or bolting, to the mounting platform. The base 301 is provided with symmetrical mounting beams 302 so that one base 301 can be used to mount and support two photovoltaic panels 200.
Specifically, a support beam 305 is mounted on the mounting beam 302. The mounting beam 302 is provided with a plurality of third through holes 303 which are arranged at intervals, for example, five through holes are formed. The support beam 305 is provided with a second through hole, and the support beam 305 is connected to the mounting beam 302 by a second bolt 304 passing through the third through hole 303 and the second through hole. After the support beam 305 is adjusted to a desired height, the second through hole of the support beam 305 is aligned with one of the third through holes 303 of the mounting beam 302, then a second bolt 304 is inserted, and the mounting beam 302 and the support beam 305 are fixed by tightening a nut.
The supporting beam 305 is provided with a pressing block 306 through a guide post 308, and specifically, the supporting beam 305 is fixedly provided with the guide post 308 through welding. The press block 306 is provided with a guide post hole through which the Rong Daozhu 308 passes, so that the press block 306 can only move vertically. The upper end of the guide post 308 may further be provided with a limiting block with a size larger than that of the guide post hole, so as to prevent the press block 306 from falling off.
The press block 306 and the support beam 305 are each provided with a corresponding first through hole, and the press block 306 and the support beam 305 are connected by a first bolt 307 passing through the first through hole. After placing the photovoltaic panel 200 between the press block 306 and the support beam 305, nuts on the first bolts 307 are tightened, thereby causing the press block 306 to fix the photovoltaic panel 200.
In use, at least two sets of support mechanisms are used together, and the two sets of support mechanisms respectively fix two opposite sides of the photovoltaic panel 200, thereby fixing the photovoltaic panel 200.
The cell sheets in the photovoltaic panel 200 are perovskite/TOPCon laminate cells 100. Specifically, the photovoltaic panel 200 includes a frame 202, and the frame 202 is used to fix an upper cover 201 and a lower cover 203. An encapsulation material 204 is provided between the upper cover 201 and the lower cover 203. A plurality of perovskite/TOPCon laminate cells 100, such as 72, are encapsulated within the encapsulation material. The plurality of perovskite/TOPCon laminate batteries 100 are connected in series by an electrical connection, and then the leads of the battery string are connected with the junction box 205.
The electric connecting piece, also called a photovoltaic welding strip or a welding strip, is used for being electrically connected with the electrode of the battery piece to collect the current converted by the battery piece, is a component for realizing the electric connection between the battery pieces in the photovoltaic module, and is a core electric connecting component in the photovoltaic module. The quality of the electric connecting piece directly influences the collection efficiency of the photovoltaic module to electricity. In some embodiments, the electrical connection includes an interconnecting strap and a bus strap. The interconnecting strip is used for connecting the battery pieces in series, and the back of each battery piece is welded with one interconnecting strip, so that a plurality of battery pieces are welded together in series to form a battery string. The bus bar is a carrier for connecting the battery strings, and connects the battery strings connected in series, and finally leads out the positive and negative electrodes to be connected to the junction box 205. In some embodiments, both the interconnect and bus tapes are tin-coated copper tapes.
The cover plate includes an upper cover plate 201 and a lower cover plate 203, and generally a side of the photovoltaic module directly facing the light source (e.g., sunlight) is referred to as a front side, and a side away from the light source is referred to as a back side. The upper cover 201 is located on the front side of the photovoltaic module, also referred to as a panel. The upper cover plate 201 is made of transparent material, and has a light transmittance of 91% or more in a spectral wavelength range of 320nm-1100nm, and is generally toughened glass, also called photovoltaic glass. The photovoltaic glass is special glass capable of utilizing solar radiation and leading out current, is also a light-transmitting packaging panel at the outermost layer of the photovoltaic module, mainly plays roles of light transmission and protection, and the quality of the photovoltaic glass directly influences the power generation efficiency and the service life of the photovoltaic module. Tempered glass is classified into coated glass and ordinary glass. The toughened glass adopts low-iron super Bai Rongmian toughened glass, the light transmittance can reach more than 90 percent, and the toughened glass can resist solar ultraviolet radiation. The lower cover plate 203 is located on the back of the photovoltaic module and is also referred to as a back plate. The backboard is a packaging component on the back of the photovoltaic module and has the functions of heat resistance, insulation and protection. The common backboard material is TPT (polyethylene fluoride composite film) (Tedlar/PET/Tedl) and has good environmental erosion resistance, insulating property and good bonding property with packaging materials.
The packaging material 204 comprises a photovoltaic packaging adhesive film, namely a bonding material among a panel, a battery and a backboard in the photovoltaic module, and plays roles of bonding, light transmission, protection and insulation. The photovoltaic packaging adhesive film is typically an EVA (Ethylene-Vinyl-Acetate-Copolymer) adhesive film or a POE (Polyolefin elastomer ) adhesive film. The EVA adhesive film is a thermosetting adhesive film, has advantages in the aspects of adhesive force, durability, optical characteristics and the like, and is widely applied to current components and optical products. Meanwhile, the EVA adhesive film is not sticky at normal temperature, and is convenient to operate. The POE adhesive film has water vapor isolation performance and PI (Potential Induced Degradation) resistance (potential induced attenuation) property and the like stronger than those of the EVA adhesive film, and is particularly suitable for a photovoltaic module packaged by double-sided glass.
The frame 202 is used as the packaging structure of the outermost layer of the photovoltaic module, has good portability and can meet the characteristic requirements of the photovoltaic module. The frame 202 can improve the overall mechanical strength of the assembly, and is convenient for assembly installation and transportation. The frame 202 is typically an aluminum alloy frame for protecting the edges of the cover plate and cooperating with silicone edging to enhance the sealing performance of the photovoltaic module.
Junction box 205 is capable of transmitting the current generated within the photovoltaic module to an external line. The junction box 205 includes positive and negative electrode lead wires and an electrical box connected to the outside. Junction box 205 includes a bypass diode that forms a bypass path to remain operational when the assembly fails, and a blocking diode that prevents current flow back when low light is present.
The embodiment also provides a preparation method of the photovoltaic module containing the perovskite/TOPCON laminated cell, which comprises the following steps:
after the height of the supporting beam 305 is adjusted, the supporting beam 305 is connected with the mounting beam 302;
placing photovoltaic panel 200 between press block 306 and support beam 305;
tightening the first bolts 307 to fix the photovoltaic panel 200 by the press blocks 306;
the preparation method of the perovskite light absorption layer of the perovskite/TOPCON laminated cell in the photovoltaic panel 200 comprises the following steps:
after an electron transmission layer is manufactured on the front surface of the silicon wafer, a perovskite light absorption layer is deposited;
the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min;
t1 < T2, and T1 < T2.
There are three main technical routes of TOPCon: low pressure vapor deposition, plasma enhanced vapor deposition, and Physical Vapor Deposition (PVD), each of which is defective, and which will become the mainstream in the future is not yet established. And secondly, the working procedures are numerous, and the yield is low. The TOPCon production process reaches 12 steps, 4 steps are added compared with PERC, and 8 steps are added compared with HJT, so that the yield is only 92% -95% at present, and is far lower than that of PERC and heterojunction by more than 98%, and the cost and the production line efficiency are directly affected. Thirdly, the cost-reducing route is difficult. The cost of TOPCon cells is mainly silicon wafer and silver paste. From the aspect of silicon chips, the core technology for reducing the cost is flaking, but due to the conditions of burning through of doping elements and burning through of metal slurry in a passivation layer under a high-temperature process, certain difficulty exists in achieving the thickness below 160 microns (the 182-size silicon chip used in the TOPCON battery at present corresponds to 180 microns and the 166-size silicon chip corresponds to about 170 microns), and a method for achieving flaking needs to be found by further optimizing the process in the future. The TOPCO cell also uses a higher silver paste content than the PERC cell from the silver paste perspective.
The theoretical conversion efficiency of the TOPCon battery is 28.7%, the conversion efficiency of the current mass production is about 26.5%, the improvement of the efficiency reaches a bottleneck period, and the process is complicated, so that the improvement of the efficiency by 0.1% is difficult.
In this embodiment, the present application also proposes a perovskite/TOPCon laminate cell, including a silicon wafer layer; one side of the silicon wafer layer is sequentially laminated with a boron doped layer, a first conductive glass layer, an electron transport layer, a perovskite light absorption layer, a hole transport layer, a second conductive glass layer and a front electrode; the other side of the silicon wafer layer is sequentially provided with a first tunneling oxide layer, a first Poly layer, a second tunneling oxide layer, a second Poly layer, a silicon nitride anti-reflection layer and a back electrode in a laminated mode.
Example 1
In this embodiment, the present application proposes a method for preparing a perovskite light absorbing layer, including: after an electron transmission layer is manufactured on the front surface of the silicon wafer, a perovskite light absorption layer is deposited; the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min; wherein T1 is less than T2, and T1 is less than T2. Specifically, the time interval between the two annealing is t3 minutes, and the value of t3 is 20-60 minutes, for example, t3 can be 30 minutes. The film forming conditions were 50℃and 25% humidity.
DMSO is dimethyl sulfoxide. ACN is acetonitrile. The 2-ME is 2-methoxyethanol.
In this example, T1 is greater than or equal to 50deg.C, T2 is greater than or equal to 90deg.C, wherein T1 has a value in the range of 50-70deg.C, and T2 has a value in the range of 90-100deg.C.
In this embodiment, t1 is less than 0.5t2, where the range of t1 is 2-3 minutes and the range of t2 is 5-20 minutes.
The preparation method of the electron transport layer comprises the following steps: depositing a football alkene layer with the thickness of H1 on the surface of a silicon wafer, and then depositing SnO with the thickness of H2 on the football alkene layer by adopting an atomic layer deposition method 2 A layer;
wherein H1 is more than H2, the value range of H1 is 25-30 nanometers, and the value range of H2 is 7-12 nanometers.
The perovskite light absorption layer is coated on SnO through a one-step spin coating method 2 Deposition of Cs with thickness H3 on layer x (MA/FA) 1-x Pb(I y Br 1-y ) 3 Obtained by, among other things, cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 DMSO was evaporated by spin coating: ACN: 2-me=1: 3:2 as a solvent. Which is a kind ofThe value range of H3 is 1000-1200 nm.
In this embodiment, as shown in fig. 1, the present application further proposes a perovskite/TOPCon stacked cell, including a silicon wafer layer 101, where a boron doped layer 102, a first conductive glass layer 103, an electron transport layer 104, a perovskite light absorption layer 105, a hole transport layer 106, a second conductive glass layer 107, and a front electrode 108 are sequentially stacked on the front surface of the silicon wafer layer 101. The back surface of the silicon wafer layer 101 is sequentially laminated with a first tunneling oxide layer 109, a first Poly layer 111, a second tunneling oxide layer 112, a second Poly layer 113, a silicon nitride anti-reflection layer 114 and a back electrode 110.
In this embodiment, the silicon wafer layer 101 is an N-type M10 silicon wafer, the thickness of which is 125 micrometers, and the pile height of the silicon wafer is 0.45-0.85 micrometers after cleaning and double-sided texturing treatment, so that the obtained pile is moderate and uniform in size, has a large body surface ratio value, and is beneficial to subsequent lamination of a perovskite layer on the surface of the silicon wafer.
When the silicon wafer is cleaned, the silicon wafer can be cleaned by mixing the mixed solution of NaOH, the additive and deionized water.
In the present embodiment, the first tunneling oxide layer 109 and the second tunneling oxide layer 112 are both SiO 2 Tunneling oxide layer. Hole transport layer 106 is a nano CuO layer. The first conductive glass layer 103 and the second conductive glass layer 107 are both ITO transparent conductive films manufactured by a magnetron sputtering method, the thickness of the first conductive glass layer 103 is 15-20 nanometers, and the thickness of the second conductive glass layer 107 is 120-150 nanometers.
The electron transport layer 104 is formed by depositing SnO on the football layer 2 The layer is obtained by firstly thermally depositing a 25-30 nanometer football alkene layer on the surface of a silicon wafer, and then depositing 7-12 nanometer SnO on the football alkene layer by adopting an atomic layer deposition method 2 The layer is made, in this example, the tin source is tetra (dimethylamino) tin.
In the present embodiment, the perovskite light absorbing layer 105 is formed on SnO by a one-step spin coating method 2 Depositing Cs on the layer to a thickness of 1000-1200 nm x (MA/FA) 1-x Pb(I y Br 1-y ) 3 Obtained by, among other things, cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 DMSO was evaporated by spin coating: ACN: 2-me=1: 3:2 as a solvent.
The front electrode 108 forms an ohmic contact with the boron doped layer 102 and the back electrode 110 forms an ohmic contact with the second Poly layer 113.
The front electrode 108 is an Ag paste electrode formed by printing and sintering, the Ag paste contains no Al powder, and the front electrode 105 is prepared from pure Ag paste, wherein the Al content is zero. Compared with the conventional Ag-Al slurry electrode, the resistivity of the pure Ag slurry electrode is lower; in the slurry component, the cancellation of Al powder leads to the reduction of metal diffusion penetration depth, the reduction of composite current density of a metal area and the improvement of Voc; the aluminum powder is cancelled and the glass material is changed, so that the corrosion resistance of the front metal electrode to carboxylic acid is improved, DH attenuation is reduced, and the reliability of the battery is improved.
In this embodiment, the first Poly layer 111 and the second Poly layer 113 are subjected to a phosphorus doping process.
In this embodiment, in the preparation process of the laminated cell, after the electron transport layer is fabricated on the front surface of the silicon wafer, a perovskite light absorption layer is deposited, wherein the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 I.e. perovskite light-absorbing layer may be Cs x MA 1-x Pb(I y Br 1-y ) 3 Cs may also be x FA 1-x Pb(I y Br 1-y ) 3 . By adjusting the values of x and y, different kinds of composition can be obtained. The perovskite light absorbing layer was prepared by spin-coating evaporation of DMSO: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃ to obtain the product.
Fig. 2 shows the film formation after the first annealing of the perovskite light absorbing layer, and fig. 3 shows the film formation after the second annealing of the perovskite light absorbing layer. From SEM characterization, after the first annealing at 50-70 ℃, the perovskite light absorption layer film layer is condensed into a small and uniform crystal structure, but the film layer has insufficient bonding degree with a monocrystalline silicon piece, so that more defects are caused, and the transmission of photo-generated carriers is affected. After the second annealing at 90-100 ℃, the grains of the perovskite light absorption layer film are redistributed and then grow uniformly, and the connection matching degree of the perovskite light absorption layer film and the monocrystalline silicon piece is improved, so that a film with higher quality is formed, the corresponding light is improved, and the unnecessary loss of photo-generated carriers is reduced.
FIGS. 4-7 show the formation of perovskite light absorbing layers after annealing at several different temperatures and times, where FIG. 4 shows two anneals, T1> T2, and T1> T2; FIG. 5 is a double anneal with T1< T2 and 0.5t2 < T1< T2; FIG. 6 is a double anneal with T1< T2, and T1<0.5T2; fig. 7 is two anneals with T1< T2 and T1<0.5T2, the two anneals being separated by 24 hours.
It CAN be seen that when the first annealing temperature T1 is higher than the second annealing temperature T2 and the first annealing time T1 is higher than the second annealing time T2, the volatile solvents CAN and 2-ME volatilize too quickly due to the too high temperature, so that the crystallization speed of the perovskite is too fast, and in addition, the solubility of DMSO increases nonlinearly with the increase of temperature, which causes uneven crystallization of the perovskite, poor matching and bonding degree with the monocrystalline silicon piece, and serious voids appear.
When the first annealing temperature T1 is smaller than the second annealing temperature T2 and the first annealing time T1 is higher than 0.5t2 and lower than the second annealing time T2, the crystallization film forming quality of the perovskite absorption layer is obviously better, and the degree of embedding between the perovskite absorption layer and monocrystalline silicon is also better, because the crystallization speed can be slowed down by the first lower annealing temperature, the formation of a high-quality film layer is facilitated, and the correspondingly proper increase of the annealing time is facilitated, so that the grain redistribution of the film layer is facilitated.
When the first annealing temperature T1 is smaller than the second annealing temperature T2 and the first annealing time T1 is smaller than 0.5t2, the film forming quality of the whole perovskite light absorption layer is close to an ideal result. Finally, when the interval between the two times of annealing is 24 hours, the time interval is too long, and the effect of the second time of annealing on the film layer is hardly observed, because after the film layer is placed for a long time, the film layer of the perovskite absorption layer is basically grown and shaped, and the film layer is not greatly influenced by annealing at a higher temperature, and the film layer is damaged due to too high temperature.
Example two
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning the silicon wafer and performing double-sided texturing. In this step, N-type M10 silicon wafer with resistivity of 0.4-1.6Ω & cm and thickness of 125 μm is selected.
S2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example III
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning the silicon wafer and performing double-sided texturing. In the step, an N-type M10 silicon wafer with resistivity of 0.4-1.6Ω & cm and thickness of 125 micrometers is selected, and the silicon wafer is cleaned and double-sided textured by mixing solution of NaOH, additive, deionized water and the like. The height of the obtained suede pyramid is 0.45-0.85 micrometers, so that the obtained suede has moderate and uniform size and large surface ratio value, and is beneficial to subsequent overlapping of the perovskite layer on the surface of the suede pyramid.
S2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example IV
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming PN junction with N-type substrate monocrystalline silicon, and the boron source is selected as BCl 3 Because of BCl 3 Is substantially non-damaging to Dan Yingyuan devices. And controlling the sheet resistance of the monocrystalline silicon piece after boron expansion to be 142-172 omega/sq.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example five
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
S1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the edge and the back PN junction of the silicon wafer, specifically, removing the edge and the back BSG by proportioning mixed solutions of HF, an additive, deionized water and the like, and then performing alkali polishing to remove the edge and the back PN junction by proportioning mixed solutions of NaOH, the additive, deionized water and the like, so that short circuit is prevented, and the back polishing improves the long-wave response. The weight of the silicon wafer subjected to alkali polishing is reduced by about 0.12-0.28mg, the reflectivity is larger than 38%, and the texture is affected if the silicon wafer is excessively polished or underpolished.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
S9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example six
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process. In this step, the first tunneling oxide layer is SiO 2 And the thickness of the tunneling oxide layer is 1-2 nanometers. The first Poly layer has a thickness of 55-65 nanometers.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example seven
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer. The second tunneling oxide layer is SiO 2 And the thickness of the tunneling oxide layer is 1-2 nanometers. The second Poly layer has a thickness of 55-65 nanometers.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example eight
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
S1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, carrying out a phosphorus expansion process by face-to-face double insertion, wherein in the phosphorus expansion process, the phosphorus source is POCl 3 . The phosphorus is gradually diffused into the two Poly layers, thereby dividing the conventional single layer process into two layers.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
s8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
S12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example nine
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + The Poly layer is then removed from the wafer front-side BSG and back-side PSG. Specifically, edge and front PSG are removed by proportioning mixed solution of HF, additive and deionized water, and then RCA is performed by proportioning mixed solution of NaOH/HF, additive and deionized water, so that N formed by coiling and expanding front and edge is removed + The layers are then removed with the front side BSG and the back side PSG to reduce the silicon wafer weight by about 0.02-0.04 mg.
S8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer;
s9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Examples ten
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + The Poly layer is then removed from the wafer front-side BSG and back-side PSG.
S8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer. Specifically, in this step, by controlling SiH 4 And NH 3 The Si-N ratio is gradually reduced in the deposition process, and the film thickness of the silicon nitride anti-reflection layer is 67-91 nanometers.
In this embodiment, siH 4 ：NH 3 =0.099-0.265。
S9, manufacturing a first conductive glass layer on the front surface of the silicon wafer;
s10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example eleven
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
S1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + The Poly layer is then removed from the wafer front-side BSG and back-side PSG.
S8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer.
S9, manufacturing a first conductive glass layer on the front surface of the silicon wafer. Specifically, a magnetron sputtering method (In 2 O 3 /SnO 2 ) An ITO transparent conductive film with the thickness of 15-20 nanometers is manufactured.
S10, manufacturing an electron transmission layer on the front surface of a silicon wafer;
s11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
S12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example twelve
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + The Poly layer is then removed from the wafer front-side BSG and back-side PSG.
S8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer.
S9, manufacturing a first conductive glass layer on the front surface of the silicon wafer.
S10, manufacturing an electron transmission layer on the front surface of the silicon wafer. Specifically, firstly, a 25-30 nanometer football alkene layer is thermally deposited on the surface of a silicon wafer, and then 7-12 nanometer SnO is deposited on the football alkene layer by adopting an atomic layer deposition method 2 The layer, where the tin source is tetra (dimethylamino) tin, was maintained at a substrate temperature of 100 ℃.
S11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃;
s12, manufacturing a hole transport layer on the front surface of the silicon wafer;
s13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Example thirteen
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning a silicon wafer and performing double-sided texturing;
s2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer; thereby forming a PN junction with the N-type substrate monocrystalline silicon.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer.
S6, performing a phosphorus expansion process in a face-to-face double-insertion manner.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + The Poly layer is then removed from the wafer front-side BSG and back-side PSG.
S8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer.
S9, manufacturing a first conductive glass layer on the front surface of the silicon wafer.
S10, manufacturing an electron transmission layer on the front surface of the silicon wafer.
S11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃.
Specifically, the perovskite light-absorbing layer is coated on SnO by a one-step spin coating method 2 Depositing Cs on the layer to a thickness of 1000-1200 nm x (MA/FA) 1-x Pb(I y Br 1-y ) 3 Obtained by, among other things, cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 DMSO was evaporated by spin coating: ACN: 2-me=1: 3:2 as solvent, then annealing at 50-70 ℃ for 2-3 minutes, and then stripping at 90-100 DEG CAnnealing under the piece for 5-20 minutes.
In this embodiment, DMSO is dimethyl sulfoxide; ACN is acetonitrile; the 2-ME is 2-methoxyethanol.
S12, manufacturing a hole transport layer on the front surface of the silicon wafer;
S13, manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and S14, manufacturing electrode grid lines on the front surface and the back surface of the silicon wafer, and finally manufacturing the laminated battery.
Examples fourteen
In this embodiment, the present application proposes a method for preparing a perovskite/TOPCon laminate battery, comprising the steps of:
s1, cleaning the silicon wafer and performing double-sided texturing. In the step, an N-type M10 silicon wafer with resistivity of 0.4-1.6Ω & cm and thickness of 125 micrometers is selected, and the silicon wafer is cleaned and double-sided textured by mixing solution of NaOH, additive, deionized water and the like. The height of the obtained suede pyramid is 0.45-0.85 micrometers, so that the obtained suede has moderate and uniform size and large surface ratio value, and is beneficial to subsequent overlapping of the perovskite layer on the surface of the suede pyramid.
S2, performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer so as to form a PN junction with N-type substrate monocrystalline silicon, wherein a boron source is selected as BCl 3 Because of BCl 3 Is substantially non-damaging to Dan Yingyuan devices. And controlling the sheet resistance of the monocrystalline silicon piece after boron expansion to be 142-172 omega/sq.
S3, pickling to remove the edge and the back BSG of the silicon wafer, and then performing alkali polishing to remove the edge and the back PN junction of the silicon wafer, specifically, removing the edge and the back BSG by proportioning mixed solutions of HF, an additive, deionized water and the like, and then performing alkali polishing to remove the edge and the back PN junction by proportioning mixed solutions of NaOH, the additive, deionized water and the like, so that short circuit is prevented, and the back polishing improves the long-wave response. The weight of the silicon wafer subjected to alkali polishing is reduced by about 0.12-0.28mg, the reflectivity is larger than 38%, and the texture is affected if the silicon wafer is excessively polished or underpolished.
S4, depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insertion LPCVD process. In this step, the firstThe tunneling oxide layer is SiO 2 And the thickness of the tunneling oxide layer is 1-2 nanometers. The first Poly layer has a thickness of 55-65 nanometers.
S5, performing the LPCVD process again, depositing a second tunneling oxide layer on the back surface of the silicon wafer, and simultaneously depositing a second Poly layer. The second tunneling oxide layer is SiO 2 And the thickness of the tunneling oxide layer is 1-2 nanometers. The second Poly layer has a thickness of 55-65 nanometers.
S6, carrying out a phosphorus expansion process by face-to-face double insertion, wherein in the phosphorus expansion process, the phosphorus source is POCl 3 . The phosphorus is gradually diffused into the two Poly layers, thereby dividing the conventional single layer process into two layers.
S7, removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + The Poly layer is then removed from the wafer front-side BSG and back-side PSG. Specifically, edge and front PSG are removed by proportioning mixed solution of HF, additive and deionized water, and then RCA is performed by proportioning mixed solution of NaOH/HF, additive and deionized water, so that N formed by coiling and expanding front and edge is removed + The layers are then removed with the front side BSG and the back side PSG to reduce the silicon wafer weight by about 0.02-0.04 mg.
S8, adopting a PECVD procedure to form two silicon nitride antireflection layers with different refractive indexes on the back surface of the silicon wafer. Specifically, in this step, by controlling SiH 4 And NH 3 The Si-N ratio is gradually reduced in the deposition process, and the film thickness of the silicon nitride anti-reflection layer is 67-91 nanometers.
In this embodiment, siH 4 ：NH 3 =0.099-0.265。
S9, manufacturing a first conductive glass layer on the front surface of the silicon wafer. Specifically, a magnetron sputtering method (In 2 O 3 /SnO 2 ) An ITO transparent conductive film with the thickness of 15-20 nanometers is manufactured.
S10, manufacturing an electron transmission layer on the front surface of the silicon wafer. Specifically, firstly, a 25-30 nanometer football alkene layer is thermally deposited on the surface of a silicon wafer, and then 7-12 nanometer SnO is deposited on the football alkene layer by adopting an atomic layer deposition method 2 The layer, where the tin source is tetra (dimethylamino) tin, was maintained at a substrate temperature of 100 ℃.
S11, manufacturing a perovskite light absorption layer on the front surface of the silicon wafer; then annealing for 2-3 minutes at 50-70 ℃ and then annealing for 5-20 minutes at 90-100 ℃.
Specifically, the perovskite light-absorbing layer is coated on SnO by a one-step spin coating method 2 Depositing Cs on the layer to a thickness of 1000-1200 nm x (MA/FA) 1-x Pb(I y Br 1-y ) 3 Obtained by, among other things, cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 DMSO was evaporated by spin coating: ACN: 2-me=1: 3:2 as a solvent, and then annealing at 50-70 ℃ for 2-3 minutes, and then annealing at 90-100 ℃ for 5-20 minutes.
In this embodiment, DMSO is dimethyl sulfoxide; ACN is acetonitrile; the 2-ME is 2-methoxyethanol.
S12, manufacturing a hole transport layer on the front surface of the silicon wafer. Specifically, a PTAA of 5-9 nm was spin-coated on the perovskite surface by spin-coating, and then annealed at 50℃for 1-2 minutes to prepare a hole transport layer.
S13, manufacturing a second conductive glass layer on the front surface of the silicon wafer. Specifically, a magnetron sputtering method (In 2 O 3 /SnO 2 ) An ITO transparent conductive film with the thickness of 120-150 nanometers is manufactured.
S14, preparing silver/aluminum electrode grid lines on the front ITO transparent conductive film and the back SiNx film by using a thermal evaporation method, wherein the thickness of the electrode grid lines is about 250-350 nanometers, and finally preparing the laminated battery.
After perovskite/TOPCon laminated batteries are prepared by the preparation method, the perovskite/TOPCon laminated batteries are compared with other batteries, and relevant performance test data are shown in the following table:
from the data, the open pressure after the perovskite/TOPCon lamination is greatly improved from 0.73V to 1.82V, which is far more than the upper limit value of the monocrystalline silicon cell because of the intrinsic band gap limitation; the conversion efficiency is improved from 25.3 percent27.2% which easily approximates the theoretical conversion limit of 28.7% for TOPCon cells; and its reverse side radiation conversion rate also reached 26%. The only disadvantage is that the current density and fill factor after series lamination is affected by the perovskite properties, the current density is from 40.3 mA/cm 2 Down to 19.2 mA/cm 2 The fill factor was reduced from 85.2% to 75.4%.
The invention and its embodiments have been described above by way of illustration and not limitation, and the invention is illustrated in the accompanying drawings and described in the drawings in which the actual structure is not limited thereto. Therefore, if one of ordinary skill in the art is informed by this disclosure, the structural mode and the embodiments similar to the technical scheme are not creatively designed without departing from the gist of the present invention.
Claims (20)
1. A photovoltaic module comprising a perovskite/TOPCon laminate cell, comprising a support mechanism and a photovoltaic panel (200); the method is characterized in that:
the supporting mechanism comprises a base (301), wherein the base (301) is provided with symmetrical mounting beams (302), and the mounting beams (302) are provided with supporting beams (305); a pressing block (306) is arranged on the supporting beam (305) through a guide pillar (308);
the pressing block (306) and the supporting beam (305) are respectively provided with a corresponding first through hole, and the pressing block (306) and the supporting beam (305) are connected through a first bolt (307) penetrating through the first through holes;
the pressing block (306) is used for fixing the photovoltaic panel (200);
The cell sheet in the photovoltaic panel (200) is a perovskite/TOPCon laminated cell (100);
the perovskite/TOPCON laminate cell (100) includes a silicon wafer layer;
one side of the silicon wafer layer is sequentially provided with a boron doped layer, a first conductive glass layer, an electron transport layer, a perovskite light absorption layer, a hole transport layer, a second conductive glass layer and a front electrode in a laminated manner;
the other side of the silicon wafer layer is sequentially provided with a first tunneling oxide layer, a first Poly layer, a second tunneling oxide layer, a second Poly layer, a silicon nitride anti-reflection layer and a back electrode in a laminated mode;
the preparation method of the perovskite light absorption layer comprises the following steps:
after an electron transmission layer is manufactured on the front surface of the silicon wafer, a perovskite light absorption layer is deposited;
the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min;
t1 < T2, and T1 < T2.
2. A method of manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module as claimed in claim 1, comprising the steps of:
after the height of the supporting beam (305) is adjusted, the supporting beam (305) is connected with the mounting beam (302);
Placing a photovoltaic panel (200) between a press block (306) and a support beam (305);
tightening the first bolt (307) to enable the pressing block (306) to fix the photovoltaic panel (200);
the preparation method of the perovskite light absorption layer of the perovskite/TOPCO laminated cell in the photovoltaic panel (200) comprises the following steps:
after an electron transmission layer is manufactured on the front surface of the silicon wafer, a perovskite light absorption layer is deposited;
the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min;
t1 < T2, and T1 < T2.
3. The method for manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 2, characterized in that: the time interval of the two annealing is t3, and the value range of t3 is 20-60 minutes.
4. A method of manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 3, characterized in that: the value range of T1 is 50-70 ℃; the value range of T2 is 90-100 ℃.
5. The method for manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 2, characterized in that: the t1 is less than 0.5t2.
6. The method for manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 5, characterized in that: the value range of t1 is 2-3 minutes, and the value range of t2 is 5-20 minutes.
7. The method for preparing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 2, wherein the method for preparing the electron transport layer comprises the steps of: depositing a football alkene layer with the thickness of H1 on the surface of a silicon wafer, and then depositing SnO with the thickness of H2 on the football alkene layer by adopting an atomic layer deposition method 2 A layer;
wherein H1 > H2.
8. The method for manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 7, characterized in that: the value range of H1 is 25-30 nanometers; the value range of H2 is 7-12 nanometers.
9. The method for manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 7, characterized in that: the perovskite light absorption layer is coated on SnO through a one-step spin coating method 2 Deposition of Cs with thickness H3 on layer x (MA/FA) 1-x Pb(I y Br 1-y ) 3 Obtained by, among other things, cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 DMSO was evaporated by spin coating: ACN:2-me=1: 3:2 as a solvent.
10. The method for manufacturing a perovskite/TOPCon laminate cell-containing photovoltaic module according to claim 9, characterized in that: the value range of H3 is 1000-1200 nanometers.
11. A preparation method of a perovskite/TOPCON laminated cell is characterized by comprising the following steps:
the preparation method of the perovskite light absorption layer comprises the following steps:
after an electron transmission layer is manufactured on the front surface of the silicon wafer, a perovskite light absorption layer is deposited;
the perovskite light absorption layer is Cs x (MA/FA) 1-x Pb(I y Br 1-y ) 3 It evaporates DMSO by spin coating: ACN: 2-ME= (1-6): (0-5) as a precursor solution of the solvent, then annealing at the temperature of T1 for T1 min, and then annealing at the temperature of T2 for T2 min;
t1 is less than T2, and T1 is less than T2;
before the electron transport layer is manufactured on the front surface of the silicon wafer, the method comprises the following steps:
cleaning the silicon wafer and double-sided texturing;
performing boron diffusion on the front surface of the silicon wafer to form a boron doped layer;
pickling to remove the edge and the back BSG of the silicon wafer, and performing alkali polishing to remove the PN junction of the edge and the back of the silicon wafer;
depositing a first tunneling oxide layer on the back surface of the silicon wafer and simultaneously depositing a first Poly layer in a face-to-face double-insert LPCVD process;
performing LPCVD process again, depositing a second tunneling oxide layer on the back of the silicon wafer, and simultaneously depositing a second Poly layer;
performing a phosphorus expansion procedure in a face-to-face double-insertion way;
removing PSG at the edge and the front side of the silicon wafer, and performing RCA cleaning to remove N at the edge and the front side of the silicon wafer + -Poly layer, then removing the front BSG and back PSG of the wafer;
Adopting PECVD procedure to form two silicon nitride anti-reflection layers with different refractive indexes on the back of the silicon wafer;
manufacturing a first conductive glass layer on the front surface of the silicon wafer;
after deposition of the perovskite light absorbing layer, the method comprises the following steps:
a hole transmission layer is manufactured on the front surface of the silicon wafer;
manufacturing a second conductive glass layer on the front surface of the silicon wafer;
and manufacturing electrode grid lines on the front and back of the silicon wafer, and finally manufacturing the laminated battery.
12. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: the silicon wafer is an N-type silicon wafer with the resistivity of 0.4-1.6Ω & cm; the pile height is 0.45-0.85 micrometers.
13. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: when boron diffuses, the boron source is BCl 3 The sheet resistance after boron diffusion is 142-172 ohm/sq.
14. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: the weight of the product after alkali polishing is reduced by 0.12-0.28 mg, and the reflectivity is more than 38%.
15. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: the first tunneling oxide layer and the second tunneling oxide layer are both SiO 2 The tunneling oxide layer has a thickness of 1-2 nm.
16. The method for producing a perovskite/TOPCon laminate cell according to claim 15, wherein: the first and second Poly layers are each 55-65 nanometers thick.
17. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: by controlling SiH 4 And NH 3 To form silicon nitride antireflection layers with different refractive indexes, wherein the film thickness of the silicon nitride antireflection layers is67-91 nm.
18. The method for producing a perovskite/TOPCon laminate cell according to claim 17, wherein: siH (SiH) 4 ：NH 3 =0.099-0.265。
19. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: PTAA of 5-9 nanometers was spin-coated on the perovskite surface by spin coating, and then annealed at 50℃for 1-2 minutes to prepare a hole transporting layer.
20. The method for producing a perovskite/TOPCon laminate cell according to claim 11, characterized in that: the first conductive glass layer and the second conductive glass layer are ITO transparent conductive films manufactured through a magnetron sputtering method, the thickness of the first conductive glass layer is 15-20 nanometers, and the thickness of the second conductive glass layer is 120-150 nanometers.
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