CN112086534A

CN112086534A - Laminated battery and manufacturing method thereof

Info

Publication number: CN112086534A
Application number: CN202010850989.0A
Authority: CN
Inventors: 徐琛
Original assignee: Longi Green Energy Technology Co Ltd
Current assignee: Longi Green Energy Technology Co Ltd
Priority date: 2020-08-21
Filing date: 2020-08-21
Publication date: 2020-12-15
Anticipated expiration: 2040-08-21
Also published as: CN112086534B

Abstract

The invention discloses a laminated cell and a manufacturing method thereof, relates to the technical field of solar energy, and aims to solve the problem that a perovskite laminated cell cannot be prepared on a textured surface of a bottom cell and improve the efficiency of the laminated cell. The laminate battery includes: the solar cell comprises a bottom battery, a hole transport layer deposited above the suede in vacuum and a perovskite absorption layer formed on the hole transport layer. The bottom cell has a textured surface. The manufacturing method of the laminated battery comprises the laminated battery provided by the technical scheme. The laminated battery and the manufacturing method thereof provided by the invention are used for manufacturing the laminated battery.

Description

Laminated battery and manufacturing method thereof

Technical Field

The invention relates to the technical field of solar cells, in particular to a laminated cell and a manufacturing method thereof.

Background

The crystalline silicon-perovskite laminated cell is a laminated cell formed by combining a crystalline silicon cell and a perovskite cell. The laminated cell takes a crystalline silicon cell as a bottom cell for absorbing solar energy of 700nm-1200nm, takes a perovskite cell as a top cell for absorbing solar energy of 300nm-800nm, and is connected with the perovskite cell through a composite layer, so that the crystalline silicon cell and the perovskite cell are connected in series.

When the crystalline silicon-perovskite laminated cell is manufactured, a solution spin coating method can be adopted to form the perovskite cell on the polished surface of the crystalline silicon cell so as to obtain the crystalline silicon-perovskite laminated cell. However, since the surface of the crystalline silicon cell needs to be processed by a polishing process, the manufacturing cost of the crystalline silicon-perovskite laminated cell is increased, the light absorption rate and the light utilization rate of the crystalline silicon-perovskite laminated cell are also inhibited, and the advantage of the efficiency gain of the laminated cell is difficult to embody.

Disclosure of Invention

The invention aims to provide a laminated battery and a manufacturing method thereof, which are used for improving the conversion efficiency of the laminated battery and reducing the manufacturing cost on the basis of keeping a suede structure of a bottom battery.

In a first aspect, the present invention provides a laminate battery. The laminate battery includes: the solar cell comprises a bottom battery with a suede surface, a hole transport layer deposited above the suede surface in a vacuum mode and a perovskite absorption layer formed on the hole transport layer. The perovskite absorption layer is a perovskite absorption layer containing lead ions. The hole transport layer is formed by co-depositing a metal sulfide hole transport material and an inorganic lead compound. Wherein the band gap of the metal sulfide is not less than 1.6 eV. The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate and lead acetate.

In the laminated battery provided by the invention, the hole transport layer is formed by vacuum codeposition of the metal sulfide hole transport material and the inorganic lead compound, and when the hole transport layer is formed on the suede of the bottom battery in a vacuum codeposition mode, the metal sulfide and the inorganic lead compound in a gas phase can be uniformly deposited on the suede of the bottom battery under the condition of not using an organic solvent. At the moment, the suede of the bottom battery is ensured to have a good light trapping effect, and the light utilization rate of the laminated battery can be increased.

On the basis, in the laminated battery provided by the invention, the perovskite absorption layer is a perovskite absorption layer with lead ions, and the perovskite absorption layer and the hole transport layer both contain the lead ions, so that when the perovskite absorption layer is formed on the hole transport layer, the hole transport layer can be used as an induction layer to induce the crystal growth of a perovskite absorption layer material, so that the perovskite absorption layer with higher order degree and good crystallinity is formed, and the photoelectric conversion efficiency is further improved. Meanwhile, soft alkali ions contained in the semiconductor material of the hole transport layer can be subjected to soft acid and soft alkali coordination with soft acid ions of the perovskite absorption layer material, so that the interface defect of the perovskite absorption layer can be passivated, the carrier recombination of the laminated cell is reduced, and the photoelectric conversion efficiency is improved. In addition, due to the soft acid and soft base coordination action force between the soft base ions and the soft acid ions in the perovskite absorption layer, the contact interface between the hole transport layer and the perovskite absorption layer has high compatibility, and therefore the hole extraction performance of the hole transport layer can be improved.

According to the laminated cell provided by the invention, the uniform perovskite absorption layer is formed on the hole transmission layer in an inducing manner, so that the formed perovskite absorption layer can be uniformly formed on the suede of the bottom cell, the uniform and compact perovskite absorption layer is formed on the suede of the bottom cell, the suede structure of the bottom cell is reserved, the sunlight absorption rate and the sunlight utilization rate of the laminated cell are improved, and the conversion efficiency of the laminated cell is further improved.

In one possible implementation, the mass ratio of the metal sulfide and the inorganic lead compound is 1: (0.01 to 0.5), for example, it may be 1: 0.01, 1: 0.25, 1: 0.45, 1: 0.5, etc. In the mixed type hole transport layer, the metal sulfide is used as a hole transport functional main body material accounting for more than 50 percent, and the inorganic lead compound is used as an inducing material for the growth of an anchoring layer on the hole transport layer and accounts for 1 to 50 percent.

In a possible implementation manner, the metal sulfide includes one or more of manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, gallium trisulfide, gallium monosulfide, germanium sulfide, germanium monosulfide, arsenic trisulfide, tin disulfide, tungsten disulfide, and lead sulfide. The semiconductor materials have large band gaps, basically do not absorb incident light in a battery absorption waveband, can be manufactured in a vacuum thermal evaporation mode, and are simple in manufacturing method and low in price.

In one possible implementation, the perovskite absorption layer has a chemical formula ABX₃(ii) a Wherein A is one or more of alkylamine cation, ethylenediamine cation and cesium cation, and B is the alkali metal cation and Pb²⁺、Sn²⁺Is one or more of, X is I^-、Cl^-、Br^-One or more of (a).

In one possible implementation, the thickness of the perovskite absorption layer is 100nm to 1000 nm.

In one possible implementation, the thickness of the hole transport layer is 5nm to 100 nm.

In one possible implementation manner, the stacked cell further includes a tunneling composite layer formed above the textured surface, and the hole transport layer is formed on the tunneling composite layer.

In a second aspect, the invention further provides a method for manufacturing the laminated battery. The manufacturing method of the laminated battery comprises the following steps:

a bottom cell is provided, and the bottom cell is provided with a suede surface.

And co-depositing a metal sulfide hole transport material and an inorganic lead compound above the textured surface by adopting a vacuum co-deposition process to form a hole transport layer. The band gap of the metal sulfide is not less than 1.6 eV. The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate and lead acetate.

And forming an anchoring layer on the hole transport layer by vacuum deposition, wherein the anchoring layer contains a metal halide, and the metal halide at least comprises lead halide.

And coating a cation salt on the anchoring layer by a solution method, wherein the metal halide contained in the anchoring layer reacts with the cation salt to form the perovskite absorption layer.

An electron transport layer is formed on the perovskite absorption layer, and an upper electrode is formed on the electron transport layer.

Since the metal sulfide is easily deposited on various types of bottom cells, the bottom cells may be N-type polycrystalline silicon cells, single crystal silicon cells, and the like. The manufacturing method of the laminated cell can also be applied to the manufacturing of laminated cells such as copper indium gallium selenide-perovskite laminated cells, perovskite-perovskite laminated cells, gallium arsenide-perovskite laminated cells, organic photovoltaic-perovskite laminated cells and the like.

In one possible implementation, the metal halide further includes one or both of tin halide and alkali metal halide.

In one possible implementation manner, the co-depositing the metal sulfide hole transport material and the inorganic lead compound on the textured surface by using the vacuum co-deposition process to form the hole transport layer comprises the following steps: and co-depositing metal sulfide and lead compound above the suede by adopting a vacuum thermal evaporation process to obtain a hole transport layer. The vacuum thermal evaporation rate of the metal sulfide and the inorganic lead compound is

In one possible implementation, the forming the anchoring layer above the hole transport layer includes: co-depositing metal halide on the hole transport layer by adopting a vacuum evaporation method to obtain an anchoring layer; the vacuum evaporation rate of the alkali metal halide is

The vacuum evaporation rate of the lead halide and the tin halide is

Since there is a difference in physical properties between the metal halide and the lead and tin halides, it is necessary to control the vacuum deposition rate of the alkali metal halide within the above range during the vacuum deposition film formation.

In one possible implementation, the coating of the cationic salt on the anchoring layer by the solution method includes: and coating a cationic salt solution on the anchoring layer by a solution method, so that the metal halide contained in the anchoring layer reacts with the cationic salt to form the perovskite absorption layer.

In a possible implementation manner, after the cation salt is formed on the anchoring layer by using the solution method and before the electron transport layer is formed on the perovskite absorption layer, the method for manufacturing the tandem cell further includes: and annealing the perovskite absorption layer. The temperature of the annealing treatment is 50-200 ℃, and the time of the annealing treatment is 5-60 minutes. Through annealing treatment, a more compact, more regular and more uniform perovskite absorption layer is formed, so that the efficiency of the laminated cell can be improved.

In a possible implementation manner, before the electron transport layer is formed on the perovskite absorption layer, the method for forming the stacked cell further includes: and forming an electron-transporting interface layer on the perovskite absorption layer for transporting carriers. The electron transport interface layer comprises a LiF layer and C₆₀And (3) a layer. LiF layer formed on the perovskite absorption layer, C₆₀The layer is formed on the LiF layer. Wherein the thickness of the LiF layer is 0.1nm-10nm, and C₆₀The thickness of the layer is 1nm-20 nm.

In a possible implementation manner, before the forming the hole transport layer over the textured surface, the method for manufacturing the stacked cell further includes: and forming a tunneling composite layer above the suede.

The beneficial effects of the method for manufacturing a stacked cell provided by the second aspect are the same as those of the stacked cell provided by the first aspect, and are not described herein again.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic structural diagram of a prior art crystalline silicon-perovskite tandem cell;

FIG. 2 is a schematic diagram of a stacked cell structure according to an embodiment of the present invention;

fig. 3A to fig. 3H are schematic diagrams illustrating states of various stages of a method for manufacturing a stacked cell according to an embodiment of the invention;

fig. 4 is a texture surface cross-sectional SEM image of the stacked cell fabricated in the first embodiment of the present invention;

fig. 5 is a textured SEM image of the tandem cell manufactured in the first embodiment of the present invention;

fig. 6 is an I-V curve of the stacked batteries manufactured according to the first embodiment of the present invention, and the second embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Organic-inorganic hybrid perovskite solar cells are of wide interest worldwide as novel high efficiency, low cost solar cells. In as little as a few years, the photoelectric conversion efficiency of perovskite cells has rapidly risen from 3.8% in 2009 to over 25%, approaching the efficiency of commercial silicon-based solar cells. As a multi-component battery, the absorption spectrum band gap of the perovskite battery can be regulated and controlled within the range of 1.5eV to 1.8eV through the component formula. The crystalline silicon cell is a high-efficiency crystalline silicon photovoltaic cell technology, the cell efficiency (26.7%) of the crystalline silicon photovoltaic cell is close to the theoretical limit efficiency (29.4%), and the tandem cell technology is an effective way for breaking through the efficiency of the traditional crystalline silicon photovoltaic cell. Perovskite is an ideal top-of-stack cell material. FIG. 1 shows a schematic structural diagram of a crystalline silicon-perovskite laminated cell in the prior art, and as shown in FIG. 1, the crystalline silicon-perovskite laminated cell sequentially comprises a silver electrode 1-1, a back transparent conductive film 1-2, a P-type amorphous silicon layer 1-3, an intrinsic amorphous silicon layer 1-4, a bottom cell light absorption layer 1-5, an N-type amorphous silicon layer 1-6, an N-type heavily doped tunneling junction layer 1-7, a P-type heavily doped tunneling junction layer 1-8, a hole transport layer 1-9, a perovskite absorption layer 1-10, an electron transport interface layer 1-11, SnO, and SnO from bottom to top₂Electron transport layer 1-12, transparent front electrode 1-13, silver electrode grid line 1-14. The crystalline silicon-perovskite laminated cell takes a crystalline silicon cell as a bottom cell to absorb the solar energy of 700nm-1200nm, takes a perovskite cell as a top cell to absorb the solar energy of 300nm-800nm, and is connected through a composite layer to form a cell with two ends connected in series. The overall open circuit voltage of the stack is the voltage superposition of the top and bottom cells, while the current of the stack requires good current matching between the top and bottom cells. The crystalline silicon-perovskite laminated cell is expected to achieve more than 30% of photoelectric conversion efficiency.

At present, several documents report that the conversion efficiency of the crystalline silicon-perovskite laminated cell reaches more than 25%. Typical perovskite cells are fabricated with various functional layers in the device by a solution spin-coating process. The efficient crystalline silicon cell generally adopts two-sided matte trapping structure to improve the absorption and utilization ratio of sunlight, and then promotes battery conversion efficiency. The micron-scale pyramid textured light trapping structure in the crystalline silicon cell is a great challenge for manufacturing a perovskite roof cell by a solution method. The difficulty is that the thickness of each functional layer of the perovskite battery is generally hundreds of nanometers, and the functional layers are difficult to be uniformly deposited on the surface of a micron-sized pyramid textured surface by a solution spin coating method. The current solution is to polish the crystalline silicon bottom cell and reduce the roughness of the textured surface so that it becomes possible to solution fabricate the perovskite top cell. Although the method can process and manufacture the perovskite top cell and the laminated cell on the suede surface, the cell efficiency gain brought by the suede surface structure and the light trapping effect is sacrificed. Meanwhile, the manufacturing cost of the whole battery is greatly increased in the polishing process, and the advantage of the efficiency gain of the laminated battery is difficult to embody. The retaining of the texture surface structure of the bottom battery and the direct manufacture of the perovskite battery on the texture surface of the bottom battery are the key for realizing the high efficiency of the laminated battery. However, the key to directly manufacture the perovskite battery on the textured surface of the bottom battery is how to uniformly deposit each functional layer of the perovskite top battery on the textured surface, wherein each functional layer of the perovskite top battery comprises a hole transport layer, a perovskite layer, an electron transport layer, a hole blocking layer, an electrode buffer layer, an electrode and the like. Compared with the solution processing method, the vacuum evaporation deposition process can uniformly deposit various evaporation functional materials on various substrates, and is an effective solution for overcoming the difficulty of manufacturing the perovskite top cell on the suede of the bottom cell. The vacuum evaporation electron transport layer, the hole blocking layer, the electrode buffer layer and the sputtering electrode all have mature functional materials and deposition processes. The vacuum evaporation of the conformal deposition cavity transmission layer and the perovskite layer on the suede of the bottom cell is a difficult point and a key for manufacturing the high-efficiency crystalline silicon-perovskite laminated cell.

In order to solve the above technical problem, an embodiment of the present invention provides a stacked cell. The laminated cell is not only suitable for the laminated cell taking a crystal silicon cell as a bottom cell, but also suitable for the laminated cell taking any one of a polycrystalline silicon cell, a copper indium gallium selenide cell, a perovskite cell, a gallium arsenide cell and an organic photovoltaic cell as the bottom cell, and is not limited to the above.

Fig. 2 is a schematic structural diagram of a stacked cell according to an embodiment of the present invention. As shown in fig. 2, a stacked battery provided by an embodiment of the present invention includes: a bottom cell 1, a hole transport layer 2 and a perovskite absorption layer 3.

As shown in fig. 2, the bottom cell 1 has a pile surface. The bottom cell 1 may be any one of the bottom cells 1 described above, and is not limited thereto. The suede can be a suede with pyramid appearance, and can also be a suede with inverted pyramid appearance, and the like.

As shown in fig. 2, the hole transport layer 2 is formed on the textured surface, and the hole transport layer 2 is formed by vacuum co-depositing a metal sulfide hole transport material and an inorganic lead compound, which may be deposited on the textured surface by vacuum co-deposition.

As shown in fig. 2, if the laminate battery further includes a tunnel composite layer 4, the tunnel composite layer 4 is formed on the bottom battery 1. The tunnel composite layer 4 may be a tunnel composite layer 4 made of heavily doped silicon opposite to the pn-junction of the bottom cell 1. For example, a tunnel junction composite layer 4 mainly composed of an n-type doped microcrystalline silicon layer and a p-type doped microcrystalline silicon layer. Specifically, the n-type doped microcrystalline silicon layer may be a microcrystalline silicon layer doped with group va atoms such as phosphorus, arsenic, antimony, and bismuth, and the p-type doped microcrystalline silicon layer may be a microcrystalline silicon layer doped with group iiia atoms such as boron, aluminum, gallium, indium, and thallium.

Of course, the tunneling composite layer 4 may also be a tunneling composite layer 4 made of other materials, for example, a composite layer made of transparent metal oxides such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), indium tungsten oxide (IWO), indium titanium oxide (ITIO), tin fluorine oxide (FTO), and zinc aluminum oxide (AZO).

As shown in fig. 2, the above-described hole transport layer 2 is formed on the tunneling composite layer 4, and the hole transport layer 2 is formed by vacuum co-depositing a metal sulfide and an inorganic lead compound. The mass ratio of the metal sulfide to the inorganic lead compound is 1: (0.01 to 0.5), for example, it may be 1: 0.01, 1: 0.25, 1: 0.45, 1: 0.5, etc. In the hole transport layer 2 formed by the above formulation, the proportion of the metal sulfide is large, so that the hole transport performance of the hole transport layer 2 is not affected. Meanwhile, lead ions are added into the hole transport layer 2, so that a contact interface between the hole transport layer 2 and the perovskite absorption layer 2 has high compatibility, the hole transport layer 2 can induce the perovskite absorption layer 2 to grow through crystallization, the perovskite absorption layer 2 with high degree of order and good degree of crystallization is formed, and the photoelectric conversion efficiency is improved.

As shown in fig. 2, the inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate and lead acetate. The thickness of the hole transport layer 2 can be set as appropriate, for example, the thickness of the hole transport layer 2 is 5nm to 100 nm. The hole transport layer 2 is formed on the tunneling composite layer 4. The bottom battery 1 and the perovskite top battery are connected through a tunneling composite layer 4 to form a battery with two ends connected in series. The formation mode here may be a conformal formation.

As shown in fig. 2, the metal sulfide and the inorganic lead compound can be uniformly deposited on the texture of the bottom cell 1 by using a vacuum co-deposition process, so that the light trapping effect of the texture of the bottom cell 1 is maintained, and the bottom cell 1 can ensure good absorption of incident light. Meanwhile, the hole transport layer 2 manufactured by the above process has good compatibility and adaptability with other functional layers, so that the bottom cell 1 in the stacked cell of the embodiment of the present invention can be selected according to actual needs. And because the metal sulfide and the inorganic lead compound are relatively cheap, the cost of the laminated battery can be reduced by using the metal sulfide and the inorganic lead compound as the materials of the hole transport layer, so that the application range of the laminated battery is wider.

As shown in fig. 2, the perovskite absorption layer 3 is formed on the hole transport layer 2, and the perovskite absorption layer 3 is a perovskite absorption layer 3 having lead ions. The thickness of the perovskite absorption layer 3 may be set as the case may be, for example, the thickness of the perovskite absorption layer 3 is 100nm to 1000 nm.

On the other hand, as shown in fig. 2, according to the principle that soft acid and soft base are easily and stably combined in the soft acid-base theory, the sulfide ions contained in the hole transport layer 2 are soft base ions, and there is a strong interaction force with the soft acid ions (lead ions) contained in the perovskite absorption layer 3. Since the perovskite absorption layer 3 and the hole transport layer 2 both contain lead ions, when the perovskite absorption layer 3 is formed on the hole transport layer 2, the hole transport layer 2 can be used as an inducing layer to induce the crystal growth of the material of the perovskite absorption layer 3, so that the perovskite absorption layer 3 with higher order degree and good crystallinity is formed, and the photoelectric conversion efficiency is further improved. Meanwhile, soft alkali ions contained in the semiconductor material of the hole transport layer 2 can be subjected to soft acid and soft alkali coordination with soft acid ions of the material of the perovskite absorption layer 3, so that the interface defects of the perovskite absorption layer 3 can be passivated, the carrier recombination of the laminated cell is reduced, and the photoelectric conversion efficiency is improved. In addition, due to the soft acid-soft base coordination action force between the soft base ions and the soft acid ions in the perovskite absorption layer 3, the contact interface between the hole transport layer 2 and the perovskite absorption layer 3 has high compatibility, so that the hole extraction performance of the hole transport layer 2 can be improved.

On the other hand, as shown in fig. 2, the laminated cell provided by the invention has the advantages that the uniform perovskite absorption layer 3 is induced and formed on the hole transport layer 2, so that the formed perovskite absorption layer 3 can be uniformly formed on the suede of the bottom cell 1, the uniform and compact perovskite absorption layer 3 is formed on the suede of the bottom cell 1, the suede structure of the bottom cell 1 is reserved, the sunlight absorption rate and the sunlight utilization rate of the laminated cell are improved, and the conversion efficiency of the laminated cell is further improved.

In some embodiments, as shown in FIG. 2, the perovskite absorption layer 3 has the general chemical formula ABX₃(ii) a Wherein A is one or more of alkylamine cation, ethylenediamine cation and cesium cation, and B is the alkali metal cation and Pb²⁺、Sn²⁺Is one or more of, X is I^-、Cl^-、Br^-One or more of (a). Wherein the alkylamine cation comprises CH₃NH₃Cation, C₄H₉NH₃One or a combination of two of the cations.

As shown in fig. 2, the band gap of the metal sulfide is not less than 1.6eV, and the metal sulfide with a wide band gap is selected, so that the formed hole transport layer hardly absorbs incident light in the absorption band of the tandem cell, and the formed hole transport layer has low optical loss.

As shown in fig. 2, the metal sulfide may include one or more of manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, digallium trisulfide, gallium monosulfide, germanium sulfide, germanium monosulfide, arsenic trisulfide, tin disulfide, tungsten disulfide, and lead sulfide, but is not limited thereto.

In one example, when the metal sulfide is manganese sulfide, since manganese sulfide is a high mobility P-type semiconductor with an optical band gap of 3.25eV, incident light is not absorbed in the absorption band of the stacked cell. And the valence band energy level of manganese sulfide is-5.24 eV, which is very close to the Highest Occupied Molecular Orbital (HOMO) energy level of perovskite (about-5.30 eV), and is beneficial to the collection of hole charges. The energy level of a conduction band of manganese sulfide is-1.61 eV, and the energy level of a Lowest Unoccupied Molecular Orbital (LUMO) of perovskite is far from the energy level (about-3.90 eV), so that the diffusion of electrons to the electrode can be effectively blocked. And when an anchoring layer is formed on the hole transport layer 2 made of manganese sulfide, sulfur ions (soft alkali) in the manganese sulfide and lead ions (soft acid) in the anchoring layer can form a strong bonding effect, so that a uniform perovskite absorption layer 3 can be formed on the textured surface of the bottom battery in the subsequent process.

Fig. 3A to 3H are schematic diagrams illustrating states of various stages of a method for manufacturing a stacked cell according to an embodiment of the present invention. The manufacturing method of the laminated battery provided by the embodiment of the invention comprises the following steps:

as shown in fig. 3A, a bottom cell 1 is provided, the bottom cell 1 having a pile surface. Taking an N-type silicon wafer as a silicon substrate as an example, the manufacturing method of the bottom cell 1 comprises the following steps:

a commercial-grade M2N-type silicon wafer is sequentially subjected to polishing, texturing and cleaning treatment to form a monocrystalline silicon substrate. The resistivity of the N-type silicon chip is 1-10 omega cm, and the thickness is 50-200 mu m.

Depositing intrinsic amorphous silicon passivation layers on two sides of a monocrystalline silicon substrate respectively by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a front passivation layer film and a back passivation layer film, wherein the thicknesses of the front passivation layer film and the back passivation layer film are 1nm-20 nm.

And depositing a phosphorus-doped N-type amorphous/microcrystalline silicon layer on the front surface of the silicon wafer by adopting PECVD (plasma enhanced chemical vapor deposition), wherein the thickness is 1nm-30nm, and a front field structure is formed.

And depositing a boron-doped P-type amorphous/microcrystalline silicon layer on the back of the silicon wafer by adopting PECVD (plasma enhanced chemical vapor deposition), wherein the thickness is 1nm-30nm, and forming an emitter structure.

And preparing the transparent conductive material layer with the thickness of 30nm-120nm by adopting a magnetron sputtering method. In practical applications, the transparent conductive material layer may be an ITO transparent conductive material layer, an IZO transparent conductive material layer, an IWO transparent conductive material layer, an ITiO transparent conductive material layer, or the like.

As shown in fig. 3B, a tunneling composite layer 4 is formed over the pile surface. Specifically, phosphorus and boron doped microcrystalline silicon films with the thickness of 1nm-30nm are respectively manufactured on the suede of the bottom cell 1 to form a tunneling composite layer 4, so that tunneling composite collection of photon-generated carriers is realized.

As shown in fig. 3C, a vacuum co-deposition process is used to co-deposit a metal sulfide hole transport material and an inorganic lead compound on the textured surface to form a hole transport layer 2. Wherein the band gap of the metal sulfide is not less than 1.6eV, and the mass ratio of the metal sulfide to the inorganic lead compound is 1: (0.01-0.5). Specifically, a vacuum thermal evaporation process is adopted to co-deposit metal sulfide and lead compound on the suede of the bottom battery 1 to manufacture the hole transport layer 2. The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate and lead acetate. The metal sulfide is one or more of manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, gallium trisulfide, gallium monosulfide, germanium sulfide, germanium monosulfide, arsenic trisulfide, tin disulfide, tungsten disulfide and lead sulfide. The vacuum thermal evaporation rate of the metal sulfide and the inorganic lead compound is

The thickness of the hole transport layer 2 is 5nm-100nmnm。

As shown in fig. 3D, an anchor layer 5 is formed on the hole transport layer 2 by vacuum deposition. The anchoring layer 5 contains a material that is a metal halide including at least a lead halide. Specifically, a metal halide is co-deposited on the hole transport layer 2 by vacuum evaporation to obtain the anchor layer 5. Wherein, the metal halide also comprises one or two of tin halide and alkali metal halide. The vacuum evaporation rate of the alkali metal halide is

The vacuum evaporation rate of the lead halide and the tin halide is

The thickness of the anchoring layer 5 is 250nm to 1000 nm.

As shown in fig. 3E, the anchoring layer 5 is coated with a cationic salt using a solution method. Specifically, a cationic salt solution is coated on the anchoring layer 5 by a solution method, so that the material contained in the anchoring layer 5 reacts with the cationic salt to form the perovskite absorption layer 3. The perovskite absorption layer 3 is a perovskite absorption layer 3 having lead ions.

As shown in fig. 3E, the perovskite absorption layer 3 is subjected to annealing treatment. Specifically, the annealing temperature is 50-200 ℃, the annealing time is 5-60 minutes, and the thickness of the formed compact and uniform perovskite absorption layer 3 is 100-1000 nm.

As shown in fig. 3F, an electron-transporting interfacial layer is formed on the perovskite absorption layer 3. In practical applications, the electron transporting interface layers can be LiF electron transporting interface layers 6 and C₆₀An electron-transporting interface layer 7. The LiF electron transport interface layer 6 is formed on the perovskite absorption layer 3, and the thickness of the LiF electron transport interface layer 6 is 0.1nm-10 nm. C₆₀An electron transporting boundary layer 7 formed on the LiF electron transporting boundary layer 6, C₆₀The thickness of the electron-transporting interface layer 7 is 1nm to 20 nm. In practical applications LiF electron transport interfacial layers 6 and C₆₀The electron-transporting interface layer 7 may be omittedOne or more of them may be omitted.

As shown in fig. 3G, an electron transport layer 8 is formed on the perovskite absorption layer 3. In practical application, the material of the electron transport layer can be SnO₂The layer thickness can be 1nm-30nm, and the manufacturing process can be any one of an atomic layer deposition process (ALD), a chemical vapor deposition process, a physical vapor deposition process and a solution coating process.

As shown in fig. 3H, an electrode 9 is formed on the electron transport layer 8. In practical application, the transparent conductive film can be prepared by adopting a magnetron sputtering method, and the thickness of the transparent conductive film is 30nm-200 nm. The silver electrode grid line 9 can be manufactured on the transparent conductive film by using modes of evaporation, screen printing and the like, the thickness of the silver electrode grid line 9 can be 100nm-500nm, and the material of the silver electrode grid line can be silver, copper, aluminum and other metals with better conductivity.

Compared with the prior art, the beneficial effects of the manufacturing method of the laminated battery provided by the embodiment of the invention are the same as those of the laminated battery, and are not repeated herein.

In order to verify the performance of the laminate battery manufactured by the method for manufacturing a laminate battery according to the embodiment of the present invention, the following description will be made by comparing the embodiment and the comparative example with each other.

Example one

The method for manufacturing the n-type silicon heterojunction-perovskite laminated cell provided by the embodiment of the invention comprises the following specific steps:

the first step is as follows: an N-type M2 silicon wafer having a resistivity of 2-4. omega. cm and a thickness of 180 μ M was provided. And polishing, texturing and cleaning the silicon wafer to form the n-type monocrystalline silicon substrate with the textured surface.

The second step is that: intrinsic amorphous silicon passivation layers are respectively deposited on two sides of an n-type monocrystalline silicon substrate by adopting a Plasma Enhanced Chemical Vapor Deposition (abbreviated as PECVD) method to form a front passivation layer film and a back passivation layer film. The thickness of the front passivation layer film and the back passivation layer film was 5 nm.

The third step: depositing phosphorus doping (doping concentration) on the front surface of the silicon wafer by adopting a PECVD method10²⁰cm^-3) The thickness of the N-type amorphous silicon layer is 10nm, and a front emitter is formed.

The fourth step: depositing boron doping (doping concentration 10) on the back of the silicon wafer by adopting a PECVD method¹⁹cm^-3) The thickness of the P-type amorphous silicon layer is 10nm, and a back surface field structure is formed.

The fifth step: and preparing the ITO transparent conducting layer with the thickness of 100nm on the P-type amorphous silicon layer by adopting a magnetron sputtering process.

And a sixth step: and respectively manufacturing phosphorus and boron doped microcrystalline silicon films with the thickness of 8nm on the suede of the bottom cell to form a tunneling composite layer.

The seventh step: and co-depositing manganese sulfide and lead oxide on the suede of the bottom cell by adopting a vacuum thermal evaporation process to prepare a hole transport layer. The mass ratio of manganese sulfide to lead oxide is 1: 0.25. by controlling the current, the vacuum thermal evaporation rates of the manganese sulfide and the lead oxide are both

The hole transport layer thickness was 15 nm.

Eighth step: and co-depositing lead iodide and cesium bromide on the hole transport layer by adopting a vacuum evaporation mode to obtain the anchoring layer. Wherein the vacuum evaporation rate of the lead iodide is

Cesium bromide has a vacuum evaporation rate of

The thickness of the anchoring layer was 350 nm.

The ninth step: preparing a mixed solution of formamidine hydroiodide (abbreviated as FAI) and formamidine hydrobromide (abbreviated as FABr) at a molar ratio of 3:1 in ethanol. And (3) coating 100 mu L of mixed solution of FAI and FABr on the anchoring layer in a spinning mode, and reacting to form the perovskite absorption material film.

The tenth step: and annealing the perovskite absorption material film to form a dense and uniform perovskite absorption layer with the thickness of 500 nm. The annealing temperature is 150 ℃, the annealing time is 30min, and the perovskite absorption layer material component is Cs_xFA_1-xPb(Br_yI_1-y)₃。

The eleventh step: and evaporating LiF on the perovskite absorption layer to form a LiF electron transport interface layer with the thickness of 1 nm. Then, C was vapor-deposited on the LiF electron transporting interfacial layer to a thickness of 10nm₆₀Form C₆₀An electron transport interfacial layer.

The twelfth step: atomic Layer Deposition (ALD) to produce SnO with a thickness of 10nm₂An electron transport layer.

The thirteenth step: and (3) preparing the ITO transparent conductive film with the thickness of 100nm by adopting a magnetron sputtering method. And then, manufacturing a silver electrode grid line on the ITO transparent conductive film by using an evaporation method to obtain the laminated cell, wherein the thickness of the silver electrode grid line is 100 nm.

Example two

the first step is as follows: an N-type M2 silicon wafer having a resistivity of 5-10. omega. cm and a thickness of 50 μ M was provided. And polishing, texturing and cleaning the silicon wafer to form the n-type monocrystalline silicon substrate with the textured surface.

The second step is that: intrinsic amorphous silicon passivation layers are respectively deposited on two sides of an n-type monocrystalline silicon substrate by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a front passivation layer film and a back passivation layer film. The thickness of the front passivation layer film and the back passivation layer film was 1 nm.

The third step: adopting a PECVD method to deposit phosphorus doping (doping concentration is 10) on the front surface of a silicon wafer²⁰cm^-3) The thickness of the N-type amorphous silicon layer is 1nm, and a front emitter is formed.

The fourth step: depositing boron doping on the back of the silicon wafer by adopting a PECVD methodHetero (doping concentration 10)¹⁹cm^-3) The thickness of the P-type amorphous silicon layer is 1nm, and a back surface field structure is formed.

The fifth step: and preparing the transparent conductive layer made of IZO material with the thickness of 30nm on the P-type amorphous silicon layer by adopting a magnetron sputtering process.

And a sixth step: and respectively manufacturing phosphorus and boron doped microcrystalline silicon films with the thickness of 7nm on the suede of the bottom cell to form a tunneling composite layer.

The seventh step: and co-depositing zinc sulfide and lead chloride above the suede of the bottom cell by adopting a vacuum thermal evaporation process to prepare a hole transport layer. The mass ratio of zinc sulfide to lead chloride is 1: 0.01. by controlling the current, the vacuum thermal evaporation rates of the zinc sulfide and the lead chloride are both controlled

The hole transport layer thickness was 5 nm.

Cesium bromide has a vacuum evaporation rate of

The thickness of the anchoring layer was 250 nm.

The tenth step: and annealing the perovskite absorption material film to form a dense and uniform perovskite absorption layer with the thickness of 200 nm. The temperature of the annealing treatment was 50 ℃ and the time of the annealing treatment was 5 min.

The eleventh step: evaporating LiF on the perovskite absorption layer to form LiF electron transport layer with the thickness of 0.1nmAnd an interface transmission layer. Then, C was vapor-deposited on the LiF electron transporting interfacial layer to a thickness of 1nm₆₀Form C₆₀An electron transport interfacial layer.

The twelfth step: fabrication of 30nm thick SnO by Atomic Layer Deposition (ALD)₂An electron transport layer.

The thirteenth step: the IZO transparent conductive film with the thickness of 100nm is manufactured by adopting a magnetron sputtering method. And then, manufacturing a silver electrode grid line on the IZO transparent conductive film by using a vapor deposition method to obtain the laminated cell, wherein the thickness of the silver electrode grid line is 200 nm.

EXAMPLE III

the first step is as follows: an N-type M2 silicon wafer having a resistivity of 1-5. omega. cm and a thickness of 200 μ M was provided. And polishing, texturing and cleaning the silicon wafer to form the n-type monocrystalline silicon substrate with the textured surface.

The second step is that: intrinsic amorphous silicon passivation layers are respectively deposited on two sides of an n-type monocrystalline silicon substrate by adopting a Plasma Enhanced Chemical Vapor Deposition (abbreviated as PECVD) method to form a front passivation layer film and a back passivation layer film. The thickness of the front passivation layer film and the back passivation layer film was 20 nm.

The third step: adopting a PECVD method to deposit phosphorus doping (doping concentration is 10) on the front surface of a silicon wafer²⁰cm^-3) The thickness of the N-type amorphous silicon layer is 30nm, and a front emitter is formed.

The fourth step: depositing boron doping (doping concentration 10) on the back of the silicon wafer by adopting a PECVD method¹⁹cm^-3) The thickness of the P-type amorphous silicon layer and the N-type amorphous silicon layer is 30nm, and a back surface field structure is formed.

The fifth step: and preparing an IWO transparent conducting layer with the thickness of 120nm on the P-type amorphous silicon layer by adopting a magnetron sputtering process.

And a sixth step: and respectively manufacturing phosphorus and boron doped microcrystalline silicon films with the thickness of 30nm on the suede of the bottom cell to form a tunneling composite layer.

The seventh step: and co-depositing a mixture of nickel sulfide and titanium disulfide and lead iodide above the suede of the bottom cell by adopting a vacuum thermal evaporation process to prepare a hole transport layer. The mass ratio of the mixture of nickel sulfide and titanium disulfide to the lead iodide is 1: 0.5. controlling the current to ensure that the vacuum thermal evaporation rates of the mixture of the nickel sulfide and the titanium disulfide and the lead iodide are both

The hole transport layer thickness was 100 nm.

Eighth step: co-depositing lead bromide and cesium iodide on the hole transport layer by adopting a vacuum evaporation method, wherein the vacuum evaporation rate of the lead bromide is

The vacuum evaporation rate of cesium iodide is

The thickness of the anchoring layer was 1000 nm.

The tenth step: and annealing the perovskite absorption material film to form a compact and uniform perovskite absorption layer with the thickness of 1000 nm. The temperature of the annealing treatment was 200 ℃ and the time of the annealing treatment was 30 min.

The eleventh step: and evaporating LiF on the perovskite absorption layer to form a LiF electron transport interface layer with the thickness of 10 nm. Then, C was vapor-deposited on the LiF electron transporting interfacial layer to a thickness of 20nm₆₀Form C₆₀An electron transport interfacial layer.

The twelfth step: atomic Layer Deposition (ALD) to produce SnO having a thickness of 1nm₂An electron transport layer.

The thirteenth step: an IWO transparent conductive film with the thickness of 30nm is manufactured by adopting a magnetron sputtering method. And then, manufacturing a silver electrode grid line on the IWO transparent conductive film by using an evaporation method to obtain the laminated cell, wherein the thickness of the silver electrode grid line is 500 nm.

Example four

the first step is as follows: an N-type M2 silicon wafer having a resistivity of 1. omega. cm-4. omega. cm and a thickness of 150 μ M was provided. And polishing, texturing and cleaning the silicon wafer to form the n-type monocrystalline silicon substrate with the textured surface.

The second step is that: intrinsic amorphous silicon passivation layers are respectively deposited on two sides of an n-type monocrystalline silicon substrate by adopting a Plasma Enhanced Chemical Vapor Deposition (abbreviated as PECVD) method to form a front passivation layer film and a back passivation layer film. The thickness of the front passivation layer film and the back passivation layer film was 15 nm.

The third step: adopting a PECVD method to deposit phosphorus doping (doping concentration is 10) on the front surface of a silicon wafer²⁰cm^-3) The thickness of the N-type amorphous silicon layer is 15nm, and a front emitter is formed.

The fourth step: depositing boron doping (doping concentration 10) on the back of the silicon wafer by adopting a PECVD method¹⁹cm^-3) The thickness of the P-type amorphous silicon layer is 15nm, and a back surface field structure is formed.

The fifth step: and preparing an ITiO transparent conducting layer with the thickness of 70nm on the P-type amorphous silicon layer by adopting a magnetron sputtering process.

And a sixth step: and respectively manufacturing phosphorus-doped and boron-doped microcrystalline silicon films with the thickness of 15nm on the suede of the bottom cell to form a tunneling composite layer.

The seventh step: and co-depositing molybdenum disulfide and lead bromide above the suede of the bottom cell by adopting a vacuum thermal evaporation process to prepare a hole transport layer. The mass ratio of molybdenum disulfide to lead bromide is 1: 0.45. by controlling the current, the vacuum thermal evaporation rates of the molybdenum disulfide and the lead bromide are both

The hole transport layer thickness was 55 nm.

Eighth step: and co-depositing lead iodide, tin iodide and cesium chloride on the hole transport layer by adopting a vacuum evaporation mode to obtain the anchoring layer. Wherein the vacuum evaporation rate of the lead iodide and the tin iodide is

The vacuum evaporation rate of the cesium chloride is

The thickness of the anchoring layer was 500 nm.

The tenth step: and annealing the perovskite absorption material film to form a dense and uniform perovskite absorption layer with the thickness of 100 nm. The temperature of the annealing treatment was 170 ℃ and the time of the annealing treatment was 60 min.

The eleventh step: and evaporating LiF on the perovskite absorption layer to form a LiF electron transport interface layer with the thickness of 5 nm. Then, C was vapor-deposited on the LiF electron transporting interfacial layer to a thickness of 15nm₆₀Form C₆₀An electron transport interfacial layer.

The twelfth step: fabrication of SnO with a thickness of 15nm by Atomic Layer Deposition (ALD)₂An electron transport layer.

The thirteenth step: and preparing the ITiO transparent conductive film with the thickness of 200nm by adopting a magnetron sputtering method. And then, manufacturing a silver electrode grid line on the ITiO transparent conductive film by using an evaporation method to obtain the laminated cell, wherein the thickness of the silver electrode grid line is 255 nm.

EXAMPLE five

The seventh step: and co-depositing magnesium sulfide, lead thiocyanate and lead acetate mixture on the suede of the bottom battery by adopting a vacuum thermal evaporation process to manufacture a hole transport layer. The mass ratio of the nickel sulfide and the mixture of lead thiocyanate and lead acetate is 1: 0.5. the vacuum thermal evaporation rate of the nickel sulfide and the mixture of the lead thiocyanate and the lead acetate is controlled by controlling the current

The hole transport layer thickness was 100 nm.

Eighth step: co-depositing lead chloride and cesium iodide on the hole transport layer by adopting a vacuum evaporation method, wherein the vacuum evaporation rate of the lead chloride is

The vacuum evaporation rate of cesium iodide is

The thickness of the anchoring layer was 1000 nm.

Comparative example 1

The method for manufacturing the laminate battery provided in this comparative example is substantially the same as that described in the first example, except that: the material of the hole transport layer is Spiro-TTB.

Comparative example No. two

The method for manufacturing the laminate battery provided in this comparative example is substantially the same as that described in the first example, except that: the hole transport layer is made of nickel oxide.

To verify the performance of the tandem cells, the tandem cells prepared in example one, comparative example one and comparative example two were subjected to Scanning Electron Microscope (SEM) and I-V tests, and the photoelectric conversion efficiency, fill factor, open circuit voltage, short circuit current, and other performance parameters of each device were compared (table 1).

TABLE 1 Performance parameters of the laminate Battery

As can be seen from table 1, the performance parameters of the laminate battery manufactured by using manganese sulfide and an inorganic lead compound as hole transport materials are obviously superior to those of the currently widely used Spiro-type and nickel oxide materials.

Fig. 4 shows a suede cross-sectional SEM image of the tandem cell manufactured in the first embodiment, and fig. 5 is a suede SEM image of the tandem cell manufactured in the first embodiment, and it can be seen from fig. 4 and 5 that the lower surface of the perovskite layer is tightly attached to the bottom cell, no interface void and peeling phenomenon occurs, the perovskite thin film grows uniformly, and no obvious grain boundary defect exists, thereby proving that the tandem cell manufactured by using the method of the first embodiment of the present invention can maintain the suede structure of the bottom cell, and increase the efficiency of the tandem cell.

Fig. 6 shows I-V curves of the stacked cells prepared in the first example, the first comparative example and the second comparative example of the present invention under am1.5g solar light intensity irradiation. As can be seen from fig. 6, the short-circuit current J of the stacked battery prepared in the first embodiment_scIs 20.0mA/cm²Open circuit voltage V_ocAt 1.68V, fill was 77% since FF, and the final cell conversion efficiency was 26.0%. The performance parameters of each device of the laminated battery prepared in the first embodiment are obviously superior to those of the traditional laminated battery.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A laminate battery, comprising:

a bottom cell having a textured surface;

a hole transport layer formed over the textured surface, the hole transport layer being formed by vacuum co-deposition of a metal sulfide hole transport material and an inorganic lead compound, the metal sulfide having a band gap of not less than 1.6eV, the inorganic lead compound being one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanide, and lead acetate;

a perovskite absorption layer formed on the hole transport layer, the perovskite absorption layer containing lead ions.

2. The laminate battery according to claim 1, wherein the mass ratio of the metal sulfide and the inorganic lead compound is 1: (0.01-0.5).

3. The laminate battery of claim 1, wherein the metal sulfide comprises one or more of manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, digallium trisulfide, gallium monosulfide, germanium sulfide, germanium monosulfide, diarsenium trisulfide, tin disulfide, tungsten disulfide, and lead sulfide.

4. The laminate battery of claim 1, wherein the perovskite absorption layer has the general chemical formula ABX₃(ii) a Wherein the content of the first and second substances,

a is one or more of alkylamine cation, ethylenediamine cation and cesium cation, and B is the alkali metal cation and Pb²⁺、Sn²⁺Is one or more of, X is I^-、Cl^-、Br^-One or more of (a).

5. The laminate battery of any one of claims 1-4, wherein the thickness of the perovskite absorption layer is from 100nm to 1000 nm; and/or the presence of a gas in the gas,

the thickness of the hole transport layer is 5nm-100 nm.

6. The stack of any of claims 1-4, further comprising a tunneling composite layer formed over the pile surface, the hole transport layer being formed on the tunneling composite layer.

7. A method of fabricating a laminate battery, comprising:

providing a bottom battery, wherein the bottom battery is provided with a suede;

co-depositing a metal sulfide hole transport material and an inorganic lead compound above the suede by adopting a vacuum co-deposition process to form a hole transport layer; the band gap of the metal sulfide is not less than 1.6eV, and the inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate and lead acetate;

forming an anchoring layer on the hole transport layer through vacuum deposition, wherein the anchoring layer contains a metal halide; the metal halide at least comprises a lead halide;

coating the anchoring layer with a cationic salt by a solution method; the anchoring layer contains a material that reacts with the cationic salt to form a perovskite absorption layer;

manufacturing an electron transport layer on the perovskite absorption layer;

and manufacturing an electrode on the electron transport layer.

8. The method for manufacturing a laminate battery as claimed in claim 7, wherein the metal halide further comprises one or both of tin halide and alkali metal halide.

9. The method for manufacturing a stacked battery as claimed in claim 7 or 8, wherein the co-depositing the metal sulfide and the inorganic lead compound on the textured surface by using the vacuum co-deposition process to form the hole transport layer comprises: co-depositing a metal sulfide and an inorganic lead compound above the suede by adopting a vacuum thermal evaporation process to obtain a hole transport layer; the vacuum thermal evaporation rate of the metal sulfide and the inorganic lead compound is

10. The method for manufacturing a stacked battery according to claim 8, wherein the forming of the anchor layer by vacuum deposition over the hole transport layer comprises: co-depositing metal halide on the hole transport layer by adopting a vacuum evaporation method to obtain an anchoring layer; the vacuum evaporation rate of the alkali metal halide is

The vacuum evaporation rate of the lead halide and the tin halide is

11. The method for manufacturing a laminate battery as claimed in claim 7 or 8, wherein the step of coating the anchoring layer with a cation salt by a solution method comprises: coating a cationic salt solution on the anchoring layer by a solution method, so that metal halide contained in the anchoring layer reacts with the cationic salt to form a perovskite absorption layer; and/or the presence of a gas in the gas,

after the cation salt is formed on the anchoring layer by adopting a solution method and before the electron transport layer is manufactured on the perovskite absorption layer, the manufacturing method of the laminated battery further comprises the following steps: annealing the perovskite absorption layer; the temperature of the annealing treatment is 50-200 ℃, and the time of the annealing treatment is 5-60 minutes.

12. The method for manufacturing a laminate battery as claimed in claim 7 or 8, wherein before the step of manufacturing the electron transport layer on the perovskite absorption layer, the method for manufacturing a laminate battery further comprises: forming an electron-transporting interfacial layer on the perovskite absorption layer; the electron transport interface layer comprises a LiF layer and C₆₀A layer; the LiF layer is formed on the perovskite absorption layer, and the C layer₆₀Forming a layer on the LiF layer; wherein the thickness of the LiF layer is 0.1nm-10nm, and the C layer is₆₀The thickness of the layer is 1nm-20 nm;

and/or the presence of a gas in the gas,

before the hole transport layer is formed on the textured surface, the method for manufacturing the laminated cell further comprises the following steps: and forming a tunneling composite layer above the suede.