CN110970455B - 一种Micro-LED芯片及其制备方法、显示装置 - Google Patents
一种Micro-LED芯片及其制备方法、显示装置 Download PDFInfo
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- CN110970455B CN110970455B CN201811133686.6A CN201811133686A CN110970455B CN 110970455 B CN110970455 B CN 110970455B CN 201811133686 A CN201811133686 A CN 201811133686A CN 110970455 B CN110970455 B CN 110970455B
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Abstract
本申请公开一种Micro‑LED芯片及其制备方法、显示装置,该Micro‑LED芯片包括:驱动背板和发光芯片,驱动背板和发光芯片均包括电极,其中:驱动背板的电极上方形成有凹槽,凹槽的底部露出驱动背板的电极;凹槽内填充有导电材料,驱动背板的电极通过凹槽内的导电材料与发光芯片的电极连接,凹槽内的导电材料由导电材料对应的导电墨水固化得到,导电墨水通过喷墨打印的方法打印到凹槽内。发光芯片的电极通过固化后的导电墨水与驱动背板的电极连接,相较于直接将发光芯片的电极与驱动背板的电极焊接而言,由于电极与固化后的导电墨水之间的接触性较好,因此,可以有效改善发光芯片的电极与驱动背板的电极之间的接触性能,提高电极之间连接的可靠性。
Description
技术领域
本申请涉及显示技术领域,尤其涉及一种Micro-LED芯片及其制备方法、显示装置。
背景技术
Micro-LED芯片是一种新型的显示芯片,具有自发光、薄型、高效率、高亮度、高解析度、反应时间快等特点,被越来越多的应用到各个显示以及照明领域。
通常,Micro-LED芯片可以包括发光芯片和驱动背板两部分,其中,由于工艺流程的不可兼容,发光芯片和驱动背板需要分别制备得到,在制备得到发光芯片和驱动背板后,可以将发光芯片的电极和驱动背板的电极焊接,以驱动发光芯片发光。
然而,在实际应用中,由于发光芯片的电极和驱动背板的电极尺寸较小,因此,很难有效地将发光芯片的电极和驱动背板的电极焊接,从而影响Micro-LED芯片的性能。
发明内容
本申请提供一种Micro-LED芯片及其制备方法、显示装置,用于解决现有技术中无法有效地将Micro-LED芯片中发光芯片的电极和驱动背板的电极进行有效焊接的问题。
本申请实施例提供一种Micro-LED,包括:驱动背板和发光芯片,所述驱动背板和所述发光芯片均包括电极,其中:
所述驱动背板的电极上方形成有凹槽,所述凹槽的底部露出所述驱动背板的电极;
所述凹槽内填充有导电材料,所述驱动背板的电极通过所述凹槽内的导电材料与所述发光芯片的电极连接,所述凹槽内的导电材料由所述导电材料对应的导电墨水固化得到。优选地,所述导电墨水为纳米银线导电墨水或纳米铜线导电墨水,所述导电墨水通过喷墨打印的方法打印到所述凹槽内。
可选地,所述凹槽的个数为多个,不同凹槽的顶端位于同一水平面上。
可选地,所述凹槽沿垂直于所述驱动背板方向上的截面的形状为弧形、矩形、梯形或其他多边形。
本申请实施例提供一种Micro-LED芯片的制备方法,包括:
提供驱动背板和发光芯片,所述驱动背板和所述发光芯片均包括电极;
在所述驱动背板的电极上方形成凹槽,所述凹槽的底部露出所述驱动背板的电极;
在所述凹槽内打印导电墨水;
将发光芯片的电极与所述凹槽内的导电墨水对位接触;
固化所述导电墨水,使得所述发光芯片的电极通过固化后的所述导电墨水与所述驱动背板的电极连接。
可选地,所述凹槽的个数为多个,不同凹槽的顶端位于同一水平面上;
所述凹槽沿垂直于所述驱动背板方向上的截面的形状为弧形、矩形、梯形或其他多边形。
可选地,在驱动背板的电极上方形成凹槽,包括:
在驱动背板的电极上方涂抹光刻胶;
对所述光刻胶进行图案化,使得所述光刻胶在所述驱动背板的电极处形成凹槽,所述凹槽的底部露出所述驱动背板的电极。
可选地,在所述凹槽内打印导电墨水,包括:
通过喷墨打印的方式在所述凹槽内打印所述导电墨水;或,
通过喷墨打印的方式在所述凹槽内打印导电墨水前驱体;对所述导电墨水前驱体进行光子烧结处理,得到所述导电墨水。
可选地,所述导电墨水为纳米银线导电墨水或纳米铜线导电墨水,当所述导电墨水或所述导电墨水前驱体的高度等于设定高度时停止打印,所述设定高度小于所述凹槽顶端的高度。
可选地,将发光芯片的电极与所述凹槽内的导电墨水对位接触,包括:
将所述发光芯片的电极与所述凹槽内的导电墨水对位,并将所述发光芯片的电极浸入所述导电墨水中。
可选地,固化所述导电墨水,包括:
对所述导电墨水进行红外烧结处理,将所述导电墨水转化为导电材料,使得所述发光芯片的电极通过所述导电材料与所述驱动背板的电极连接。
本申请实施例还提供一种显示装置,包括:上述记载的Micro-LED芯片或者通过上述记载的Micro-LED芯片的制备方法制备得到的Micro-LED芯片。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果:
(1)通过在驱动背板的电极侧形成凹槽,并在凹槽内打印导电墨水,发光芯片的电极通过导电墨水固化后的导电材料与驱动背板的电极连接,相较于直接将发光芯片的电极与驱动背板的电极焊接而言,由于电极与固化后的导电材料之间的接触性较好,因此,可以有效改善发光芯片的电极与驱动背板的电极之间的接触性能,提高电极之间连接的可靠性;
(2)在凹槽内打印导电墨水,导电墨水固化后,凹槽可以对固化后的导电材料起保护作用,避免导电材料脱落;
(3)对位精度高,可以实现小于20微米级别的电极连接;
(4)在驱动背板电极侧的凹槽内打印导电墨水时,不同凹槽内打印的导电墨水的高度可以在同一水平面上,这样,在将发光芯片的电极与驱动背板的电极连接时,发光芯片的电极可以通过处于同一水平面上导电墨水与驱动背板的电极进行有效连接,进而避免由于驱动背板的电极高度差异大导致的不能与发光芯片的电极进行有效连接的问题。
附图说明
此处所说明的附图用来提供对本申请的进一步理解,构成本申请的一部分,本申请的示意性实施例及其说明用于解释本申请,并不构成对本申请的不当限定。在附图中:
图1为现有技术中的一种Micro-LED芯片的结构示意图;
图2为本申请实施例提供的一种Micro-LED芯片的结构示意图;
图3为本申请实施例提供的一种Micro-LED芯片的制备方法的流程示意图;
图4至图10为本申请实施例提供的一种Micro-LED芯片的制备方法的示意图。
具体实施方式
通常,在制备Micro-LED芯片时,由于工艺流程的不可兼容,需要分别制备Micro-LED芯片中包含的发光芯片和驱动背板。在制备得到发光芯片和驱动背板后,可以将发光芯片的电极和驱动背板的电极连接,以驱动发光芯片发光。
现有技术中,通常采用倒装焊工艺将发光芯片的电极和驱动背板的电极进行焊接。
具体地,如图1所示,首先,可以在驱动背板11的电极111和电极112上制备焊料12;其次,倒装发光芯片13,并将发光芯片13的电极131和电极132分别与驱动背板11的电极111和电极112进行对位;最后,在高温高压的条件下进行焊接,实现发光芯片13的电极131和电极132与驱动背板11的电极111和电极112之间的电学连通。
然而,在实际应用中,由于驱动背板的电极高度差异较大,因此,在将发光芯片的电极和驱动背板的电极对位焊接时,驱动背板中的部分电极与发光芯片的电极距离较近,部分电极与发光芯片的电极距离较远,这样,针对距离发光芯片电极较远的驱动背板电极而言,很容易出现焊接接触不良等现象,从而影响Micro-LED芯片的性能。
此外,针对距离发光芯片电极较远的驱动背板电极而言,也可以通过涂抹较多的焊料来保证与发光芯片的电极之间的有效连接。然而,由于发光芯片的尺寸较小,因此,过多的焊料很容易与周围的电极相互接触,导致电极之间短路,从而影响Micro-LED芯片的性能。
由此可见,现有技术中很难将Micro-LED芯片中发光芯片的电极和驱动背板的电极进行有效焊接。
有鉴于此,本申请实施例提供一种Micro-LED芯片及其制备方法、显示装置,可以有效解决上述无法将Micro-LED芯片中发光芯片的电极和驱动背板的电极进行有效焊接的问题。
下面结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然,所描述的实施例仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
需要说明的是,本申请实施例中记载的驱动背板可以是TFT背板,发光芯片可以是Micro-LED发光芯片。其中,所述驱动背板的一侧可以分布有多个电极(包括阳极和阴极),所述发光芯片的一侧也分布有多个电极(包括阳极和阴极),在制备Micro-LED芯片时,需要将所述驱动背板的阳极和阴极分别与发光芯片的阳极和阴极连接。
通常,所述驱动背板中电极的尺寸以及所述发光芯片中电极的尺寸都在几十微米左右,通过直接焊接的方式很难将所述驱动背板的电极与所述发光芯片的电极进行有效焊接。本申请实施例提供的技术方案,可以有效改善所述驱动背板的电极与所述发光芯片的电极之间的接触性能,提高电极之间连接的可靠性。
以下结合附图,详细说明本申请各实施例提供的技术方案。
图2为本申请实施例提供的一种的Micro-LED芯片的结构示意图。所述Micro-LED芯片的结构如下所述。
图2中,Micro-LED芯片可以包括驱动背板21和发光芯片22,其中,驱动背板21包括电极211,发光芯片22包括电极221。
驱动背板21的电极上方形成有凹槽a,凹槽a的底部露出电极211。其中,凹槽a的形成过程可以包括:在驱动背板21的电极上方涂抹光刻胶23,在电极211的位置对光刻胶23进行图案化,形成凹槽。
凹槽a内填充有导电材料24,导电材料24由所述导电材料24对应的导电墨水固化得到,所述导电墨水可以通过喷墨打印的方法打印到凹槽a内。图4中,凹槽a内导电材料24的高度低于凹槽a的深度(即凹槽a的顶端)。
需要说明的是,在实际应用中,在驱动背板电极处形成的凹槽的个数为多个(图2仅示出了1个),其中,不同凹槽的顶端可以位于同一水平面,这样,在凹槽内打印导电墨水时,可以保证驱动背板的电极通过导电墨水处于同一水平面上,在将发光芯片的电极与驱动背板的电极连接时,发光芯片的电极可以通过处于同一水平面上导电墨水与驱动背板的电极进行有效连接,进而避免由于驱动背板的电极高度差异大导致的不能与发光芯片的电极进行有效连接的问题。
针对其中一个凹槽而言,优选地,所述凹槽沿垂直于驱动背板21方向(即图2中的X方向)上的截面的形状为梯形,可以提升电极连接的稳定性和可靠性。在其他实现方式中,所述截面的形状还可以是弧形、矩形或其他多边形。
图2中,驱动背板21的电极211可以直接通过凹槽a内的导电材料24与发光芯片22的电极221连接。这样,将发光芯片的电极通过固化得到的导电材料与驱动背板的电极连接,相较于直接将驱动背板的电极与发光芯片的电极焊接而言,由于电极与固化后的导电材料连接的接触性较好,因此,可以有效改善电极之间的接触性能,提高电极之间连接的可靠性。
为了制备得到本申请实施例记载的Micro-LED芯片,本申请实施例还提供一种Micro-LED芯片的制备方法。所述Micro-LED芯片的制备方法的流程示意图可以如图3所示。图3所示的制备方法可以制备得到图2所示的Micro-LED芯片。所述制备方法如下所述。
步骤302:提供驱动背板和发光芯片。
在制备Micro-LED芯片时,可以提供用于制备得到Micro-LED芯片的驱动背板和发光芯片,其中,所述驱动背板可以是TFT背板,所述发光芯片可以是Micro-LED发光芯片,所述驱动背板和所述发光芯片均包括电极。
本申请实施例提供的制备Micro-LED芯片的方法可以用于将所述驱动背板的电极与所述发光芯片的电极连接。
步骤304:在驱动背板的电极上方形成凹槽。
在步骤304中,在将发光芯片的电极与驱动背板的电极进行连接时,可以在驱动背板的电极上方(即驱动背板的电极所在侧)形成凹槽。
在所述驱动背板的电极上方形成凹槽,可以是在所述驱动背板的每一个电极上方均形成凹槽,针对其中一个电极以及该电极上方形成的凹槽而言,所述凹槽的底部需要露出所述电极。其中,所述凹槽可以露出所述电极的一部分,也可以露出所述电极的全部。
所述凹槽沿垂直于所述驱动背板方向上的截面的形状可以是弧形、矩形、梯形或其他多边形,其中,优选地,所述梯形可以是正梯形(上窄下宽),也可以是倒梯形(上宽下窄),可以提升电极连接的稳定性和可靠性。
本申请实施例中,由于所述驱动背板的电极的个数为多个,因此,在所述驱动背板的电极上方形成的凹槽可以是多个,其中,不同凹槽的顶端可以位于同一水平面上,这样,可以便于后续在凹槽内填充导电材料时,能够保证驱动背板的电极通过导电材料处于同一水平面上,在将发光芯片的电极与驱动背板的电极连接时,发光芯片的电极可以通过处于同一水平面上导电材料与驱动背板的电极进行有效连接,进而避免由于驱动背板的电极高度差异大导致的不能与发光芯片的电极进行有效连接的问题。
本申请的一个实施例中,在驱动背板的电极上方形成凹槽,可以包括:
在驱动背板的电极上方涂抹光刻胶;
对所述光刻胶进行图案化,使得所述光刻胶在所述驱动背板的电极处形成凹槽,所述凹槽的底部露出所述驱动背板的电极。
具体地,首先,可以在所述驱动背板的电极上方形成光刻胶,其中,所述光刻胶远离所述驱动背板的一侧可以是平面,这样,可以保证后续形成的凹槽的顶端位于同一水平面上。
其次,可以对所述光刻胶进行图案化,其中,图案化的具体步骤可以包括:曝光、显影和清洗。其中,在对所述光刻胶进行曝光时,曝光的区域可以是所述驱动背板的电极所在的区域。在对所述平光刻胶进行曝光处理后,可以对曝光后的光刻胶依次进行显影和清洗处理。
最后,所述光刻胶可以在所述驱动背板的电极处形成凹槽,其中,所述凹槽的底部露出所述驱动背板的电极。
在通过上述记载的方法在驱动背板的电极上方形成凹槽后,可以执行步骤306。
步骤306:在所述凹槽内打印导电墨水。
所述导电墨水可以理解为导电材料和液体的混合物,优选地,所述导电墨水可以是纳米银线导电墨水,固化后的纳米银线导电墨水与电极的接触性好,可以有效改善发光芯片的电极与驱动背板的电极之间的接触性能,提高电极之间连接的可靠性。可选地,所述导电墨水可以是纳米铜线导电墨水。应理解,所述导电墨水还可以是其他导电材料的导电墨水,这里不再一一举例说明。
在本申请的一个实施例中,在所述凹槽内打印导电墨水时,可以直接将所述导电墨水打印在所述凹槽内,其中,可以通过喷墨打印的方式将所述导电墨水打印在所述凹槽内,具体地,可以将导电墨水置于打印机的墨盒内,并选择打印精度较高且不易堵塞的喷头进行打印。
在本申请的另一个实施例中,在所述凹槽内打印导电墨水,可以包括:
在所述凹槽内打印导电墨水前驱体;
对所述导电墨水前驱体进行光子烧结处理,得到所述导电墨水。
本实施例可以不直接将导电墨水打印在所述凹槽内,而是首先在所述凹槽内打印所述导电墨水对应的导电墨水前驱体,然后,对所述导电墨水前驱体进行光子烧结处理,得到所述导电墨水,从而实现在所述凹槽内打印所述导电墨水的目的。其中,在进行光子烧结时,可以使用激光器。
本实施例在打印所述导电墨水前驱体时,也可以通过喷墨打印的方式进行打印。
在实际应用中,可以根据实际情况选择上述任一种方式在所述凹槽内打印导电墨水,其中,若采用喷墨打印的方式在所述凹槽内打印导电墨水,则可以根据喷头孔径的大小,确定选择哪种打印方式。
具体地,当喷头的孔径较小时,可以选择打印导电墨水前驱体,并通过光子烧结形成导电墨水,这样,可以避免直接打印导电墨水导致的喷头孔径阻塞的问题;当喷头的孔径较大时,可以选择直接打印导电墨水,这样,相较于打印导电墨水前驱体而言,可以简化工艺流程。
本申请实施例中,在所述凹槽内打印导电墨水或导电墨水前驱体时,为了避免所述导电墨水或所述导电墨水前驱体溢出所述凹槽,当所述导电墨水的高度等于设定高度时,可以停止打印,其中,所述设定高度小于所述凹槽顶端的高度,具体可以根据实际情况确定。
例如,当所述凹槽顶端高度在15至20微米时,所述设定高度可以是10至15微米。在实际应用中,也可以根据导电墨水(或导电墨水前驱体)的浓度确定所述设定高度,例如,当导电墨水的浓度较高时,所述设定高度可以低一些(例如,小于凹槽顶端高度的50%),当导电墨水的浓度较低时,所述设定高度可以高一些(例如,在凹槽顶端高度的60%至90%之间)。
在通过上述记载的方法在所述凹槽内打印导电墨水后,可以执行步骤308。
步骤308:将发光芯片的电极与所述凹槽内的导电墨水对位接触。
在步骤308中,在将发光芯片的电极与所述凹槽内的导电墨水对位接触时,首先,可以将发光芯片的电极置于所述凹槽的上方;其次,将发光芯片的电极对准所述导电墨水,并浸入到所述导电墨水中,保证发光芯片的电极与所述导电墨水之间充分接触。
在将发光芯片的电极浸入到所述凹槽内的导电墨水中时,为了避免导电墨水溢出,可以将发光芯片电极的一部分浸入到所述导电墨水中。
需要说明的是,在将发光芯片的电极浸入到所述导电墨水中之前,发光芯片的电极上可以无需涂抹焊料。
在将发光芯片的电极与所述凹槽内的导电墨水对位接触后,可以执行步骤310。
步骤310:固化所述导电墨水,使得所述发光芯片的电极通过固化后的所述导电墨水与所述驱动背板的电极连接。
在步骤310中,固化所述导电墨水可以理解为蒸发掉所述导电墨水中的液体,保留所述导电墨水中的导电材料。
本申请实施例中,固化所述导电墨水,可以包括:
对所述导电墨水进行红外烧结处理,将所述导电墨水转化为导电材料,使得所述发光芯片的电极通过所述导电材料与所述驱动背板的电极连接。
以所述导电墨水为纳米银线导线墨水为例,在对纳米银线导电墨水进行红外烧结后,可以蒸发掉纳米银线导电墨水中的液体,其中的纳米银线可以首位搭接在一起,并将发光芯片的电极与驱动背板的电极连接。整个红外烧结的过程可以视为固化纳米银线导线墨水的过程。
为了便于理解整个技术方案,可以参见图4至图10。图4至图10为本申请实施例提供的一种Micro-LED芯片的制备方法的示意图。
图4为驱动背板的示意图,图4中,驱动背板41的电极所在侧设有电极411。
图5中,在驱动背板41的电极上方形成凹槽a,凹槽a的底部露出电极411,凹槽a沿垂直于驱动背板41的方向(X方向)的截面形状为梯形,且梯形的形状为上宽下窄,这样,可以便于后续打印导电墨水(或导电墨水前驱体)。其中,形成凹槽a的具体形成过程可以参见图3所示实施例中记载的相关内容,这里不再重复描述。
在本申请的一个实施例中,在驱动背板41的电极上方形成凹槽a后,可以参见图6。图6中,可以通过喷墨打印的方式将纳米银线导电墨水42打印到凹槽a中,当纳米银线导电墨水42的高度等于设定高度时,停止打印,其中,所述设定高度小于凹槽a顶端的高度,具体可以根据实际情况确定,这里不做具体限定。
如图7所示,纳米银线导电墨水42填充凹槽a,且,纳米银线导电墨水42的高度低于凹槽a顶端的高度。
图8中,可以将发光芯片43的电极431与凹槽a中的纳米银线导电墨水42对位,并将电极431的一部分浸入到纳米银线导电墨水42中。此时,可以对纳米银线导电墨水42进行红外烧结处理,蒸发掉纳米银线导电墨水42中的液体,其中的纳米银线首尾搭接在一起,实现将发光芯片43的电极431与驱动背板41的电极411连接。
在本申请的另一个实施例中,在驱动背板41的电极上方形成凹槽a后,可以参见图9。图9中,可以通过喷墨打印的方式将纳米银线导电墨水前驱体44打印到凹槽a中,当纳米银线导电墨水前驱体44的高度等于设定高度时,停止打印,其中,所述设定高度小于凹槽a顶端的高度,具体可以根据实际情况确定,这里不做具体限定。
如图10所示,纳米银线导电墨水前驱体44填充凹槽a,且,纳米银线导电墨水前驱体44的高度低于凹槽a顶端的高度。
在凹槽a内打印纳米银线导电墨水前驱体44后,可以对纳米银线导电墨水前驱体44进行光子烧结处理,得到纳米银线导电墨水42,图7所示。
之后,可以将发光芯片44的电极441通过凹槽42中的纳米银线导电墨水43分别与驱动背板41的电极411以及412连接,具体请参见上述图8,这里不再重复说明。
需要说明的是,上述记载的图5中,在凹槽42中打印的纳米银线导电墨水43也可以由纳米铜线导电墨水代替,或者是其他导电材料的导电墨水,在图9,在凹槽42中打印的纳米银线导电墨水前驱体45也可以由纳米铜线导电墨水前驱体代替,或者是其他导电墨水前驱体,这里不再一一举例说明。
本申请实施例提供的Micro-LED芯片的制备方法至少能够达到以下有益效果:
(1)通过在驱动背板的电极侧形成凹槽,并在凹槽内打印导电墨水,发光芯片的电极通过导电墨水固化后的导电材料与驱动背板的电极连接,相较于直接将发光芯片的电极与驱动背板的电极焊接而言,由于电极与固化后的导电材料之间的接触性较好,因此,可以有效改善发光芯片的电极与驱动背板的电极之间的接触性能,提高电极之间连接的可靠性;
(2)在凹槽内打印导电墨水,导电墨水固化后,凹槽可以对固化后的导电材料起保护作用,避免导电材料脱落;
(3)对位精度高,可以实现小于20微米级别的电极连接;
(4)在驱动背板电极侧的凹槽内打印导电墨水时,不同凹槽内打印的导电墨水的高度可以在同一水平面上,这样,在将发光芯片的电极与驱动背板的电极连接时,发光芯片的电极可以通过处于同一水平面上导电墨水与驱动背板的电极进行有效连接,进而避免由于驱动背板的电极高度差异大导致的不能与发光芯片的电极进行有效连接的问题。
本申请实施例还提供一种显示装置,所述显示装置可以包括通过上述记载的Micro-LED芯片的制备方法制备得到的Micro-LED芯片。
本领域的技术人员应明白,尽管已描述了本申请的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例作出另外的变更和修改。所以,所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。
Claims (10)
1.一种Micro-LED芯片,其特征在于,包括:驱动背板和发光芯片,所述驱动背板和所述发光芯片均包括电极,其中:
所述驱动背板的电极上方形成有凹槽,所述凹槽的底部露出所述驱动背板的电极;
所述凹槽内填充有导电材料,所述驱动背板的电极通过所述凹槽内的导电材料与所述发光芯片的电极连接,所述凹槽内的导电材料由所述导电材料对应的导电墨水固化得到;
其中,所述导电材料为纳米银线,所述纳米银线的首尾搭接在一起,以将所述驱动背板的电极与所述发光芯片的电极连接。
2.如权利要求1所述的Micro-LED芯片,其特征在于,
所述凹槽的个数为多个,不同凹槽的顶端位于同一水平面上。
3.如权利要求1或2所述的Micro-LED芯片,其特征在于,
所述凹槽沿垂直于所述驱动背板方向上的截面的形状为弧形、矩形、梯形或其他多边形。
4.一种Micro-LED芯片的制备方法,其特征在于,包括:
提供驱动背板和发光芯片,所述驱动背板和所述发光芯片均包括电极;
在所述驱动背板的电极上方形成凹槽,所述凹槽的底部露出所述驱动背板的电极;
在所述凹槽内打印导电墨水;
将发光芯片的电极与所述凹槽内的导电墨水对位接触;
固化所述导电墨水,使得所述发光芯片的电极通过固化后的所述导电墨水与所述驱动背板的电极连接;
其中,所述导电墨水为纳米银线导电墨水,所述固化所述导电墨水,使得所述发光芯片的电极通过固化后的所述导电墨水与所述驱动背板的电极连接包括:固化所述纳米银线导电墨水,所述纳米银线首尾搭接在一起,使得所述发光芯片的电极通过固化后的所述纳米银线导电墨水与所述驱动背板的电极连接。
5.如权利要求4所述的方法,其特征在于,在驱动背板的电极上方形成凹槽,包括:
在驱动背板的电极上方涂抹光刻胶;
对所述光刻胶进行图案化,使得所述光刻胶在所述驱动背板的电极处形成凹槽,所述凹槽的底部露出所述驱动背板的电极。
6.如权利要求4所述的方法,其特征在于,在所述凹槽内打印导电墨水,包括:
通过喷墨打印的方式在所述凹槽内打印所述导电墨水;或,
通过喷墨打印的方式在所述凹槽内打印导电墨水前驱体;对所述导电墨水前驱体进行光子烧结处理,得到所述导电墨水。
7.如权利要求4或6所述的方法,其特征在于,
当所述导电墨水或所述导电墨水前驱体的高度等于设定高度时停止打印,所述设定高度小于所述凹槽顶端的高度。
8.如权利要求4所述的方法,其特征在于,将发光芯片的电极与所述凹槽内的导电墨水对位接触,包括:
将所述发光芯片的电极与所述凹槽内的导电墨水对位,并将所述发光芯片的电极浸入所述导电墨水中。
9.如权利要求4所述的方法,其特征在于,固化所述导电墨水,包括:
对所述导电墨水进行红外烧结处理,将所述导电墨水转化为导电材料,使得所述发光芯片的电极通过所述导电材料与所述驱动背板的电极连接。
10.一种显示装置,其特征在于,包括:如权利要求1-3任一项所述的Micro-LED芯片或如权利要求4至9任一项所述的Micro-LED芯片的制备方法制备得到的Micro-LED芯片。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101090610A (zh) * | 2006-06-16 | 2007-12-19 | 富士通株式会社 | 制造多层板的方法 |
CN107978665A (zh) * | 2017-11-16 | 2018-05-01 | 歌尔股份有限公司 | Micro LED制备方法 |
CN108365080A (zh) * | 2018-03-16 | 2018-08-03 | 易美芯光(北京)科技有限公司 | MicroLED或mini LED封装结构 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2981795B1 (fr) * | 2011-10-25 | 2015-01-02 | Commissariat Energie Atomique | Hybridation flip-chip de composants microelectroniques par chauffage local des elements de connexion |
CN104362134A (zh) | 2014-10-29 | 2015-02-18 | 广州丰江微电子有限公司 | 一种电路基板与散热器间低孔洞的纳米银线烧结工艺 |
US10192478B2 (en) * | 2015-11-17 | 2019-01-29 | Nthdegree Technologies Worldwide Inc. | LED display with patterned pixel landings and printed LEDs |
CN106847716A (zh) | 2017-02-28 | 2017-06-13 | 上海图正信息科技股份有限公司 | 一种芯片封装工艺 |
-
2018
- 2018-09-27 CN CN201811133686.6A patent/CN110970455B/zh active Active
-
2019
- 2019-04-19 WO PCT/CN2019/083546 patent/WO2020062845A1/zh active Application Filing
-
2020
- 2020-04-20 US US16/852,574 patent/US11081632B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101090610A (zh) * | 2006-06-16 | 2007-12-19 | 富士通株式会社 | 制造多层板的方法 |
CN107978665A (zh) * | 2017-11-16 | 2018-05-01 | 歌尔股份有限公司 | Micro LED制备方法 |
CN108365080A (zh) * | 2018-03-16 | 2018-08-03 | 易美芯光(北京)科技有限公司 | MicroLED或mini LED封装结构 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113471345A (zh) * | 2021-09-03 | 2021-10-01 | 罗化芯显示科技开发(江苏)有限公司 | Led芯片、led显示装置及其制造方法 |
CN113471345B (zh) * | 2021-09-03 | 2021-11-19 | 罗化芯显示科技开发(江苏)有限公司 | Led芯片、led显示装置及其制造方法 |
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