CN110970429A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110970429A
CN110970429A CN201910932072.2A CN201910932072A CN110970429A CN 110970429 A CN110970429 A CN 110970429A CN 201910932072 A CN201910932072 A CN 201910932072A CN 110970429 A CN110970429 A CN 110970429A
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China
Prior art keywords
layer
fin structure
gate
ferroelectric
dielectric
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Inventor
徐继兴
杨世海
蔡庆威
程冠伦
王志豪
曹敏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110970429A publication Critical patent/CN110970429A/zh
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Abstract

第一鳍片结构被设置于基板上。第一鳍片结构包含一半导体材料。栅极介电层被设置于第一鳍片结构的上部及侧表面上。栅极电极层被形成于栅极介电层上。第二鳍片结构被设置于基板上。第二鳍片结构与第一鳍片结构物理性地分隔，并包含一铁电材料。第二鳍片结构电性耦接至栅极电极层。

Description

半导体装置
技术领域
本公开涉及一种半导体装置，特别涉及一种包括铁电材料的负电容半导体装置。
背景技术
半导体集成电路(integrated circuit,IC)工业经历了快速的成长。在IC设计及IC材料的技术进步产生了许多世代的IC，与前一世代相比，每一世代的IC具有更小及更复杂的电路。在IC发展过程中，当几何尺寸(例如：制造工艺所能创造的最小组件(或线段))下降时，功能密度(例如：每单位芯片区域的互连装置的数量)通常都会增加。
晶体管是通常形成于半导体装置上的电路组件或元件。除了电容、电感、电阻、二极管、导电或其他元件之外，取决于电路设计，许多晶体管可形成于半导体装置上。场效晶体管(field effect transistor,FET)是晶体管的一种类型。通常来说，晶体管包括形成在源极区域与漏极区域之间的栅极堆叠。源极区域及漏极区域可包括基板的掺杂区，且可呈现适合用于特定应用的掺杂分布。栅极堆叠位于通道区域上方，且可包括夹设于(interpose)栅极电极与基板中的通道区域之间的栅极介电质。为了改进效能，可通过形成具有铁电材料(ferroelectric material)的栅极介电质来产生负电容(negativecapacitance)晶体管。然而，用于形成铁电材料的现有方法及装置仍可能需要改进，例如关于配置铁电材料的尺寸及/或位置的灵活性。
因此，尽管制造负电容装置的现有方法通常已足够用于它们的预期目的，但它们并非在所有方面都是完全令人满意的。
发明内容
本公开实施例提供一种半导体装置。上述半导体装置包括一基板。第一鳍片结构被设置于基板上。第一鳍片结构包含一半导体材料。栅极介电层被设置于第一鳍片结构的上部及侧表面上。栅极电极层被形成于栅极介电层上。第二鳍片结构被设置于基板上。第二鳍片结构与第一鳍片结构物理性地分隔，并包含一铁电材料。第二鳍片结构电性耦接至栅极电极层。
本公开实施例提供一种半导体装置。上述半导体装置包括形成于一基板中的通道区域。一栅极堆叠包括设置于通道区域上的栅极介电质，以及设置于栅极介电质上的栅极电极。一隔离结构被设置于栅极堆叠外部。一铁电层被设置于隔离结构上。铁电层电性耦接至栅极堆叠。
本公开提供一种制造半导体装置的方法。在半导体鳍片结构上形成一介电遮罩层。其中半导体鳍片结构自一基板向上突出。蚀刻介电遮罩层以形成一沟槽。通过在沟槽中沉积铁电材料以在沟槽中形成混合鳍片结构。至少在半导体鳍片结构上形成一栅极介电层。在半导体鳍片结构及混合鳍片结构上形成一栅极电极层。
附图说明
本公开实施例可通过阅读下列的详细说明及范例并配合对应的附图以更加详细地了解。需注意的是，依照业界的标准操作，各种特征并未依照比例绘制，且仅用于说明的目的。事实上，为了清楚论述，各种特征的尺寸可任意地增加或减少。
图1为FinFET装置的三维立体图。
图2A至图7A是根据一些实施例所示，范例性半导体装置的截面图。
图2B至图7B是根据一些实施例所示，范例性半导体装置的截面图。
图7C是根据一些实施例所示，范例性半导体装置的俯视图。
图8是根据一些实施例所示，半导体装置的电容模型。
图9A至图9C所示是各种材料的剩磁极化对矫顽电场的关系图表。
图10是根据一些实施例所示，范例性半导体装置的截面图。
图11是根据一些实施例所建构的制造半导体装置的范例性方法的流程图。
附图标记说明：
10～FinFET装置结构
12～外延生长材料
15～n型FinFET装置结构
25～p型FinFET装置结构
102～基板
104～鳍片结构
105～间隔物
108～隔离结构
110～栅极电极
112、114～硬遮罩层
115～介电层
200～半导体装置
210～基板
210A～鳍片结构
230～衬垫层
240～遮罩层
250～沟槽
300～铁电层
310～牺牲层
330～光阻材料
350～开口
370～介电层
400～虚拟栅极结构
420～工艺
440～介电层
450～介电组件
470～栅极间隔物
490～层间介电质
200A～n型晶体管
200B～p型晶体管
500～栅极替换工艺
510～界面层
530～高k值栅极介电质
540～金属栅极电极
550～导电结构
200C～n型晶体管
VG～栅极电压
Gnd～接地
CFE～电容
COX～栅极氧化物电容
CS～空乏区电容
CMOS～电容
705～源极区域
706～漏极区域
710～基板
710A～通道区域
720～界面层
730～高k值栅极介电层
740～金属栅极电极层
750～隔离结构
760～导电电极
770～铁电层
780～导电电极
790～电性连接机制
Vg、Vd、Vs～电性端子
900～方法
910-950～操作
具体实施方式
本公开提供许多不同的实施例或范例以实施本公开的不同特征。以下的公开内容叙述各个组件及其排列方式的特定实施例，以简化说明。理所当然的，这些特定的范例并非旨于限制。举例来说，若是本公开叙述了一第一特征形成于一第二特征之上或上方，即表示其可能包含上述第一特征与上述第二特征是直接接触的实施例，亦可能包含了有附加特征形成于上述第一特征与上述第二特征之间，而使上述第一特征与第二特征可能未直接接触的实施例。此外，以下本公开不同实施例可能重复使用相同的参考符号及/或标记。这些重复为了简化与清晰的目的，并非用以限制所讨论的不同实施例及/或结构之间有特定的关系。
此外，空间相对术语，例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，为了便于描述附图中一个元件或特征与另一个(些)元件或特征之间的关系。除了在附图中所描绘的方位外，这些空间相对术语意欲包含使用中或操作中的装置的不同方位。除此之外，设备可能被转向不同方位(旋转90度或其他方位)，则在此使用的空间相对术语也可相应地进行解释。
此外，当数字或数字范围以“约”、“近似”等描述时，该术语旨在包括在合理范围内的数字(包括所描述的数字)，例如在所述数量的+/-10％内或本技术领域中技术人员理解的其他值。举例来说，术语“约5nm”包括4.5nm至5.5nm的尺寸范围。
在过去的几十年中，集成电路(IC)装置已经快速发展。现有的IC芯片可包括许多主动装置(例如：晶体管)及被动装置(例如：电阻、电感以及电容)。在最近，负电容装置(negative capacitance device)可至少部分地经由制造场效晶体管(FET)来制造。更详细地说，可以使用包括铁电薄膜的FET装置的栅极结构来形成负电容装置。负电容装置可以提供较低的次临界摆幅(subthreshold swing)的优点。次临界摆幅表示关闭及导通晶体管电流的容易程度，是决定FET装置开关速度的一个因素。与现有FET装置相比，次临界摆幅允许FET装置具有更高的开关速度。负电容装置可用于具有非常短的通道长度的金属-氧化物-半导体场效晶体管(metal–oxide–semiconductor field-effect transistor,MOSFET)中，以用于超低功率计算(ultra-low power computing)。
然而，传统的负电容装置仍需要改进。举例来说，传统的负电容装置是通过在栅极堆叠中嵌入(embed)铁电材料所形成。随着微缩工艺所导致的越来越小的装置尺寸，这可能使嵌入有铁电材料的小栅极堆叠的制造变得益发困难。此外，由于传统负电容装置中铁电材料的尺寸较小，因此电容调谐窗口(tuning window)可能受到限制。
为了改进传统的负电容装置，本公开提供一种独特的负电容装置结构，其中铁电结构被形成为功能性晶体管外部的虚拟(dummy)或混合(hybrid)结构。接着，经由合适的电性选路(electrical routing)，将铁电结构电性耦接(electrically couple)至功能性晶体管的栅极堆叠。这样的设计使得铁电结构不受功能性晶体管的栅极堆叠内可用空间过小的限制。因此，铁电结构的制造更加容易。此外，铁电结构较大的尺寸提供了性能的提升以及附加的电容调谐能力。现在参照图1、2A-7A、2B-7B、8、9A-9C及10-11，以更加详细地讨论本公开的各种实施方式。
图1显示范例性的FinFET装置10(或称为FinFET装置结构10)的透视图。FinFET装置近年来已获得普及，且可用于制造负电容装置。因此，下文参照图1简要地讨论FinFET装置。
参照图1，FinFET装置结构10可包括具有不同导电性形式(type ofconductivity)的晶体管，例如n型FinFET装置结构(NMOS)15及p型FinFET装置结构(PMOS)25。FinFET装置结构10包括基板102。基板102可由硅或其他半导体材料制造。替代地或附加地，基板102可包括其他元素半导体材料，例如锗(germanium)。在一些实施例中，基板102由化合物半导体所制造，例如碳化硅(silicon carbide)、砷化镓(gallium arsenic)、砷化铟(indium arsenide)、或磷化铟(indium phosphide)。在一些实施例中，基板102由合金半导体所制造，例如硅锗(silicon germanium)、碳化硅锗(silicon germanium carbide)、磷砷化镓(gallium arsenic phosphide)、或磷化铟镓(allium indium phosphide)。在一些实施例中，基板102包括外延层(epitaxial layer)。举例来说，基板102可包括覆盖块材半导体(bulk semiconductor)的外延层。
FinFET装置结构10亦包括一或多个鳍片结构104(例如：硅鳍片)，鳍片结构104自基板102沿Z方向延伸，并被间隔物105沿Y方向所围绕。鳍片结构104在X方向上是延长的(elongated)，并且可选地包括锗(Ge)。鳍片结构104可通过使用合适的工艺来形成，例如微影(photolithography)及蚀刻工艺。在一些实施例中，使用干式蚀刻或等离子体工艺自基板102蚀刻鳍片结构104。一些其他实施例中，鳍片结构104可通过多重图案化(multiplepatterning)微影工艺来形成，例如双重图案化微影(double-patterning lithography,DPL)工艺。DPL是通过将图案分成两个交错(interleaved)的图案以在基板上建构图案的方法。DPL允许增加特征(例如：鳍片)的密度。鳍片结构104亦包括外延生长材料12，外延生长材料12可以(连同鳍片结构104的一些部分一起)作为FinFET装置结构10的源极/漏极。
隔离结构108(例如：浅沟槽隔离(shallow trench isolation,STI)结构)被形成以围绕鳍片结构104。在一些实施例中，鳍片结构104的下部被隔离结构108所围绕，而鳍片结构104的上部自隔离结构108突出，如图1所示。换句话说，鳍片结构104的一部分嵌入隔离结构108中。隔离结构108防止电子干扰(electrical interference)或串音(electricalcrosstalk)。
FinFET装置结构10亦包括栅极堆叠结构，栅极堆叠结构包括栅极电极110以及栅极电极110下方的栅极介电层(未图示)。栅极电极110可以包括多晶硅(polysilicon)或金属。金属包括氮化钽(tantalum nitride,TaN)、镍硅(nickel silicon,NiSi)、钴硅(cobaltsilicon,CoSi)、钼(molybdenum,Mo)、铜(copper,Cu)、钨(tungsten,W)、铝(aluminum,Al)、钴(cobalt,Co)、锆(zirconium,Zr)、铂(platinum,Pt)、或其他适用的材料。栅极电极110可被形成于栅极后制工艺(gate last process)(或是栅极替换工艺)。硬遮罩层112及硬遮罩层114可用于定义(define)栅极电极110。介电层115亦可形成于栅极电极110的侧壁上以及硬遮罩层112及114上。在至少一个实施例中，介电层115直接与栅极电极110接触。
栅极介电层(未图示)可包括介电材料，例如氧化硅、氮化硅、氮氧化硅、具有高介电常数(高k值)的介电材料、或其组合。高k值介电材料的范例包括氧化铪(hafniumoxide)、氧化锆(zirconium oxide)、氧化铝(aluminum oxide)、二氧化铪-氧化铝合金(hafnium dioxide-alumina alloy)、氧化铪硅(hafnium silicon oxide)、氮氧化铪硅(hafnium silicon oxynitride)、氧化铪钽(hafnium tantalum oxide)、氧化铪钛(hafnium titanium oxide)、氧化铪锆(hafnium zirconium oxide)等、或其组合。
在一些实施例中，栅极堆叠结构包括额外的薄层，例如界面层(interfaciallayer)、覆盖层(capping layer)、扩散(diffusion)/阻挡(barrier)层或其他适用的薄层。在一些实施例中，栅极堆叠结构形成于鳍片结构104的中央部分上方。在一些其他实施例中，复数栅极堆叠结构形成于鳍片结构104上方。在一些其他实施例中，栅极堆叠结构包括虚拟栅极堆叠，并在执行高热预算(high thermal budget)工艺之后，随后被金属栅极(metal gate,MG)所取代。
通过沉积工艺、微影工艺及蚀刻工艺形成栅极堆叠。沉积过程包括化学气相沉积(chemical vapor deposition,CVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、高密度等离子体CVD(high density plasmaCVD,HDPCVD)、金属有机CVD(metal organic CVD,MOCVD)、远程等离子体CVD(remoteplasma CVD,RPCVD)、等离子体增强型CVD(plasma enhanced CVD,PECVD)、电镀(plating)、其他合适的方法、及/或其组合。微影工艺包括光阻(photoresist)涂布(例如：旋涂)、软烤(soft baking)、光罩对准、曝光、曝后烤(post-exposure baking)、显影光阻、冲洗、干燥(例如：硬烤(hard baking))。蚀刻工艺包括干式蚀刻工艺或湿式蚀刻工艺。可选择地，微影工艺可通过其他适当的方法来实现或代替，例如无光罩微影(masklessphotolithography)、电子束写入(electron-beam writing)、以及离子束写入(ion-beamwriting)。
与传统的金属氧化物半导体场效晶体管(MOSFET)装置(亦称为平面晶体管(planar transistor)装置)相比，FinFET装置具有多项优势。这些优势可包括更好的芯片面积效率、改进的载子迁移率(carrier mobility)、以及与平面装置的制造工艺兼容的制造工艺。因此，可能期望能设计部分或整体IC芯片使用FinFET装置的集成电路(IC)芯片。举例来说，负电容装置可以以FinFET装置的形式实施。
图2A及图2B显示半导体装置200的不同的示意性局部截面侧视图。图2A的截面图是沿着图1的Y-Z平面所截取的，而图2B的截面图是沿着图1的X-Z平面所截取的。如此，图2A亦可被称为Y形切割，而图2B亦可称为X形切割。
参照图2A及图2B，半导体200包括基板210。基板210可为图1的基板102的一个实施例。举例来说，基板210可包括硅或另一种元素半导体，例如锗。基板210亦可包括化合物半导体，例如碳化硅、砷化镓、砷化铟及磷化铟。基板210亦可包括合金半导体，例如硅锗、碳化硅锗、磷砷化镓及磷化铟镓。在一个实施例中，基板210包括外延层。举例来说，基板210可包括覆盖块材半导体的外延层。
基板210亦可包括许多p型掺杂区域及/或n型掺杂区域，这些掺杂区域由诸如离子布植(ion implantation)及/或扩散的工艺所实现。那些掺杂区包括n井(n-well)、p井、轻掺杂区(light doped region,LDD)及各种通道掺杂轮廓，这些掺杂区被配置以形成各种集成电路(IC)装置，例如互补式金属氧化物半导体场效晶体管管(complimentary MOSFET,CMOSFET)、影像感应器(imaging sensor)及/或发光二极管(light emitting diode,LED)。
基板210亦可包括许多电性隔离区域，例如图1的隔离结构108。电性隔离区域在基板210中的各种装置区域(例如：掺杂区域)之间提供电性隔离。电性隔离区域可包括通过使用不同的工艺技术形成的不同结构。举例来说，电性隔离区域可包括浅沟槽隔离(shallowtrench isolation,STI)结构。STI结构的形成可包括在基板210中蚀刻沟槽，并在沟槽中填充(fill)一或多种绝缘材料，例如氧化硅、氮化硅、氧氮化硅、或其组合。被填充的沟槽可具有多层结构，例如以氮化硅填充沟槽的热氧化衬垫层(thermal oxide liner layer)。可执行诸如化学机械研磨(chemical mechanical polishing,CMP)的研磨或平坦化工艺，以将多余的绝缘材料研磨掉，并使隔离特征的顶部表面平坦化。
如图2A所示，半导体装置200还包括鳍片结构210A。鳍片结构210A可包括自基板210垂直向上(例如：在图1的Z方向上)突出的半导体材料。鳍片结构210A可为图1的鳍片结构104的实施例。
衬垫层230被形成于基板210的上部表面及鳍片结构210A的侧表面上。衬垫层230包括介电材料，举例来说，在一些实施例中，衬垫层230可包括氮化硅(SiN)。
如图2A所示，遮罩层240被形成于基板210上方、衬垫层230上方、以及鳍片结构210A上方。在一些实施例中，遮罩层240包括与衬垫层230不同的介电材料。举例来说，遮罩层240可包括氧化硅。在一些实施例中，衬垫层230包括具有不同材料的复数子层。可通过诸如原子层沉积(ALD)的沉积工艺沉积介电材料，然后进行图案化工艺以在所沉积的介电材料中形成沟槽250，以形成遮罩层240。沟槽250可被形成于鳍片结构210A附近。举例来说，沟槽250中的一个被形成于一个鳍片结构210A的“左侧”，而沟槽250中的另一个则被形成于一个鳍片结构210A的“右侧”。当然，遮罩层240的一些部分仍将沟槽250与鳍片结构210A分隔。
应注意的是，图2B的X切割是在半导体装置200的与其中一个沟槽250相对应的部分处所截取的。如此一来，遮罩层240及鳍片结构210A在图2B中并非直接可见的。
现在参照图3A及图3B，铁电层300被形成于沟槽250中。作为非限制性范例，铁电层300可包括氧化铪、氧化铪锆(hafnium zirconium oxide)、氧化铪铝(hafnium aluminumoxide)、钛酸铅锆(lead zirconium titanium oxide)、钛酸钡(barium titanium oxide)、或其组合。可通过沉积工艺形成铁电层300以填充沟槽250，然后进行诸如化学机械研磨(CMP)的平坦化工艺，以将铁电层300的上部表面与鳍片结构210A及遮罩层240的上部表面一同平坦化。由于铁电层300向上突出，与鳍片结构210A的向上突出相似，因此铁电层300亦可被称为铁电混合鳍片。在一些实施例中，每个混合鳍片/铁电层300的横向尺寸(例如：在X方向及/或Y方向上)，可基本上相等于每个鳍片结构210A的横向尺寸。在一些其他实施例中，每个混合鳍片/铁电层300的横向尺寸(例如：沿X方向及/或沿Y方向)，可以不同于每个鳍片结构210A的横向尺寸。
现在参照图4A及图4B，牺牲层310被形成于铁电层300、遮罩层240及鳍片结构210A的平坦化的上部表面上。牺牲层310可通过合适的沉积工艺来形成，并可包括诸如氧化硅的介电材料。之后，可在牺牲层310上方形成光阻材料330，例如通过使用旋涂工艺。接着，将光阻材料图案化(例如：经由诸如曝光、烘烤、显影等微影工艺)以形成图案化的光阻遮罩330(即图案化的光阻材料330)，光阻遮罩330包括开口350，如图4B所示。接着，光阻遮罩330被用于图案化牺牲层310。然后，图案化的牺牲层310被用于图案化下方的铁电层300及衬垫层230。换句话说，开口350被蚀刻，使得开口350垂直延伸穿过铁电层300及衬垫层230，如图4B所示。基板210的一些部分被开口350所曝露。
现在参照图5A及图5B，使用剥离(stripping)或灰化(ashing)工艺移除光阻层330。以介电层370填充开口350，举例来说，以合适的沉积工艺为之。作为非限制性范例，介电层370可包括氮化硅、氧化硅、碳化硅或其组合。介电层370在铁电层300的设置在介电层370的相对侧(例如：介电层370的左侧及右侧)的部分之间提供电性隔离。介电层370亦可被称为铁电混合鳍片阻挡器(blocker)。在一些实施例中，亦可在形成介电层370之前或之后移除牺牲层310。
现在参照图6A及图6B，可使用工艺420以形成虚拟栅极结构400。首先，若牺牲层310尚未被前面的工艺移除，则将其移除。经由工艺420中的一或多个蚀刻工艺部分掘入(recess)遮罩层240(以及设置于遮罩层240的侧壁上的衬垫层230的一些部分)，使得每个鳍结构210A的上部部分及每个铁电层300的上部部分被曝露。这可被称为鳍片掘入工艺。如图6A所示，鳍片结构210A的上部角及铁电层300的上部角亦可由于鳍片掘入工艺而变得有些圆弧。
接着，在遮罩层240的剩余部分的上部表面上形成介电层440。在一些实施例中，介电层440包括氧化物材料。然后，可在鳍片结构210A及铁电层300上形成虚拟栅极结构400。举例来说，每个虚拟栅极结构400可被形成为部分环绕鳍片结构210A及铁电层300，与图1的栅极电极110部分环绕鳍片结构104相似。每个虚拟栅极结构400在Y方向上如图6A所示以伸长的方式延伸，并在X方向上如图6B所示般彼此分隔。在一些实施例中，每个虚拟栅极结构400可包括虚拟栅极介电质及虚拟栅极电极。举例来说，虚拟栅极介电质可包括氧化硅，而虚拟栅极介电质可包括多晶硅。在一些实施例中，介电层440形成虚拟栅极结构的虚拟栅极介电质。
如图6A所示，通过形成于鳍片结构210A之间的介电组件450，可将原本连续的虚拟栅极结构400分割为单独的虚拟栅极结构400。同样如图6B所示，栅极间隔物470可被形成于虚拟栅极结构400的侧壁上。
接着可形成源极/漏极区域，举例来说，通过在虚拟栅极结构400外的鳍片结构210A的一些部分上外延生长外延层来形成。源极/漏极区域亦可被n型或p型掺杂剂所掺杂，这取决于所需的晶体管的类型(例如：NFET或PFET)。通道区域由鳍片结构210A的位在源极区域与漏极区域之间，并在虚拟栅极结构400下方(或被其环绕)的部分所形成。
层间介电质(ILD)490形成于铁电层300与虚拟栅极结构400上方以及栅极间隔物470周围，如图6B所示。如图6B所示，层间介电质490的上部表面被设置为高于虚拟栅极结构400，其中虚拟栅极结构400可为内部栅极。在一些实施例中，层间介电质490包括介电材料，例如低k值介电材料(介电常数小于二氧化硅的介电常数的介电材料)。作为非限制性范例，低k值介电材料可包括掺杂氟的二氧化硅(fluorine-doped silicon dioxide)、掺杂碳的二氧化硅(carbon-doped silicon dioxide)、多孔二氧化硅(porous silicon dioxide)、多孔掺杂碳的二氧化硅(porous carbon-doped silicon dioxide)、旋涂有机聚合物介电质(spin-on organic polymeric dielectric)、旋涂硅基聚合物介电质(spin-on siliconbased polymeric dielectric)、或其组合。替代地，层间介电质490可包括氧化硅或氮化硅或其组合。
现在参照图7A及图7B，执行栅极替换工艺500，以用高k值金属栅极(high-k metalgate,HKMG)结构替换虚拟栅极结构400，高k值金属栅极可包括界面层510、高k值栅极介电质530及金属栅极电极540。在一些实施例中，栅极替换工艺500可包括一或多个蚀刻工艺以蚀刻掉虚拟栅极结构400。虚拟栅极结构400的移除可在层间介电质490中形成开口，然后经由多个沉积工艺在开口中填充界面层510、高k值栅极介电质530及金属栅极电极540。
在一些实施例中，界面层510包括诸如氧化硅的氧化物材料，或另一合适的介电层。界面层510作为通道(例如：鳍片结构210A的栅极下方的部分)与高k值栅极介电质530之间的界面。如图7A所示，界面层510形成于鳍片结构210A的上部表面及侧表面上，但是并未形成于铁电层300上。这是因为与鳍片结构210A不同，铁电层300并不是半导体材料，因此不需要在半导体材料与高k值栅极介电质530之间形成界面。
高k值栅极介电质530形成于界面层510上，以及铁电层300的上部表面及侧表面上。在一些实施例中，高k值栅极介电质530可包括所具有的介电常数大于SiO2的介电常数的材料，SiO2的介电常数约为4。在一个实施例中，高k值栅极介电质530包括氧化铪(HfO2)，氧化铪的介电常数处于自约18到约40的范围中。在替代实施例中，高k值栅极介电质530可包括ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、或SrTiO。
金属栅极电极540形成于高k值栅极介电质530上，且可被实施为图1的栅极电极110的实施例。在一些实施例中，金属栅极电极540可包括功函数(work function)金属组件及填充金属组件。功函数金属组件被配置以调整其对应的晶体管的功函数，以达到所期望的临界电压Vt(threshold voltage)。在多种实施例中，功函数金属组件可包含：TiAl、TiAlN、TaCN、TiN、WN或W、或其组合。填充金属组件被配置以作为HKMG栅极结构的主要导电部分。在多种实施例中，填充金属组件可包含铝(Al)、钨(W)、铜(Cu)或其组合。金属栅极电极540经由高k值栅极介电质530电性耦接(electrically couple)至铁电层300。
在形成HKMG结构之后，亦可形成诸如导电结构或导电接点(contact)之类的导电结构，以提供通往(to)半导体装置200的各个组件的电性连接，例如通往铁电层300的电性连接。作为范例，如图7B所示，在每个铁电层300上形成导电结构550，导电结构550因此电性耦接到铁电层300。可经由导电结构550向晶体管的栅极施加电压。换句话说，导电结构550可作为负电容装置(例如：半导体装置200)的晶体管的栅极输入(input)。应理解的是，随后可使用多层互连结构(multi-layer interconnect structure)将导电结构550电性连接至其他微电子组件，例如经由多层互连结构的任何给定金属层中的一或多条金属线。
应理解的是，半导体装置200可包括具有不同导电性形式的不同晶体管。举例来说，图7A的左侧的鳍片结构210A、铁电层300及金属栅极电极540可形成n型晶体管200A，而图7A的右侧的鳍片结构210A、铁电层300及金属栅极电极540可形成p型晶体管200B。作为另一范例，在图7B中亦显示了n型晶体管200A的一部分，而另一个n型晶体管200C被设置为横向地相邻于n型晶体管200A。
图7C是根据一些实施例所示，半导体装置200的简化的局部俯视图。俯视图对应于由图1的X方向与Y方向所定义的水平面。为了简单起见，图7C中省略了一些薄层或组件。俯视图显示了金属栅极电极540。在金属栅极电极540下方的是界面层510及高k值栅极介电质530，但出于简化的原因，它们在图7C中被省略。相反地，尽管显示了铁电层300(例如：混合鳍片)及鳍片结构210A的外形或轮廓，但应理解的是，由于这些组件被金属栅极所覆盖，因此在俯视图中这些组件可能不是直接可见的。在任何案例中可以看出，每个铁电层300与鳍片结构210A可X方向上以伸长的方式延伸，且它们在Y方向上彼此分隔。在一些实施例中，每个铁电层300的尺寸可在X方向上及/或在Y方向上基本上相等于每个鳍片结构210A的尺寸。在一些其他实施例中，每个铁电层300的尺寸可以在X方向及/或Y方向上与每个鳍片结构210A的尺寸基本上不同。
再次参照图7A，金属栅极电极540部分环绕鳍片结构210A(包括晶体管的通道区域)以及铁电层300。再次提及，铁电层300于本文中被作为混合鳍片结构，但它们亦提供负电容调谐，因为如上所述它们被电性耦接至金属栅极电极540。
举例来说，图8显示了根据本公开实施例的电容模型。电容模型对应电性接地(Gnd)与栅极电压(Vg)节点之间的负电容晶体管的一部分。MOS晶体管的电容表示为电容CMOS，其由栅极氧化物电容COX及空乏区电容CS所组成。栅极氧化物电容COX可由界面层510及高k值栅极介电质530的材料组成及/或厚度所决定，而空乏区电容CS可由源极/漏极区域及通道区域的工艺条件及设计来决定。电容模型还包括电容CFE，代表铁电层300的电容。电容CFE可由铁电层300的材料组成及/或厚度决定。
为了最佳化负电容装置的性能，可能需要电容匹配(capacitance matching)。举例来说，可基于厚度或材料组成的因素来调整上面所讨论的各种电容。传统的负电容装置可形成位于晶体管的通道区域与晶体管的栅极电极之间的铁电层，因此，它的尺寸可能受到限制，特别是在装置持续微缩的情况下。相反地，本公开在晶体管的栅极介电质外部实现铁电层300。举例来说，铁电层300与通道区域(例如：图7A所示的鳍片结构210A的一部分)、界面层510及高k值栅极介电质530物理性地分隔。如此一来，铁电层300不受栅极介电质的尺寸的限制，或是通道区域与栅极电极540之间的空间量的限制。相反地，由于铁电层300被实现为鳍片结构210A(以及在其上形成的栅极介电层)之外的混合鳍片结构，因此与传统的负电容装置相比，所形成的铁电层300的尺寸可以大上许多。举例来说，铁电层300所具有的尺寸，可近似于鳍片结构210A的尺寸。
同时，铁电层300仍经由金属栅极电极540电性耦接至功能性晶体管，因为金属栅极电极同时围绕(并物理接触)鳍片结构210A及铁电层300，且高k值栅极介电质530形成于铁电层300及鳍片结构210A上。铁电层300亦电性耦接至导电结构550，导电结构550提供经由铁电层300通往功能性晶体管(例如：晶体管200A或200B)的栅极端的电性连接。因此，尽管本公开在结构上与传统的负电容装置有所不同(由于铁电层的外部实现)，但以上所讨论的电性选路方案仍允许其达到由传统的负电容装置所提供的优点。事实上，控制/配置铁电层300的尺寸及位置的弹性，可提供附加的负电容调谐自由度，这提供了比传统负电容装置更为泛用的负电容装置。如此一来，在栅极堆叠外部的铁电结构的实施，改进了电容匹配。
图9A至图9C显示了多种材料的剩磁极化(remanent polarization)对矫顽电场(coercive field)的图表。举例来说，图9A显示氧化铪的剩磁极化(Y轴)对矫顽电场(X轴)的曲线图。氧化铪材料与单片相(monolithic phase)有关。图9B是显示氧化锆的剩磁极化对矫顽电场的曲线图。氧化锆具有四方相(tetragonal phase)。图9C显示锆掺杂的氧化铪的剩磁极化对矫顽电场的曲线图。锆掺杂的氧化铪具有正交相(orthorhombic phase)。如图9C所示，锆掺杂的氧化铪的剩磁极化对矫顽电场的曲线图具有磁滞(hysteresis)，其形状类似于S曲线。这正是负电容铁电材料所期望的，且可通过电容调谐来实现。如上所述，外部的铁电结构为电容调谐提供了额外的弹性，且因此可促进磁滞的实现。
应理解的是，尽管已使用FinFET装置作为范例解释了本公开的各实施方式，但本公开亦可应用于非FinFET装置，例如平面装置。举例来说，图10显示了与图7A及图7B中的半导体装置200的FinFET晶体管相反的，被实施为平面晶体管的负电容装置700的截面侧视图。现在参照图10，负电容装置700包括基板710。基板710可包括硅材料或上述基板210的另一种合适的材料。源极区域705及漏极区域706被形成于基板710中，例如通过掺杂基板710的一些部分来形成。通道区域710A由设置于源极区域705与漏极区域706之间的基板710的一部分所形成。
界面层720被形成于通道区域710A上。在一些实施例中，界面层720包括诸如氧化硅的介电材料。高k值栅极介电层730被形成于界面层720上。高k值栅极介电层730可包括以上讨论的高k值栅极介电质530的任何材料。金属栅极电极层740被形成于高k值栅极介电层730上。金属栅极电极层740可包括上述讨论的金属栅极电极540的任何材料。应理解的是，界面层720、高k值栅极介电层730、以及金属栅极电极层740可一起被视作栅极结构或栅极堆叠。在一些实施例中，这种栅极堆叠的底部表面(例如：界面层720的底部表面)与隔离结构750的顶表面基本共面。
隔离结构750可被设置为在横向相邻于基板710。在一些实施例中，隔离结构750可与源极区域705及漏极区域706中的一者物理接触。在其他实施例中，可在隔离结构750与源极区域705之间施以附加组件，但为了简单起见，并未于本文中具体示出。隔离结构750可包括用于提供电性隔离的介电材料，例如氧化硅。
导电电极760被形成于隔离结构750上。可通过沉积并随后图案化导电材料以形成导电电极760。在一些实施例中，导电电极760可包括氮化钛材料。铁电层770被形成于导电电极760上。在一些实施例中，铁电材料可包括上述讨论的铁电层300的任何材料。另一个导电电极780被形成于铁电层770上。可通过沉积并随后图案化导电材料(例如：氮化硅材料)以形成导电电极780。在一些实施例中，铁电层770及导电电极780可一起被图案化，虽然这不是必需的。在一些实施例中，导电电极780在俯视图中的表面积，小于或等于在俯视图中的导电电极760的表面积。
如图10所示，铁电层770物理性地设置于功能性晶体管的外面或外部，其中功能性晶体管由源极区域705、漏极区域706、通道区域710A、界面层720、高k值栅极介电层730、以及金属栅极电极层740所形成。换句话说，铁电层770不是夹设于通道区域710A与金属栅极电极层740之间(这将带来很大的空间及尺寸上的限制)，而是于栅极堆叠的外部形成铁电层770。这允许铁电层770在尺寸、形状、及/或位置的配置上拥有更大的弹性。不过，铁电层770仍电性耦合到栅极堆叠。举例来说，电性连接机制790可用于将导电电极780(其电性连接至铁电层770)电性连接至金属栅极电极层740。在一些实施例中，电性连接机制790可包括多层互连结构的金属线。如此一来，尽管铁电层770在物理上实现于栅极堆叠的外部，但铁电层770仍电性耦接至栅极堆叠，且因此也允许负电容调谐。
于图10所示的实施例中，电性端子Vs耦接至源极区域705、电性端子Vd耦接至漏极区域706、而电性端子Vg耦接至导电电极760。电性端子Vs、电性端子Vd、及电性端子Vg可被实施为多层互连结构的导电接点或导电结构。因为导电电极760亦电性连接到铁电层770，且因为铁电层770电性连接到金属栅极电极层740，因此电性端子Vg电性连接到金属栅极电极层740，并提供通往功能性晶体管的栅极端的电性连接。电性端子Vs及电性端子Vd分别提供通往功能性晶体管的源极端及漏极端的电性连接。再次提及，在平面晶体管实施例中，在栅极堆叠外部的铁电层770的实施，提供了与前文参考FinFET实施例所讨论的那些优点相似的优点。
图11为制造半导体装置的方法900的流程图。方法900包括操作910，操作910在半导体鳍片结构上形成介电遮罩层。半导体鳍片结构自基板向上突出。
方法900包括操作920，操作920在介电遮罩层中蚀刻沟槽。
方法900包括操作930，操作930通过在沟槽中沉积铁电材料以在沟槽中形成混合鳍片结构。在一些实施例中，铁电材料包含氧化铪、氧化铪锆、氧化铪铝、钛酸铅锆、钛酸钡、或其组合。在一些实施例中，开口被形成以垂直延伸穿过混合鳍片结构。开口填充有电性绝缘材料。
方法900包括操作940，操作940至少在半导体鳍片结构上形成栅极介电层。
方法900包括操作950，操作950在半导体鳍片结构及混合鳍片结构上方形成栅极电极层。在一些实施例中，形成栅极电极层的操作包括形成同时环绕半导体鳍片结构及混合鳍片结构的金属栅极电极层。
在一些实施例中，沉积操作包括沉积以锆掺杂的氧化铪。
应理解的是，可以在方法900的操作910-950之前、之中、或之后执行附加工艺。举例来说，方法900可包括在半导体鳍片结构上但不在混合鳍片结构上形成界面介电层的操作。在一些实施例中，栅极介电层的形成包括在界面介电层上及混合鳍片结构上沉积高k值介电材料。作为另一范例，方法900包括将铁电材料与导电结构电性耦接的操作。导电结构可为互连结构的一部分，互连结构包括：分布于复数金属层中的金属线、将金属线连接到装置(例如：源极、漏极及栅极)的接点、以及用于垂直连接相邻金属层中的金属线的通孔。互连结构的形成可以包括镶嵌(damascene)工艺或其他合适的程序。金属组件(金属线、接点及通孔)可包括铜、铝、钨、金属合金、硅化物(silicide)、掺杂的多晶硅、其他合适的导电材料、或其组合。其他工艺可包括诸如测试及封装(packaging)工艺。出于简化的目的，并未于本文详细讨论这些附加操作。
总而言之，本公开形成了一种负电容电容器，其包括在栅极堆叠外部的铁电结构。在一些实施例中，铁电结构被实现为混合鳍片结构，该混合鳍片结构被设置为与栅极堆叠的半导体鳍片结构物理性地分隔，但电性耦接至栅极堆叠的半导体鳍片结构。举例来说，金属栅极电极层被形成环绕混合鳍片结构(例如：铁电结构)及半导体鳍片结构。因此，金属栅极电极层将铁电鳍片结构与半导体鳍片结构电性耦接在一起。导电结构可被形成于铁电结构上，以作为负电容装置的晶体管的栅极端子。在一些其他实施例中，铁电结构被实现为铁电层，该铁电层被设置为横向地相邻于平面晶体管的栅极堆叠，但仍物理性地与平面晶体管的栅极堆叠分隔。可在铁电层的上方及下方形成导电电极层。这些导电电极中的一个经由多层互连结构的连接机制(例如：金属线或通孔)电性耦接到平面晶体管的栅极堆叠，而这些导电电极中的另一个具有形成于其上的导电结构，以作为平面晶体管的栅极端子。
基于上述讨论可以看出，本公开提供了优于传统方法的优点。然而，应理解的是，其他实施例可提供额外的优点，且并非所有优点皆需于本文中公开，且并未有所有实施例皆需具备的特定优点。一个优点是在电容匹配方面更具弹性。如上所述，传统的负电容装置将铁电层实施为栅极堆叠内部的一薄层，例如实施为夹在通道与栅极电极之间的薄层。该方案对铁电层的尺寸及/或位置施加了严格的限制，这局限了负电容调谐的自由度。相反地，本文中铁电层的外部实施方式允许在配置铁电层的尺寸及/或位置方面拥有更大的弹性。因此，本公开提供了改进的负电容调谐弹性。此外，本文所讨论的外部铁电结构的较大尺寸可用于提供性能提升。其他优点包括与现行制造工艺的兼容性以及较低的实施成本。
上述的先进微影工艺、方法及材料可用于许多应用，包括鳍式场效晶体管(FinFET)。举例来说，鳍片可被图案化以在特征之间产生相对紧密之间隔，上述公开与这些间隔非常登对。此外，可根据上述公开来处理用于形成FinFET的鳍片之间隔物，亦称为心轴(mandrel)。
本公开实施例提供一种半导体装置。上述半导体装置包括一基板。第一鳍片结构被设置于基板上。第一鳍片结构包含一半导体材料。栅极介电层被设置于第一鳍片结构的上部及侧表面上。栅极电极层被形成于栅极介电层上。第二鳍片结构被设置于基板上。第二鳍片结构与第一鳍片结构物理性地分隔，并包含一铁电材料。第二鳍片结构电性耦接至栅极电极层。在一或多个实施例中，栅极介电层的一部分被设置于第二鳍片结构的上部及侧表面上。在一或多个实施例中，上述半导体装置还包括一界面层，被设置于栅极介电层与第一鳍片结构之间。在一或多个实施例中，栅极介电层直接与第二鳍片结构接触。在一或多个实施例中，上述半导体装置还包括一导电结构，设置于铁电材料的一部分上，并电性耦接至铁电材料的上述部分。在一或多个实施例中，栅极介电层被设置于第一鳍片结构的上部片段上，且一衬垫层被设置于第一鳍片结构的下部片段的侧表面上，但并未被设置于第二鳍片结构的侧表面上。在一或多个实施例中，铁电材料包含氧化铪、氧化铪锆、氧化铪铝、钛酸铅锆、钛酸钡、或其组合。
本公开实施例提供一种半导体装置。上述半导体装置包括形成于一基板中的通道区域。一栅极堆叠包括设置于通道区域上的栅极介电质，以及设置于栅极介电质上的栅极电极。一隔离结构被设置于栅极堆叠外部。一铁电层被设置于隔离结构上。铁电层电性耦接至栅极堆叠。在一或多个实施例中，上述半导体装置还包括一第一导电电极，设置于隔离结构与铁电层之间，以及一第二导电电极，设置于铁电层上，其中第二导电电极电性耦接至栅极堆叠。在一或多个实施例中，第二导电电极经由多层互连结构的组件，电性耦接至栅极电极。在一或多个实施例中，就俯视图而言，第二导电电极的面积小于或等于第一导电电极的面积。在一或多个实施例中，隔离结构的顶部表面与栅极堆叠的底部表面基本上共面。在一或多个实施例中，栅极堆叠还包括一界面层，界面层设置于栅极介电质与栅极电极之间。在一或多个实施例中，铁电层包含氧化铪、氧化铪锆、氧化铪铝、钛酸铅锆、钛酸钡、或其组合。
本公开提供一种制造半导体装置的方法。在半导体鳍片结构上形成一介电遮罩层。其中半导体鳍片结构自一基板向上突出。蚀刻介电遮罩层以形成一沟槽。通过在沟槽中沉积铁电材料以在沟槽中形成混合鳍片结构。至少在半导体鳍片结构上形成一栅极介电层。在半导体鳍片结构及混合鳍片结构上形成一栅极电极层。在一或多个实施例中，上述制造半导体装置的方法还包括在半导体鳍片结构上形成一界面介电层，但并未形成于混合鳍片上。在一或多个实施例中，栅极介电层的形成，包括在界面介电层及混合鳍片结构上沉积一高k值介电材料。在一或多个实施例中，栅极电极层的形成包括形成一金属栅极电极层，金属栅极电极层同时环绕半导体鳍片结构及混合鳍片结构。在一或多个实施例中，上述制造半导体装置的方法还包括将铁电材料与一导电结构电性耦接，其中铁电材料包含氧化铪、氧化铪锆、氧化铪铝、钛酸铅锆、钛酸钡、或其组合。在一或多个实施例中，上述制造半导体装置的方法还包括形成一开口，开口垂直延伸穿过混合鳍片结构，以及以一电性绝缘材料填充开口。
前述内文概述了许多实施例的特征，使本技术领域中技术人员可以从各个方面更佳地了解本公开。本技术领域中技术人员应可理解，且可轻易地以本公开为基础来设计或修改其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员亦应了解这些相等的结构并未脱离本公开的构思与范围。在不脱离本公开的构思与范围的前提下，可对本公开进行各种改变、置换及修改。

Claims (1)

1.一种半导体装置，包括：
一基板；
一第一鳍片结构，设置于上述基板上，其中上述第一鳍片结构包含一半导体材料；
一栅极介电层，设置于上述第一鳍片结构的上部及侧表面上；
一栅极电极层，形成于上述栅极介电层上；
一第二鳍片结构，设置于上述基板上，其中上述第二鳍片结构与上述第一鳍片结构物理性地分隔，并包含一铁电材料，且其中上述第二鳍片结构电性耦接至上述栅极电极层。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11349008B2 (en) * 2018-09-27 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance transistor having a multilayer ferroelectric structure or a ferroelectric layer with a gradient doping profile
US10861968B1 (en) 2019-05-30 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with negative capacitance structure and method for forming the same
KR20210033346A (ko) * 2019-09-18 2021-03-26 삼성전자주식회사 전자 소자 및 그 제조방법
US20220140147A1 (en) * 2020-11-04 2022-05-05 Samsung Electronics Co., Ltd. Thin film structure and semiconductor device comprising the same
US11749718B2 (en) * 2021-03-05 2023-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US11791383B2 (en) 2021-07-28 2023-10-17 Infineon Technologies Ag Semiconductor device having a ferroelectric gate stack

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030152813A1 (en) * 1992-10-23 2003-08-14 Symetrix Corporation Lanthanide series layered superlattice materials for integrated circuit appalications
JP4373647B2 (ja) * 2002-06-19 2009-11-25 独立行政法人産業技術総合研究所 強誘電体不揮発性記憶装置及びその駆動方法
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8362575B2 (en) 2009-09-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the shape of source/drain regions in FinFETs
US8610240B2 (en) 2009-10-16 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with multi recessed shallow trench isolation
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8036088B1 (en) 2010-06-14 2011-10-11 Oracle International Corporation Optical tape drive movable planarizer subsystem and method for minimizing damage to an optical pickup unit
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8367498B2 (en) 2010-10-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8723236B2 (en) 2011-10-13 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8815712B2 (en) 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8847293B2 (en) 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8860148B2 (en) * 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US8680576B2 (en) 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US8809139B2 (en) 2012-11-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-last FinFET and methods of forming same
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US8853025B2 (en) 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US8963258B2 (en) 2013-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company FinFET with bottom SiGe layer in source/drain
US8796666B1 (en) 2013-04-26 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with strain buffer layer and methods of forming the same
JP6299114B2 (ja) * 2013-08-29 2018-03-28 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US20160005749A1 (en) * 2014-07-01 2016-01-07 Qualcomm Incorporated Series ferroelectric negative capacitor for multiple time programmable (mtp) devices
US9449972B1 (en) * 2015-03-06 2016-09-20 Globalfoundries Inc. Ferroelectric FinFET
US9711533B2 (en) 2015-10-16 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9978868B2 (en) * 2015-11-16 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance field effect transistor with charged dielectric material
US10475707B2 (en) * 2016-02-02 2019-11-12 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10937783B2 (en) * 2016-11-29 2021-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10475738B2 (en) * 2016-12-27 2019-11-12 United Microelectronics Corp. Multi-threshold voltage semiconductor device
CN109148607B (zh) * 2017-06-27 2021-08-13 中芯国际集成电路制造(上海)有限公司 半导体装置、mos电容器及其制造方法
US11114565B2 (en) * 2017-09-29 2021-09-07 National Institute Of Advanced Industrial Science And Technology Semiconductor device
US10861973B2 (en) 2018-06-27 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance transistor with a diffusion blocking layer

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