CN110945655A

CN110945655A - Cell architecture with intrinsic decoupling capacitor

Info

Publication number: CN110945655A
Application number: CN201880049605.6A
Authority: CN
Inventors: H·钦塔拉帕里·雷迪; J·霍兰; S·穆罕默德
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2017-08-02
Filing date: 2018-07-09
Publication date: 2020-03-31
Anticipated expiration: 2038-07-09
Also published as: WO2019027627A1; US10163884B1; CN110945655B

Abstract

The IC includes an array of cells and a first set of end cap cells. The cell array includes a first group M coupled to a first voltage_xLayer power interconnect, first group M_xLayer interconnection, a second group M coupled to a second voltage source_xLayer power interconnect, and a second group M_xThe layers are interconnected. The first end cap unit comprises a first group M_x+1Layer interconnect and second group M_x+1The layers are interconnected. First group M_x+1The layer interconnection is coupled to the first group M_xLayer power interconnect and second set M_xThe layers are interconnected to provide a first set of decoupling capacitors. Second group M_x+1The layer interconnection is coupled to the second group M_xLayer power interconnect and first set M_xThe layers are interconnected to provide a second set of decoupling capacitors.

Description

Cell architecture with intrinsic decoupling capacitor

Cross Reference to Related Applications

The present application claims priority from U.S. patent application No. 15/667,576 entitled CELL ARCHITECTURE WITH interfacing manufacturing cap, filed on 8/2/2017, which is expressly incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to cell architectures and, more particularly, to cell architectures having one or more intrinsic decoupling capacitors.

Background

Standard cell devices are Integrated Circuits (ICs) that implement digital logic. Application specific ics (asics), such as system-on-a-chip (SoC) devices, may include thousands of standard cell devices. A typical IC includes a stack of layers formed in sequence. Each layer may be stacked or overlaid on previous layers and patterned to form shapes that define transistors (e.g., Field Effect Transistors (FETs) and/or fin field effect transistors (finfets)) and connect the transistors into a circuit.

Decoupling capacitors (also referred to as bypass capacitors) decouple one part of the circuit from another part of the circuit. Noise caused by a circuit element may be shunted through the decoupling capacitor, thereby reducing the effect of the noise on other circuit elements. There is a current need for improvements in the design of decoupling capacitors.

Disclosure of Invention

In an aspect of the disclosure, an IC includes at least a first IC portion and a second IC portion on a first side of the first IC portion. The IC includes a cell array in a first IC portion. The cell array includes: first group of metals x (M)_x) Layer power interconnectA first set of metal layer power interconnects coupled to a first voltage source and extending in a first direction across the cell array adjacent to an active region of a p-type Metal Oxide Semiconductor (MOS) (pMOS); first group M_xA layer interconnect extending in a first direction across the cell array adjacent to the pMOS active region; second group M_xA layer power interconnect coupled to a second voltage source smaller than the first voltage source and extending in a first direction across the cell array adjacent to the n-type MOS (NMOS) active area; and a second group M_xA layer interconnect extending in a first direction across the cell array adjacent to the nMOS active region. The IC further includes a first set of end cap units in the second IC portion. First group M_xLayer power interconnect, first group M_xLayer interconnection, second group M_xLayer power interconnect, and a second group M_xThe layer interconnect extends further across the first set of end cap units. The first set of end cap units includes a first set of metals x +1 (M) extending in a second direction orthogonal to the first direction_x+1) The layers are interconnected. First group M_x+1The layer interconnection is coupled to the first group M_xLayer power interconnect and second set M_xLayer interconnection to form a second group M_xA first voltage source is provided at the layer interconnect. The first set of end cap units further comprises a second set M extending in a second direction_x+1The layers are interconnected. Second group M_x+1The layer interconnection is coupled to the second group M_xLayer power interconnect and first set M_xLayers interconnected to form a first group M_xA second voltage source is provided at the layer interconnect. First group M_xLayer power interconnect and first set M_xThe layer interconnections serve as a first set of decoupling capacitors, and a second set M_xLayer power interconnect and second set M_xThe layer interconnects serve as a second set of decoupling capacitors.

In aspects of the disclosure, an IC and a method of operation of an IC are provided. The IC includes at least a first IC portion and a second IC portion on a first side of the first IC portion. In the first group M_xA first voltage is provided in the tier power interconnect. The cell array is in the first IC portion. The cell array includes a first group M_xA tier power interconnect coupled to a first voltage source and across the cell array in a first direction adjacent to the pMThe OS active region extends. The cell array further includes a first group M_xLayer interconnection, the first group M_xThe layer interconnect extends across the cell array adjacent to the pMOS active region in the first direction. In the second group M_xA second voltage is provided in the tier power interconnect. The cell array includes a second group M_xLayer power interconnection, the second group M_xThe tier power interconnect is coupled to a second voltage source that is smaller than the first voltage source and extends across the array of cells adjacent to the nMOS active region in the first direction. The cell array further includes a second group M_xLayer interconnection, the second group M_xA layer interconnect extends in a first direction across the cell array adjacent to the nMOS active region. The first set of end cap units is in the second IC portion. First group M_xLayer power interconnect, first group M_xLayer interconnection, second group M_xLayer power interconnect and second set M_xThe layer interconnect extends further across the first set of end cap units. In the second group M_xA first voltage is provided at the layer interconnect. The first set of end cap units comprises a first set M extending in a second direction orthogonal to the first direction_x+1The layers are interconnected. First group M_x+1The layer interconnection is coupled to the first group M_xLayer power interconnect and second set M_xLayer interconnection to form a second group M_xA first voltage source is provided at the layer interconnect. In the first group M_xA second voltage is provided at the layer interconnect. The first group of end cap units comprises a second group M extending in a second direction_x+1The layers are interconnected. Second group M_x+1The layer interconnection is coupled to the second group M_xLayer power interconnect and first set M_xLayers interconnected to form a first group M_xA second voltage source is provided at the layer interconnect. First group M_xLayer power interconnect and first set M_xThe layer interconnections serve as a first set of decoupling capacitors, and a second set M_xLayer power interconnect and second set M_xThe layer interconnects serve as a second set of decoupling capacitors.

Drawings

Fig. 1 is a first diagram illustrating a side view of standard cells and various layers within an IC.

Fig. 2 is a second diagram illustrating a side view of various layers within a standard cell and IC.

Fig. 3 is a plan view conceptually illustrating a cell architecture with an internal decoupling capacitor.

Fig. 4 is a first diagram conceptually illustrating a plan view of a macroblock including an array of cells and an end cap cell.

Fig. 5 is a second diagram illustrating a plan view of a macroblock including an array of cells and an end cap unit.

Fig. 6 is a diagram illustrating different metal layers in the macroblock of fig. 5.

Fig. 7 is a third diagram illustrating a plan view of a macro block including an array of cells and an end cap unit.

Fig. 8 is a diagram illustrating an operating method of an exemplary IC.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. The apparatus and methods are described in the following detailed description and may be illustrated by various blocks, modules, components, circuits, steps, procedures, algorithms, elements, and the like in the figures.

The decoupling capacitor decouples one portion of the circuit from another portion of the circuit. Noise caused by the circuit elements may be shunted through the decoupling capacitor, thereby reducing the effect of the noise on other circuit elements. Decoupling capacitors can occupy a significant amount of space on the IC. An exemplary (standard) cell architecture with intrinsic/built-in decoupling capacitors is provided below. An exemplary cell architecture with intrinsic/built-in decoupling capacitors can save space on an IC because the decoupling capacitors are intrinsic and built into standard cells that perform various logic functions, such as buffers, inverters, and gates, nand gates, or gates, nor gates, and other logic functions. In one configuration, the exemplary decoupling capacitor may be formed internally within a standard cell on a metal 0(M0) layer. Fig. 1 and 2 provide side views of various layers including the standard cell and M0 layer within the IC.

Fig. 1 is a first diagram 100 illustrating a side view of standard cells and various layers within an IC. As shown in fig. 1, the transistor has a gate 102, a source 104, and a drain 106. The source 104 and drain 106 may be formed from fins. A contact b (cb) layer interconnect 108 (also referred to as a Metal POLY (MP) layer interconnect) may contact the gate 102. A contact a (ca) layer interconnect 110 (also referred to as a Metal Diffusion (MD) layer) interconnect) may contact the source 104 or drain 106. Via 112 (which may be referred to as via d (vd) or via g (vg)) may contact CA layer interconnect 110. The vias VD, VG112 are formed by separate masks in at least a double patterning process. The M0 layer interconnect 114 contacts via VD/VG 112. Via V0116 may contact M0 level interconnect 114.

Fig. 2 illustrates a second diagram 200 of a side view of various layers within a standard cell and IC. As shown in fig. 2, the transistor has a gate 202, a source 204, and a drain 206. The source 204 and drain 206 may be formed from fins. The CB layer interconnect 208 may contact the gate 202. The CA layer interconnect 210 may contact the source 204 or the drain 206. The via 212VD/VG can contact the CB layer interconnect 208. The M0 layer interconnect 214 contacts via VD/VG 212. Via V0116 may contact M0 level interconnect 214.

As discussed above, an exemplary cell architecture with intrinsic decoupling capacitors is provided. Decoupling capacitors are built into standard cells that provide various logic functions. For example, standard cells providing logic functions (such as buffers, inverters, and gates, nand gates, or gates, nor gates, and other logic functions) may also include built-in decoupling capacitors. Such a built-in decoupling capacitor may be coupled to V through the following interconnects_ddAnd V_ss: through interconnects within the end cap unit, through interconnects in a complementary mos (cmos) interrupt unit that is largely free of pMOS/nMOS active regions (also referred to as Oxide Diffusion (OD) regions), and/or through interconnects that extend at/over the interrupt (OD interrupt) of the pMOS/nMOS active regions. Exemplary cell architectures with intrinsic/built-in decoupling capacitors are provided below with respect to fig. 3-7。

Fig. 3 is a plan view conceptually illustrating a cell architecture with an internal decoupling capacitor. Note that fig. 3 is a simplified diagram in order to illustrate an exemplary cell architecture with an intrinsic decoupling capacitor. Referring to FIG. 3, IC300 includes a first set M_xTier power interconnects 302, 306. M_x Layer power interconnect 302 is coupled to V_dd。M_x Layer power interconnect 306 is also coupled to V_ddThis is because M_x Layer power interconnect 306 through M_x+1Layer interconnect 340 is coupled to M_x Layer power interconnect 302, M_x+1Layer interconnect 340 through via V _x342 are connected to a first group M_xTier power interconnects 302, 306. Integrated circuit 300 also includes a second set M_xTier power interconnects 312, 316. M_x Layer power interconnect 312 is coupled to V_ss。M_xThe layer power interconnect 316 is also coupled to V_ssThis is because M_x Layer power interconnect 316 passes through M_x+1Layer interconnect 344 is coupled to M_x Layer power interconnect 312, M_x+1Layer interconnect 344 through via V _x346 being coupled to the second group M_xTier power interconnects 312, 316. First group M_xLayer power interconnects 302, 306 and a second set M_xThe tier power interconnects 312, 316 extend in a first direction. M_x Tier power interconnect 302 is located at top edge 350 of the standard cell in the pMOS region. M_xThe tier power interconnect 302 may be shared with standard cells that are adjacent above the top edge 350. M_xThe layer power interconnect 312 is located at the bottom edge 352 of the standard cell in the nMOS region. M_x Layer power interconnect 312 may be shared with standard cells that are adjacent below bottom edge 352.

IC300 also includes a first set M_xLayer interconnect 304 (in FIG. 3, in the first set M_xOnly one of the layer interconnects is illustrated) and a second group M_xLayer interconnect 314 (in FIG. 3, in the second group M_xOnly one of the layer interconnects is illustrated). First group M_xLayer power interconnects 302, 306 and a first set M_xThe layer interconnect 304 forms a first set of decoupling capacitors adjacent to the pMOS active area 370 (where the pMOS transistor is located). Second group M_xLayer powerInterconnects 312, 316 and a second set M_xThe layer interconnect 314 forms a second set of decoupling capacitors adjacent to the nMOS active region 372 (where the nMOS transistors are located). In fig. 3, four decoupling capacitors are illustrated, as are terminals 302/304, 306/304, 314/312 and 314/316. Assume in the first group M_xPresence of S in layer power interconnect_1pA M_xLayer power interconnect, in a first group M_xPresence of S in layer interconnection₁A M_xLayer interconnection, in a second group M_xPresence of S in layer power interconnect_2pA M_xLayer power interconnect, and a second group M_xPresence of S in layer interconnection₂A M_xLayer interconnection of | S_1p-S₁1 and S_2p-S₂I ≦ 1, then the first set of decoupling capacitors will include S_1p+S₁-1 decoupling capacitors, and the second set of decoupling capacitors will comprise S_2p+S₂-1 decoupling capacitor.

IC300 also includes a first set M_x+1Interconnect 320 (in FIG. 3, in the first group M_x+1Only one of the layer interconnects is illustrated) that extends in a second direction orthogonal to the first direction. First group M_x+1Layer interconnect 320 through via V _x330. 332 mix M_x Layer power interconnect 302 is coupled to M_xLayer interconnect 314 to at M_xProviding a voltage V at the layer interconnect 314_dd. IC300 also includes a second set M_x+1Layer interconnect 322 (in FIG. 3, in the second group M_x+1Only one of the layer interconnects is illustrated) that extends in the second direction. Second group M_x+1Layer interconnect 322 through via V _x334. 336 will M_x Tier power interconnect 312 coupled to M_xLayer interconnect 304 to be at M_xProviding a voltage V at the layer interconnect 304_ss. Accordingly, the first group M_x+1The layer interconnect 320 ties the terminals 314 of the decoupling capacitors 314/316, 314/312 to V_dd. Further, a second group M_x+1Layer interconnect 322 ties terminals 304 of decoupling capacitors 306/304, 302/304 to V_ss。

First and second groups M_x+1The layer interconnects 320, 322 may also pass through separatelyHole V _x+1390. 392 to V_dd、V_ss. First and second groups M_x+1The layer interconnects 320, 322 may be located outside of the standard cell array that provides the specific logic function. In one example, the first and second groups M_x+1The layer interconnects 320, 322 may be within an endcap cell, within a CMOS interrupt (standard) cell that is largely free of pMOS/nMOS active area (OD area), or within an area that includes a pMOS/nMOS active area interrupt (OD interrupt).

In one configuration, x is less than or equal to three. In another configuration, x is less than or equal to 2. In another configuration, x is less than or equal to one. In yet another configuration, x is equal to zero. Accordingly, in the case where x is equal to zero, M_xThe layer is M0 layer, M_x+1Layer is M1 layer, via V_xIs via V0, and via V_x+1Is via V1.

In the pMOS region of the IC300, a first group M_xLayer power interconnects 302, 306 and a first set M_xThe layer interconnects 304 are staggered (on every other adjacent track extending in the first direction). In the nMOS region of the IC300, a second group M_xLayer power interconnects 312, 316 and a second set M_xThe layer interconnects 314 are staggered (on every other adjacent track extending in the first direction). In one configuration, the first group M_xLayer power interconnects 302, 306 and a second set M_xBoth layer power interconnects 312, 316 include interconnects on standard cell edges 350 and 352, respectively. This configuration is shown in FIG. 3, as M_xThe layer power interconnects 302, 312 are on the standard cell edges 350, 352, respectively. However, in another configuration, the first group M_xLayer interconnect 304 and second set M_xLayer interconnect 314 includes interconnects on standard cell edges 350 and 352, respectively. Such a configuration is shown in fig. 5 to 7. As such, in the pMOS region of the IC300, M on the edge 350 of the standard cell is shown in FIG. 3_xThe layer interconnect may be bonded to V_ddOr may be bound to V as shown in fig. 5 to 7_ss. Further, as shown in FIG. 3, M on the standard cell edge 350 within the nMOS region of the IC300_xThe layer interconnection can be boundTo V_ssOr may be bound to V as shown in fig. 5 to 7_dd。

Fig. 4 is a first diagram conceptually illustrating a plan view of a macroblock that includes an array of cells 402 and

endcap units

404, 406. Referring to fig. 4, IC 400 includes a standard cell array 402 that performs various logic functions (e.g., buffers, inverters, and gates, nand gates, or gates, nor gates, and/or other logic functions) and also includes intrinsic/built-in decoupling capacitors. The standard cell array 402 includes built-in terminals for decoupling capacitors, as discussed above. Built-in terminals are within the standard cell itself (e.g., in M3, M2, M1, or M0), rather than being part of the interconnect formed during the global routing phase (e.g., at M0)_yIn the metal layer above, wherein the standard cell comprises M_yAnd lower layers). Adjacent to the standard cell array 402 is an endcap unit 408. Adjacent to the end cap units are

end cap units

404, 406, the

end cap units

404, 406 providing for binding the terminals of the decoupling capacitors to V_ddAnd V_ssThe bandage of (1).

Fig. 5 is a second diagram illustrating a plan view of a macroblock including an array of cells and an end cap unit. FIG. 6 is a diagram 600 illustrating different metal layers M0, M1, M2 in the macroblock of FIG. 5. Fig. 7 is a third diagram illustrating a plan view of a macro block including an array of cells and an end cap unit. Referring to fig. 5, 6, an IC 500 is illustrated that includes two

rows

502a, 502b of standard cell arrays. Adjacent to

standard cell arrays

502a, 502b are endcap cells 504a/506a, 504b/506 b. Each of the

standard cell arrays

502a, 502b includes a second set M of built-in decoupling capacitor terminals_xLayer interconnects 602, 606, 610, first set M_x

Tier power interconnect

622, 618, 614, first set M_xLayer interconnects 624, 620, 616, and a second set M_xTier power interconnects 604, 608, 612. End cap unit 504a includes a first set M_x+1Layer interconnect 520, first group M_x+1Layer interconnect 520 from first set M_xTier power interconnects 622, 618, 614 to a second set M_xThe tier interconnects 602, 606, 610 provide Power (PWR), and the endcap unit 504a includes a second set M_x+1Layer interconnect 522, the second group M_x+1Layer by layerFrom the second group M_x

Tier power interconnect

604, 608, 612 to first set M_xLayer interconnects 624, 620, 616 provide Ground (GND).

M_xLayer interconnect 540 connects first group M_xThe tier power interconnects 622, 618, 614 are bonded together and to the PWR. M_xLayer interconnect 542 connects second group M_xThe tier power interconnects 604, 608, 612 are bonded together and to ground.

As illustrated in fig. 5, 6, the IC 500 includes at least a first IC portion 502a and a second IC portion 504a, the second IC portion 504a being on a first side of the first IC portion 502. The IC 500 includes an array of cells 502a in a first IC portion 502 a. Each standard cell in the cell array 502a provides a logic function (such as a buffer, inverter, and gate, nand gate, or gate, nor gate, or other logic function). The cell array 502a includes a first group M_xTier power interconnects 622, 618, 614 coupled to a first voltage source (e.g., PWR, V)_dd) And extends across the cell array 502a in the first direction adjacent to the pMOS active region 598. The cell array 502a further includes a first group M_xLayer interconnects 624, 620, 616 that extend across the cell array 502a in the first direction adjacent to the pMOS active region 598. First group M_xTier power interconnects 622, 618, 614 and a first set M_xThe layer interconnects 624, 620, 616 are staggered on every other track. As such, if the first group M_xThe layer power interconnects 622, 618, 614 extend over odd-numbered tracks, the first group M_xThe layer interconnects 624, 620, 616 will extend over even numbered tracks. As shown in fig. 6, a first group M_xLayer interconnects 624, 620, 616 have interconnects (i.e., M) on the edge (dashed line) of the standard cell_xLayer interconnect 624). However, in another configuration, the first group M_xThe tier power interconnects 622, 618, 614 may have interconnects on the standard cell edges (dashed lines) (see, e.g., discussion with respect to fig. 3). The cell array 502a further includes a second group M_xTier power interconnects 604, 608, 612 coupled to a second voltage source (e.g., GND, V) that is less than the first voltage source_ss) And across the cell array in the first directionColumn 502a extends adjacent to nMOS active region 596. The cell array 502a further includes a second group M_xLayer interconnects 602, 606, 610 extending in a first direction across the cell array 502a, adjacent to the nMOS active region 596. Second group M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 are staggered on every other track. As such, if the second group M_xThe layer power interconnects 604, 608, 612 extend over odd-numbered tracks, and the second group M_xThe layer interconnects 602, 606, 610 will extend over even numbered tracks. As shown in fig. 6, a second group M_xThe layer interconnects 602, 606, 610 have interconnects (i.e., M) on the edges (dashed lines) of the standard cells_xLayer interconnect 602). However, in another configuration, the second group M_xThe tier power interconnects 604, 608, 612 may have interconnects on the edges (dashed lines) of the standard cells (see, e.g., discussion regarding fig. 3).

IC 500 also includes a first set of end cap units 504a in a second IC portion 504 a. First group M_x

Tier power interconnect

622, 618, 614, first set M_xLayer interconnects 624, 620, 616, second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 extend further across the first set of endcap units 504 a. First set of end cap units 504a comprises a first set M_x+1 A layer interconnect 520 extending in a second direction orthogonal to the first direction. First group M_x+1Layer interconnect 520 is coupled to a first set M_xTier power interconnects 622, 618, 614 and a second set M_xLayers interconnect 602, 606, 610 to form a second set M_xProviding a first voltage source (e.g., PWR, V) at the tier interconnects 602, 606, 610_dd). First set of endcap units 504a also includes a second set M extending in a second direction_x+1The layer interconnect 522. Second group M_x+1Layer interconnect 522 is coupled to a second set M_x

Tier power interconnect

604, 608, 612 and first set M_xLayer interconnect 624, 620, 616 to be in a first set M_xSecond voltage sources (e.g., GND, V) are provided at layer interconnects 624, 620, 616_ss). First group M_xTier power interconnects 622, 618, 614 and a first set M_xLayer by

layerConnections

624, 620, 616 serve as a first set of decoupling capacitors, and a second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 serve as a second set of decoupling capacitors. The first set of decoupling capacitors has terminals 622/624, 622/620, 618/620, 618/616, and 614/616. The second set of decoupling capacitors has terminals 602/604, 606/604, 606/608, 610/608, and 610/612.

As discussed above, the first group M_xTier power interconnects 622, 618, 614 and a first set M_xThe layer interconnects 624, 620, 616 are staggered in a second direction (on every other track extending in the first direction), and a second group M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 are staggered in the second direction (on every other track extending in the first direction).

As shown in fig. 6, a first group M_xThe tier power interconnects 622, 618, 614 include S_1pA M_xLayer power interconnect, first group M_xLayer interconnects 624, 620, 616 include S₁A M_xLayer interconnection, second group M_xThe

tier power interconnect

604, 608, 612 includes S_2pA M_xLayer power interconnection, and a second group M_xThe layer interconnects 602, 606, 610 comprise S₂A M_xLayer interconnection of | S_1p-S₁1 and S_2p-S₂Less than or equal to 1. First group M_xTier power interconnects 622, 618, 614 and a first set M_xLayer interconnects 624, 620, 616 form S_1p+S₁1 decoupling capacitors, and a second group M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 form S_2p+S₂-1 decoupling capacitor. In FIG. 6, S_1p、S₁、S_2pAnd S₂Is 3, and thus the first group M_xTier power interconnects 622, 618, 614 and a first set M_xLayer interconnects 624, 620, 616 form 5 decoupling capacitors, and a second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 form 5 decoupling capacitors.

First group M_x+1Layer interconnect 520 and second set M_x+1The layer interconnects 522 are staggered in a first direction (on every other track).

IC 500 also includes a third IC portion 506a on a second side of first IC portion 502a, where the second side is opposite the first side with respect to first IC portion 502 a. The IC 500 also includes a second set of end cap units 506a in a third IC portion 506 a. First group M_x

Tier power interconnect

622, 618, 614, first set M_xLayer interconnects 624, 620, 616, second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 extend further across the second set of end cap units 506 a. Second set of end cap units 506a includes a third set M extending in a second direction_x+1Layer interconnect 570. Third group M_x+1Layer interconnect 570 is coupled to first set M_xTier power interconnects 622, 618, 614 and a second set M_xLayers interconnect 602, 606, 610 to form a second set M_xProviding a first voltage source (e.g., PWR, V) at the tier interconnects 602, 606, 610_dd). Second set of end cap units 506a further includes a fourth set M extending in a second direction_x+1The layer interconnect 572. Fourth group M_x+1Layer interconnect 572 is coupled to a second set M_x

Tier power interconnect

604, 608, 612 and first set M_xLayer interconnect 624, 620, 616 to be in a first set M_xSecond voltage sources (e.g., GND, V) are provided at layer interconnects 624, 620, 616_ss)。

Similar to the first and second groups M_x+1Layer interconnection, third group M_x+1Layer interconnect 570 and fourth set M_x+1The layer interconnects 572 are staggered in a first direction (on every other track extending in a second direction).

The IC may further comprise a third set M_x+1Layer interconnect 540 and fourth group M_x+1Layer interconnect 542, third group M_x+1The layer interconnect 540 extends in a second direction and connects the first group M_xLayer power interconnects 622, 618, 614 are coupled together, and a fourth set M_x+1The layer interconnect 542 extends in a second direction and connects the second group M_xThe tier power interconnects 604, 608, 612 are coupled together.

In one configuration, the first group M_xThe tier power interconnects 622, 618, 614 comprise a first set M_x Layer power interconnect 622, first group M_xLayer interconnects 624, 620, 616 include a first set M_xLayer interconnect 624, first group M_xLayer interconnect 624 with a first set M_x Layer power interconnect 622 is adjacent; second group M_xThe tier power interconnects 604, 608, 612 include a first and second set M_x Layer power interconnect 604, and a second set M_xThe layer interconnects 602, 606, 610 comprise a first and a second set M_xLayer interconnect 602, first and second set M_xLayer interconnect 602 with first and second sets M_xThe tier power interconnect 604 is contiguous. In this configuration, the first group M_x+1Layer interconnect 520 is coupled to a first set M_x Layer power interconnect 622 and first and second sets M_xLayer interconnect 602 to be in first and second groups M_xProviding a first voltage source (e.g., PWR, V) at layer interconnect 602_dd). Further, in this configuration, the second group M_x+1The layer interconnect 522 is coupled to the first and second sets M_x Layer power interconnect 604 and first set M_xLayer interconnect 624 to be in a first group M_xProviding a second voltage source (e.g., GND, V) at layer interconnect 624_SS). First group M_x Layer power interconnect 622 and first set M_xLayer interconnect 624 serves as a first decoupling capacitor in a first set of decoupling capacitors, and a first second set M_x Layer power interconnect 604 and first and second sets M_xThe layer interconnect 602 serves as a second decoupling capacitor in the second set of decoupling capacitors.

Referring to fig. 7, the IC 700 may further include a set of CMOS interrupt cells 580 that are largely devoid of pMOS and nMOS active areas. The CMOS interrupt unit 580 may be completely free of a pMOS/nMOS active region or may be free of a pMOS/nMOS active region except at a side extending in the second direction (i.e., left/right sides in fig. 7, which are opposite to each other in the first direction). The CMOS interrupt unit 580 includes a third group M extending in the second direction_x+1Layer interconnects 582, 584 (in FIG. 7, only one M is shown_x+1Layer interconnect 582). Third group M_x+1Each M of layer interconnects 582, 584_x+1Layer interconnection connects first group M_xEach of the tier power interconnects 622, 618, 614 is coupled to the second set M_xLayers interconnect 602, 606, 610 to form a second set M_xAt layer interconnects 602, 606, 610 (as shown in FIG. 7, M_x+1Layer interconnect 582 provides coupling) provides a first voltage source (e.g., PWR, V)_dd) Or a second group M_xTier power interconnects 604, 608, 612 are coupled to a first set M_xLayer interconnect 624, 620, 616 to be in a first set M_xAt layer interconnects 624, 620, 616 (as shown in FIG. 7, M_x+1Layer interconnect 584 provides coupling) to provide a second voltage source (e.g., GND, V)_ss)。

As discussed above, in one configuration, x ≦ 3. In another configuration, x ≦ 2. In another configuration, x ≦ 1. In yet another configuration, x is 0.

Fig. 8 is a diagram illustrating an operating method of an exemplary IC. A method of operating an IC is provided. The IC includes at least a first IC portion and a second IC portion on a first side of the first IC portion.

At 802, at a first set M_xProviding a first voltage (e.g., PWR, V) in tier power interconnects 622, 618, 614_dd). The cell array 502a is in the first IC portion. The cell array 502a includes a first group M_xTier power interconnects 622, 618, 614 coupled to a first voltage source (e.g., PWR, V)_dd) And extends across the cell array 502a in the first direction adjacent to the pMOS active region 598. The cell array 502a further includes a first group M_xLayer interconnects 624, 620, 616 that extend across the cell array 502a in the first direction adjacent to the pMOS active region 598.

At 804, in the second group M_xThe second voltage (e.g., GND, V) is provided in the tier power interconnects 604, 608, 612_ss). The cell array 502a includes a second group M_xTier power interconnects 604, 608, 612 coupled to less than a first voltage source (e.g., PWR, V)_dd) Second voltage source (e.g., GND, V)_ss) And extends in the first direction across the cell array 502a adjacent to the nMOS active region 596. The cell array 502a further includes a second group M_xLayer interconnects 602, 606. 610 extending in a first direction across the cell array 502a adjacent to the nMOS active region 596. The first set of end cap units is in the second IC portion. First group M_x

Tier power interconnect

622, 618, 614, first set M_xLayer interconnects 624, 620, 616, second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 extend further across the first set of end cap units.

At 806, in the second group M_xProviding a first voltage (e.g., PWR, V) at the tier interconnects 602, 606, 610_dd). The first end cap unit comprises a first group M_x+1Layer interconnect 520, first group M_x+1The layer interconnect 520 extends in a second direction orthogonal to the first direction. First group M_x+1Layer interconnect 520 is coupled to a first set M_xTier power interconnects 622, 618, 614 and a second set M_xLayers interconnect 602, 606, 610 to form a second set M_xProviding a first voltage source (e.g., PWR, V) at a layer interconnect_dd)。

At 808, in the first set M_xA second voltage (e.g., GND, V) is provided at layer interconnects 624, 620, 616_ss). The first group of end cap units comprises a second group M extending in a second direction_x+1The layer interconnect 522. Second group M_x+1Layer interconnect 522 is coupled to a second set M_x

Tier power interconnect

604, 608, 612 and first set M_xLayer interconnect 624, 620, 616 to be in a first set M_xProviding a second voltage source (e.g., GND, V) at the layer interconnect_ss). First group M_xTier power interconnects 622, 618, 614 and a first set M_xLayer interconnects 624, 620, 616 function as a first set of decoupling capacitors, and a second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 serve as a second set of decoupling capacitors.

In one configuration, an IC is provided. The IC includes at least a first IC portion and a second IC portion on a first side of the first IC portion. IC includes a first group M_xProviding a first voltage (e.g., PWR, V) in tier power interconnects 622, 618, 614_dd) The component (2). The cell array 502a is in the first IC portion. The cell array 502a includesFirst group M_xTier power interconnects 622, 618, 614 coupled to a first voltage source (e.g., PWR, V)_dd) And extends across the cell array 502a in the first direction adjacent to the pMOS active region. The cell array 502a further includes a first group M_xLayer interconnects 624, 620, 616 that extend across the cell array 502a in the first direction adjacent to the pMOS active region 598. The IC further comprises a second group M for_xProviding a second voltage (e.g., GND, V) in the tier power interconnects 604, 608, 612_ss) The component (2). The cell array 502a includes a second group M_xTier power interconnects 604, 608, 612 coupled to less than a first voltage source (e.g., PWR, V)_dd) Second voltage source (e.g., GND, V)_ss) And extends in the first direction across the cell array 502a adjacent to the nMOS active region 596. The cell array 502a further includes a second group M_xLayer interconnects 602, 606, 610 extending in a first direction across the cell array 502a adjacent to the nMOS active region 596. The first set of end cap units is in the second IC portion. First group M_x

Tier power interconnect

622, 618, 614, first set M_xLayer interconnects 624, 620, 616, second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 extend further across the first set of end cap units. The IC further comprises a second group M for_xProviding a first voltage (e.g., PWR, V) at the tier interconnects 602, 606, 610_dd) The component (2). The first set of end cap units comprises a first set M extending in a second direction orthogonal to the first direction_x+1The layer interconnect 520. First group M_x+1Layer interconnect 520 is coupled to a first set M_xTier power interconnects 622, 618, 614 and a second set M_xLayers interconnect 602, 606, 610 to form a second set M_xProviding a first voltage source (e.g., PWR, V) at a layer interconnect_dd). The IC further comprises a first group M for_xA second voltage (e.g., GND, V) is provided at layer interconnects 624, 620, 616_ss) The component (2). The first group of end cap units comprises a second group M extending in a second direction_x+1The layer interconnect 522. Second group M_x+1Layer interconnect 522 is coupled to a second set M_x

Tier power interconnect

604, 608, 612 anda group of M_xLayer interconnect 624, 620, 616 to be in a first set M_xProviding a second voltage source (e.g., GND, V) at the layer interconnect_ss). First group M_xTier power interconnects 622, 618, 614 and a first set M_xLayer interconnects 624, 620, 616 function as a first set of decoupling capacitors, and a second set M_xTier power interconnects 604, 608, 612 and a second set M_xThe layer interconnects 602, 606, 610 serve as a second set of decoupling capacitors.

The decoupling capacitor decouples one portion of the circuit from another portion of the circuit. Noise caused by a circuit element may be shunted through the decoupling capacitor, thereby reducing the effect of the noise on other circuit elements. Decoupling capacitors can occupy a significant amount of space on the IC. The above provides an exemplary (standard) cell architecture with intrinsic/built-in decoupling capacitors. An exemplary cell architecture with intrinsic/built-in decoupling capacitors can save space on an IC because the decoupling capacitors are intrinsic and built into standard cells that perform various logic functions, such as buffers, inverters, and gates, nand gates, or gates, nor gates, and other logic functions. As discussed above, exemplary decoupling capacitors may be formed internally within standard cells on metal layers at or below M3, M2, or M1, and specifically within standard cells on the M0 layer. The built-in decoupling capacitor may be coupled to V by the following interconnects_ddAnd V_ss: interconnects within the end cap unit, through interconnects in the CMOS interrupt unit, and/or through interconnects extending at the interrupt (OD interrupt) of the pMOS/nMOS active area. Such an interconnection would be V_ddCoupling V from one terminal of decoupling capacitor adjacent to pMOS active region to another terminal adjacent to nMOS active region_ssFrom the decoupling capacitor terminal adjacent to the nMOS active region to the other terminal adjacent to the pMOS active region. Correspondingly, coupled to V_ddAnd V_ssAdjacent to the pMOS active region and the nMOS active region. Coupled to V adjacent to pMOS active region_ddAlso supplies power to the pMOS transistor in the pMOS active region and is coupled to V adjacent to the nMOS active region_ssThe terminal is alsoThe nMOS transistors in the nMOS active region are powered. The pMOS/nMOS transistors together provide CMOS logic functions.

It should be understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. It should be understood that the particular order or hierarchy of steps in the processes may be rearranged based on design preferences. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. The term "some" means one or more unless explicitly stated otherwise. Combinations such as "A, B or at least one of C", "A, B and at least one of C", and "A, B, C or any combination thereof" include any combination of A, B, and/or C, and may include multiples of a, multiples of B, or multiples of C. Specifically, combinations such as "at least one of A, B or C", "at least one of A, B and C", and "A, B, C or any combination thereof" may be a only, B only, C, A and B, A and C, B and C or a and B and C, where any such combination may include one member or more members of a, B or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. Any claim element should not be construed as a component plus function unless the element is explicitly recited using the phrase "component for … …".

Claims

1. An Integrated Circuit (IC) comprising at least a first IC portion and a second IC portion on a first side of the first IC portion, the IC comprising:

a cell array in the first IC portion, the cell array comprising: first group of metals x (M)_x) Layer power interconnect, the first group M_xA layer power interconnect coupled to a first voltage source and extending in a first direction across the cell array adjacent to a p-type Metal Oxide Semiconductor (MOS) (pMOS) active region; first group M_xA layer interconnect extending across the cell array adjacent to the pMOS active region in the first direction; second group M_xA layer power interconnect coupled to a second voltage source smaller than the first voltage source and extending across the cell array adjacent to an n-type MOS (nMOS) active area in the first direction; and a second group M_xA layer interconnect extending across the cell array adjacent to the nMOS active region in the first direction; and

a first set of end cap units in the second IC portion, wherein the first set M_xLayer power interconnect, the first set M_xLayer interconnect, the second group M_xLayer power interconnect, and the second group M_xA layer interconnect further extends across the first set of end cap units, the first set of end cap units comprising:

first group of metals x +1 (M)_x+1) A layer interconnection extending in a second direction orthogonal to the first direction, the first group M_x+1Layer interconnects are coupled to the first set M_xLayer power interconnect and the second set M_xLayer interconnection to form a layer in the second group M_xProviding the first voltage source at a layer interconnect; and

second group M_x+1Layer interconnections extending in the second direction, the second group M_x+1Layer interconnects are coupled to the second group M_xLayer power interconnect and the first set M_xLayer interconnection to form a layer in the first group M_xThe second voltage source is provided at a layer interconnect,

wherein the first group M_xLayer power interconnect and the first set M_xThe layer interconnections serve as a first set of decoupling capacitors, and the second set M_xLayer power interconnect and the second set M_xThe layer interconnects serve as a second set of decoupling capacitors.

2. The IC of claim 1, wherein the first set M_xLayer power interconnect and the first set M_xThe layer interconnections are staggered in the second direction, and the second group M_xLayer power interconnect and the second set M_xThe layer interconnects are staggered in the second direction.

3. The IC of claim 2, wherein the first set M_xThe layer power interconnection comprises S_1pA M_xLayer power interconnect, the first group M_xThe layer interconnect includes S₁A M_xLayer interconnection, the second group M_xThe layer power interconnection comprises S_2pA M_xLayer power interconnect, and the second group M_xThe layer interconnect includes S₂A M_xLayer interconnection of | S_1p-S₁Less than or equal to 1 and S_2p-S₂L.ltoreq.1, and wherein the first group M_xLayer power interconnect and the first set M_xLayer interconnect formation S_1p+S₁-1 decoupling capacitors, and said second set M_xLayer power interconnect and the second set M_xLayer interconnect formation S_2p+S₂-1 decoupling capacitor.

4. The IC of claim 1, wherein the first set M_x+1Layer interconnect and the second group M_x+1The layer interconnects are staggered in the first direction.

5. The IC of claim 1, wherein the IC includes a third IC portion on a second side of the first IC portion, the second side opposite the first side with respect to the first IC portion, the IC further comprising:

a second set of end cap units in the third IC portion, wherein the first set M_xLayer power interconnect, the first set M_xLayer interconnect, the second group M_xLayer power interconnect and the second set M_xA layer interconnect further extends across the second set of end cap units, the second set of end cap units comprising:

a third group M extending in the second direction_x+1Layer interconnection, the third group M_x+1Layer interconnects are coupled to the first set M_xLayer power interconnect and the second set M_xLayer interconnection to form a layer in the second group M_xProviding the first voltage source at a layer interconnect; and

a fourth group M extending in the second direction_x+1Layer interconnection, the fourth group M_x+1Layer interconnects are coupled to the second group M_xLayer power interconnect and the first set M_xLayer interconnection to form a layer in the first group M_xThe second voltage source is provided at a layer interconnect.

6. The IC of claim 1, wherein the third set M_x+1Layer interconnect and the fourth set M_x+1The layer interconnects are staggered in the first direction.

7. The IC of claim 1, wherein the IC further comprises:

third group M_x+1A layer interconnection extending in the second direction and connecting the first group M_xThe layer power interconnects are coupled together; and

fourth group M_x+1A layer interconnection extending in the second direction and connecting the second group M_xThe layer power interconnects are coupled together.

8. The IC of claim 1, wherein:

the first group M_xThe layer power interconnect includes a first group M_xLayer power interconnect, the first group M_xThe layer interconnection comprises a first group M_xFirst group M of adjacent layer power interconnects_xLayer interconnection, the second group M_xThe layer power interconnection comprises a first and a second group M_xLayer power interconnect, and the second group M_xThe layer interconnect includes a first and a second group M_xLayer interconnection, the first and second groups M_xLayer interconnection with the first and second groups M_xLayer power interconnect proximity;

the first group M_x+1Layer interconnects are coupled to the first group M_xLayer power interconnect and the first and second sets M_xLayer interconnection to form a first and second group M_xProviding the first voltage source at a layer interconnect;

the second group M_x+1Layer interconnects are coupled to the first and second groups M_xLayer power interconnect and the first set M_xLayer interconnection to form a first group M_xProviding the second voltage source at a layer interconnect; and

the first group M_xLayer power interconnect and the first set M_xThe layer interconnect serves as a first decoupling capacitor of the first set of decoupling capacitors, and the first and second sets M_xLayer power interconnect and the first and second sets M_xThe layer interconnect serves as a second decoupling capacitor of the second set of decoupling capacitors.

9. The IC of claim 1, wherein the IC further comprises a set of Complementary Mos (CMOS) interrupt cells that are predominantly free of pMOS and nMOS active regions, wherein the set of CMOS interrupt cells comprises a third set M_x+1Layer interconnection, the third group M_x+1Each M in the layer interconnection_x+1Layer interconnect connects the first group M_xOne M of the power interconnections_xA power interconnect coupled to the second set M_xLayer by layerTo be connected to in said second group M_xProviding the first voltage source at a layer interconnect, or the second set M_xA layer power interconnect coupled to the first set M_xLayer interconnection to form a layer in the first group M_xThe second voltage source is provided at a layer interconnect.

10. The IC of claim 1, wherein x ≦ 3.

11. The IC of claim 10, wherein x ≦ 2.

12. The IC of claim 11, wherein x is 0.

13. A method of operation of an Integrated Circuit (IC), the IC comprising at least a first IC portion and a second IC portion on a first side of the first IC portion, the method comprising:

in the first group of metals x (M)_x) Providing a first voltage in a layer power interconnect, an array of cells in the first IC portion, the array of cells including the first set M_xLayer power interconnect, the first group M_xA layer power interconnect is coupled to a first voltage source and extends in a first direction across the cell array adjacent to a p-type Metal Oxide Semiconductor (MOS) (pMOS) active region, the cell array further including a first set M_xLayer interconnection, the first group M_xA layer interconnect extends across the cell array adjacent to the PMOS active area in the first direction;

in the second group M_xProviding a second voltage at a layer power interconnect, the cell array including the second group M_xLayer power interconnect, the second group M_xA layer power interconnect is coupled to a second voltage source smaller than the first voltage source and extends across the cell array in the first direction adjacent to an n-type MOS (nMOS) active area, the cell array further including a second set M_xLayer interconnection, the second group M_xA layer interconnect across the cell array adjacent to the nMOS active region in the first directionA domain extension, a first set of end cap units in the second IC part, wherein the first set M_xLayer power interconnect, the first set M_xLayer interconnect, the second group M_xLayer power interconnect and the second set M_xA layer interconnect further extends across the first set of end cap units;

in the second group M_xProviding the first voltage at a layer interconnect, the first set of end cap units comprising a first set of metals x +1 (M) extending in a second direction orthogonal to the first direction_x+1) Layer interconnection, the first group M_x+1Layer interconnects are coupled to the first set M_xLayer power interconnect and the second set M_xLayer interconnection to form a layer in the second group M_xProviding the first voltage source at a layer interconnect; and

in the first group M_xThe second voltage is provided at the layer interconnection, the first set of end cap units comprises a second set M extending in the second direction_x+1Layer interconnection, the second group M_x+1Layer interconnects are coupled to the second group M_xLayer power interconnect and the first set M_xLayer interconnection to form a layer in the first group M_xProviding the second voltage source at a layer interconnect;

14. The method of claim 13, wherein the first set M_xLayer power interconnect and the first set M_xThe layer interconnections are staggered in the second direction, and the second group M_xLayer power interconnect and the second set M_xThe layer interconnects are staggered in the second direction.

15. The method of claim 14, wherein the first set M_xThe layer power interconnection comprises S_1pA M_xLayer power interconnect, structureThe first group M_xThe layer interconnect includes S₁A M_xLayer interconnection, the second group M_xThe layer power interconnection comprises S_2pA M_xLayer power interconnect, and the second group M_xThe layer interconnect includes S₂A M_xLayer interconnection of | S_1p-S₁Less than or equal to 1 and S_2p-S₂L.ltoreq.1, and wherein the first group M_xLayer power interconnect and the first set M_xLayer interconnect formation S_1p+S₁-1 decoupling capacitors, and said second set M_xLayer power interconnect and the second set M_xLayer interconnect formation S_2p+S₂-1 decoupling capacitor.

16. The method of claim 13, wherein the first set M_x+1Layer interconnect and the second group M_x+1The layer interconnects are staggered in the first direction.

17. The method of claim 13, wherein the IC includes a third IC portion on a second side of the first IC portion, the second side opposite the first side with respect to the first IC portion, the IC further comprising:

the second set of end cap units in the third IC portion, wherein the first set M_xLayer power interconnect, the first set M_xLayer interconnect, the second group M_xLayer power interconnect and the second set M_xA layer interconnect further extends across the second set of end cap units, the second set of end cap units comprising:

a fourth group M extending in the second direction_x+1Layer interconnection, the fourth group M_x+1Layer interconnects are coupled to the second group M_xLayer power exchangeAnd said first group M_xLayer interconnection to form a layer in the first group M_xThe second voltage source is provided at a layer interconnect.

18. The method of claim 13, wherein the third set M_x+1Layer interconnect and the fourth set M_x+1The layer interconnects are staggered in the first direction.

19. The method of claim 13, wherein the IC further comprises:

20. The method of claim 13, wherein:

the first group M_xThe layer power interconnect includes a first group M_xLayer power interconnect, the first group M_xThe layer interconnection comprises a first group M_xFirst group M of adjacent layer power interconnects_xLayer interconnection, the second group M_xThe layer power interconnection comprises a first and a second group M_xLayer power interconnect, and the second group M_xThe layer interconnection comprises a first group M and a second group M_xFirst and second groups M of adjacent layer power interconnects_xA layer interconnect;

the second group M_x+1Layer interconnects are coupled to the first and second groups M_xLayer power interconnect and the first set M_xLayer interconnection to form a first group M_xProviding the second voltage source at a layer interconnect(ii) a And

21. The method of claim 13, wherein x ≦ 3.

22. An Integrated Circuit (IC) comprising at least a first IC portion and a second IC portion on a first side of the first IC portion, the IC comprising:

for in a first group x (M)_x) A component in a layer power interconnect providing a first voltage, an array of cells in the first IC portion, the array of cells including the first group M_xLayer power interconnect, the first group M_xA layer power interconnect is coupled to a first voltage source and extends in a first direction across the cell array adjacent to a p-type Metal Oxide Semiconductor (MOS) (pMOS) active region, the cell array further including a first set M_xLayer interconnection, the first group M_xA layer interconnect extends across the cell array adjacent to the pMOS active region in the first direction,

for in the second group M_xMeans for providing a second voltage in a layer power interconnect, the cell array comprising the second group M_xLayer power interconnect, the second group M_xA layer power interconnect is coupled to a second voltage source smaller than the first voltage source and extends across the cell array in the first direction adjacent to an n-type MOS (nMOS) active area, the cell array further including a second set M_xLayer interconnection, the second group M_xA layer interconnect extends across the cell array adjacent to the nMOS active region in the first direction, a first set of end cap cells in the second IC portion, wherein the first set M_xLayer power interconnect, the first set M_xLayer by layerAnd said second group M_xLayer power interconnect and the second set M_xA layer interconnect further extends across the first set of end cap units;

for in the second group M_xA component providing the first voltage at a layer interconnect, the first set of end cap units comprising a first set of metals x +1 (M) extending in a second direction orthogonal to the first direction_x+1) Layer interconnection, the first group M_x+1Layer interconnects are coupled to the first set M_xLayer power interconnect and the second set M_xLayer interconnection to form a layer in the second group M_xProviding the first voltage source at a layer interconnect; and

for in the first group M_xA component providing the second voltage at a layer interconnect, the first set of end cap units comprising a second set M extending in the second direction_x+1Layer interconnection, the second group M_x+1Layer interconnects are coupled to the second group M_xLayer power interconnect and the first set M_xLayer interconnection to form a layer in the first group M_xThe second voltage source is provided at a layer interconnect,

23. The IC of claim 22, wherein the first set M_xLayer power interconnect and the first set M_xThe layer interconnections are staggered in the second direction, and the second group M_xLayer power interconnect and the second set M_xThe layer interconnects are staggered in the second direction.

24. The IC of claim 23, wherein the first set M_xThe layer power interconnection comprises S_1pA M_xLayer power interconnect, the first group M_xThe layer interconnect includes S₁A M_xLayer interconnection, the second group M_xThe layer power interconnection comprisesS_2pA M_xLayer power interconnect, and the second group M_xThe layer interconnect includes S₂A M_xLayer interconnection of | S_1p-S₁Less than or equal to 1 and S_2p-S₂L.ltoreq.1, and wherein the first group M_xLayer power interconnect and the first set M_xLayer interconnect formation S_1p+S₁-1 decoupling capacitors, and said second set M_xLayer power interconnect and the second set M_xLayer interconnect formation S_2p+S₂-1 decoupling capacitor.

25. The IC of claim 22, the first set M_x+1Layer interconnect and the second group M_x+1The layer interconnects are staggered in the first direction.

26. The IC of claim 22, wherein the IC includes a third IC portion on a second side of the first IC portion, the second side opposite the first side with respect to the first IC portion, the IC further comprising:

27. The IC of claim 22, wherein the third set M_x+1Layer interconnect and the fourth set M_x+1The layer interconnects are staggered in the first direction.

28. The IC of claim 22, wherein the IC further comprises:

29. The IC of claim 22, wherein:

the first group M_xLayer power interconnect and the first set M_xLayer interconnection used as the first groupA first decoupling capacitor of the coupling capacitors, and the first and second groups M_xLayer power interconnect and the first and second sets M_xThe layer interconnect serves as a second decoupling capacitor of the second set of decoupling capacitors.

30. The IC of claim 22, wherein x ≦ 3.