CN110943081A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110943081A
CN110943081A CN201910813498.6A CN201910813498A CN110943081A CN 110943081 A CN110943081 A CN 110943081A CN 201910813498 A CN201910813498 A CN 201910813498A CN 110943081 A CN110943081 A CN 110943081A
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fin
dummy
fins
region
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林志昌
吴伟豪
余佳霓
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供一种半导体装置，其包括第一装置鳍状物与第二装置鳍状物、第一虚置鳍状物与第二虚置鳍状物以及第三装置鳍状物与第四装置鳍状物。第一装置鳍状物与第二装置鳍状物其各自位于半导体装置的第一区中。第一区具有第一图案密度。第一虚置鳍状物位于第一区中。第一虚置鳍状物位于第一装置鳍状物与第二装置鳍状物之间。第一虚置鳍状物具有第一高度。第三装置鳍状物与第四装置鳍状物，各自位于半导体装置的第二区中。第二区具有第二图案密度，且第二图案密度大于第一图案密度。第二虚置鳍状物位于第二区中。第二虚置鳍状物位于第三装置鳍状物与第四装置鳍状物之间。第二虚置鳍状物具有第二高度，且第二高度大于第一高度。

Description

半导体装置
技术领域
本发明实施例涉及半导体装置，尤其涉及不同区域中不同高度的虚置鳍状物。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展，使每一代的集成电路均比前一代具有更小且更复杂的电路。在集成电路演进中，功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件或线路)缩小而增加。工艺尺寸缩小通常有利于增加产能与降低相关成本。
然而尺寸缩小亦增加处理与形成集成电路的复杂度。为实现这些进长，处理与形成集成电路的方法亦需类似发展。举例来说，可导入三维晶体管如鳍状场效晶体管以取代平面晶体管。可将鳍状场效晶体管想成一般的平面装置挤入栅极中。鳍状场效晶体管一般具有自基板向上延伸的薄鳍状物(或鳍状结构)。形成场效晶体管的通道于此垂直鳍状物中，并提供栅极于鳍状物的通道区上(比如包覆通道区)。栅极包覆鳍状物可增加通道区与栅极之间的接触面积，使栅极可自多侧控制通道。可由多种方式利此此概念。在一些应用中，鳍状场效晶体管可减少短通道效应、减少漏电流、并增加电流。换言之，鳍状场效晶体管比平面装置更快、更小、且更有效。
除了优点之外，现存的鳍状场效晶体管仍具有一些问题。举例来说，可形成介电结构如虚置鳍状物以调整整体鳍状物图案的密度、加强装置鳍状物的机械强度、及/或增进形成方法的能力。然而这些虚置鳍状物亦干扰源极/汲极外延层的横向成长。如此一来，源极/汲极外延层的尺寸较小、硅化物所用的表面积较小、及/或即将形成其上的导电接点的着陆工艺容许范围较小。在相邻晶体管之间的空间较大的集成电路区中(比如逻辑装置区中)，不想要出现上述现象。另一方面，若垂直地缩短虚置鳍状物以避免干扰源极/汲极外延层的横向成长，可能的缺点为当相邻晶体管之间的空间较小时(比如在记忆装置区中)，来自相邻晶体管的源极/汲极外延层可能合并在一起。这会在晶体管之间造成不想要的电性短路。
虽然现有的鳍状场效晶体管装置与其制作方法一般适用于其发展目的，但仍无法完全符合所有方面的需求。
发明内容
本发明一实施例提供的半导体装置，包括：第一装置鳍状物与第二装置鳍状物，各自位于半导体装置的第一区中，且第一区具有第一图案密度；第一虚置鳍状物，位于第一区中，其中第一虚置鳍状物位于第一装置鳍状物与第二装置鳍状物之间，且第一虚置鳍状物具有第一高度；第三装置鳍状物与第四装置鳍状物，各自位于半导体装置的第二区中，第二区具有第二图案密度，且第二图案密度大于第一图案密度；以及第二虚置鳍状物，位于第二区中，其中第二虚置鳍状物位于第三装置鳍状物与第四装置鳍状物之间，第二虚置鳍状物具有第二高度，且第二高度大于该第一高度。
本发明一实施例提供的半导体装置，包括：多个第一鳍状结构，其各自包含第一半导体材料；多个第一源极/汲极外延层，形成于第一鳍状结构上；多个第一介电结构，夹设于第一鳍状结构之间；多个第二鳍状结构，其各自包含第二半导体材料；多个第二源极/汲极外延层，形成于第二鳍状结构上；以及多个第二介电结构，夹设于第二鳍状结构之间，其中多个第一鳍状结构、第二鳍状结构、第一介电结构与第二介电结构垂直地向上凸起；相邻的第一鳍状结构之间的第一距离，实质上大于相邻的第二鳍状结构之间的第二距离；每一第一介电结构实质上比每一第二介电结构短但宽；第一源极/汲极外延层的部分位于第一介电结构的上表面上；以及第二源极/汲极外延层的部分物理接触第二介电结构。
本发明一实施例提供的半导体装置的形成方法，包括：形成多个第一装置鳍状物与多个第一虚置鳍状物于基板的第一区中，并形成多个第二装置鳍状物与多个第二虚置鳍状物于基板的第二区中，其中第一区的图案密度小于第二区的图案密度；形成多个栅极结构于第一装置鳍状物、第一虚置鳍状物、第二装置鳍状物与第二虚置鳍状物上；进行一或多道蚀刻工艺，使第一虚置鳍状物的高度减少程度大于第二虚置鳍状物的高度减少程度；以及在进行一或多道蚀刻工艺之后，外延成长多个第一外延层于第一装置鳍状物上，并外延成长多个第二外延层于第二装置鳍状物上，其中第一外延层的横向成长实质上不受高度减少的第一虚置鳍状物限制。
附图说明
图1是一例中，鳍状场效晶体管的透视图。
图2至图4、图7至图8与图10至图13是本发明实施例中，制作半导体装置的多种阶段的三为透视图。
图5、图6与图9是本发明实施例中，制作半导体装置的多种阶段的剖视图。
图14是本发明一实施例中，制作半导体装置的方法的流程图。
附图标记说明如下：
10 鳍状场效晶体管装置结构
12 外延成长材料
15 n型鳍状场效晶体管装置结构
25 p型鳍状场效晶体管装置结构
102 基板
104 鳍状结构
105、259 间隔物
108 隔离结构
110、270、271、272、273 栅极
112、114 硬掩模层
115 介电层
200 半导体装置
200A、200B 区域
210、211、212、220、221、222、223、224、225 装置鳍状物
230、231、232、233 硬掩模
240、241、242、250、251、252、253 虚置鳍状物
260、261、262、263 栅极结构
280、281、282、283、290、291、292、293 掩模层
295、300 蚀刻工艺
310、312、330 高度
316、318 距离
320 保护层
360 密封间隔物
400 外延成长工艺
410、411、412、430、431、432、433 外延层
440、445 点
500 层间介电层
530、531 切割图案
550、551、552、553、554、555 凹陷
570、571、572、573 金属栅极
600、601、602、603、620、621、622、623、624 层状物
900 方法
910、920、930、940 步骤
具体实施方式
可以理解的是，下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例用以简化本发明内容而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触的实施例，或两者之间隔有其他额外构件而非直接接触的实施例。此外，本发明的多个实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中，结构可直接接触另一结构，或可形成额外结构于结构及另一结构之间。此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于附图方向。
此外，当数值或数值范围的描述有“约”、“近似”或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围介于4.5nm至5.5nm之间。
半导体产业已进展至纳米技术工艺节点，以期达到更高装置密度、更高效能、与更低成本。为实施这些改良，半导体产业中的鳍状场效晶体管装置越来越普遍。
本发明实施例关于但不限于使芯片的选定区域中的虚置鳍状物凹陷，以同时最佳化效能并降低晶体管桥接/短路的顾虑。为了说明本发明的多种实施例，下述内容以鳍状场效晶体管的制作工艺为例。鳍状场效晶体管装置在半导体产业中越来越普遍。鳍状场效晶体管装置可为互补式金氧半装置，其包含p型金氧半的鳍状场效晶体管装置，与n型金氧半的鳍状场效晶体管装置。下述内容继续以一或多个鳍状场效晶体管为例，说明本发明的多种实施例。但应理解本发明实施例不限于鳍状场效晶体管装置，除非申请专利范围具体记载。
图1是一例中，鳍状场效晶体管装置结构10的透视图。鳍状场效晶体管装置结构10包含n型鳍状场效晶体管装置结构15与p型鳍状场效晶体管装置结构25。鳍状场效晶体管结构10包含基板102。基板102的组成可为硅或其他半导体材料。在其他或额外实施例中，基板102可包含其他半导体元素如锗。在一些实施例中，基板102的组成为半导体化合物如碳化硅、砷化镓、砷化铟、或磷化铟。在一些实施例中，基板102的组成为半导体合金如硅锗、碳化硅锗、磷砷化镓、或磷化镓铟。在一些实施例中，基板102包含外延层。举例来说，基板102可包含外延层于半导体基体上。
鳍状场效晶体管装置结构10亦包含在Y方向中，自基板102延伸的一或多个鳍状结构104，其于Y方向中被间隔物105围绕。鳍状结构104在X方向中伸长，且可视情况包含锗。鳍状结构104的形成方法可采用合适工艺如光刻与蚀刻工艺。在一些实施例中，采用干蚀刻或电浆工艺自基板102蚀刻出鳍状结构104。在一些其他实施例中，鳍状结构104的形成方法可为多重图案化光刻工艺，比如双重图案化光刻工艺。双重图案化光刻方法将图案分成两个交错图案，以建立基板上的图案。双重图案化光刻可增进结构如鳍状物的密度。鳍状结构104亦包含外延成长材料12，其可与鳍状结构104的部分一起作为鳍状场效晶体管装置结构10的源极/汲极。
形成隔离结构108如浅沟槽隔离结构，以围绕鳍状结构104。在一些实施例中，隔离结构108围绕鳍状结构104的下侧部分，而鳍状结构104的上侧部分自隔离结构108凸起，如图1所示。换言之，鳍状结构104的一部分埋置于隔离结构中。隔离结构108可避免电性干扰或串音。
鳍状场效晶体管装置结构10更包含栅极堆叠结构，其具有栅极110与位于栅极110下的栅极介电层(未图示)。栅极110可包含多晶硅或金属。金属包含氮化钽、镍硅化物、钴硅化物、钼、铜、钨、铝、钴、锆、铂、或其他可行材料。栅极110可由栅极后制工艺(或栅极置换工艺)所形成。硬掩模层112与114可用于定义栅极110。介电层115亦可形成于栅极110的侧壁上及硬掩模层112与114上。在至少一实施例中，介电层115直接接触栅极110。
栅极介电层(未图示)可包含介电材料如氧化硅、氮化硅、氮氧化硅、高介电常数的介电材料、或上述之组合。高介电常数的介电材料的例子包括氧化铪、氧化锆、氧化铝、氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、类似物、或上述之组合。
在一些实施例中，栅极堆叠结构包括额外的层状物如界面层、盖层、扩散阻障层、或其他可行的层状物。在一些实施例中，形成栅极堆叠结构于鳍状结构104的中心部分上。在一些实施例中，形成多栅极堆叠于鳍状结构104上。在一些其他实施例中，栅极堆叠结构包括虚置栅极堆叠，且在进行高热预算的工艺之后，再将虚置栅极堆叠置换成金属栅极。
栅极结构的形成方法为沉积工艺、光刻工艺、与蚀刻工艺。沉积工艺包括化学气相沉积、物理气相沉积、原子层沉积、高密度电浆化学气相沉积、有机金属化学气相沉积、远端电浆化学气相沉积、电浆辅助化学气相沉积、电镀、其他合适方法、及/或上述的组合。光刻工艺包含涂布光刻胶(如旋转涂布)、软烘烤、对准光罩、曝光、曝光后烘烤、显影光刻胶、冲洗、干燥(如硬烘烤)。蚀刻工艺包括干蚀刻工艺或湿蚀刻工艺。在其他实施例中，可由其他合适方法实施或置换光刻工艺，比如无光罩光刻、电子束写入、或离子束写入。
鳍状场效晶体管装置可比现有的金氧半场效晶体管装置(亦称作平面晶体管装置)提供更多优点。这些优点可包含较佳的芯片面积效率、改善的载子移动率、且制作工艺可与平面装置的制作工艺相容。因此需设计采用鳍状场效晶体管装置的集成电路，以用于整体或部分的集成电路。
然而现有的鳍状场效晶体管的制作方法仍需改善。举例来说，鳍状场效晶体管装置的制作方法可关于形成介电结构如虚置鳍状物(又称作混合鳍状物)，以调整整体鳍状物图案密度、加强装置鳍状物的机械强度、及/或增进形成方法的能力。然而集成电路芯片可包含具有不同功能、设计、及/或考量的不同种类装置，而介电结构未同时符合不同功能、设计、及/或考量。举例来说，集成电路芯片包含逻辑装置如核心装置与输入/输出装置，以及记忆装置如静态随机存取记忆装置。与静态随机存取记忆装置相较，逻极装置与输入/输出装置需要较大的源极/汲极外延层，以最佳化效能及/或处理输入/输出信号。然而当介电结构如虚置鳍状物形成于源极/汲极外延层之间时，其将限制源极/汲极外延层的横向外延成长。若发生上述限制，则源极/汲极外延层的尺寸缩小会负面地影响逻辑装置或输入/输出装置的效能。此外，源极/汲极外延层的横向成长受限会造成硅化物区缩小，并造成即将形成的导电接点所用的着陆区缩小。基于上述理由，减少介电结构的高度有益，比如横向外延成长逻辑装置或输入/输出装置所用的源极/汲极外延层时不受限制。
与逻辑装置或输入/输出装置相较，静态随机存取记忆装置可较小且更重视密度。换言之，在给定的单位面积中需具有大量的静态随机存取记忆晶体管。如此一来，虚置结构的存在一般不造成问题，因为静态随机存取记忆晶体管的源极/汲极外延层的横向成长，不像逻辑装置或输入/输出装置的源极/汲极外延层的横向成长一样重要。然而减少介电结构的高度可能造成桥接的问题。换言之，相邻晶体管的源极/汲极外延层可能成长至彼此接触，造成相邻晶体管之间的电性短路，其将负面地影响静态随机存取记忆装置的操作。值得注意的是，虚置结构凹陷或被移除所造成的桥接问题，可能存在于需要紧密布局的其他非静态随机存取记忆装置。举例来说，对一些逻辑装置而言，图案密度比效能(如速度或功率)优先。因此桥接亦为这些逻辑装置种类的考量点。
为克服上述问题，本发明实施例选择性地使芯片上的虚置结构凹陷(如选择性蚀刻)，比如使对应逻辑装置及/或输入/输出装置的区域中的虚置结构凹陷，而不使对应静态随机存取记忆装置(或需紧密布局的其他装置)的区域中的虚置结构凹陷。在此方式中，逻辑及/或输入/输出装置所用的介电结构高度减少较多，使源极/汲极的外延层具有最佳化的横向成长。静态随机存取记忆装置或其他高布局密度的装置所用的介电结构高度实质上不减少，其采用介电结构避免桥接。如此一来，可同时达到逻辑或输入/输出装置与静态随机存取记忆装置的优先目标。本发明的多种实施例将搭配图2至图14详述于下。图2至图4、图7与图8、及图10至13是半导体装置200于多种制作阶段的部分三维透视图。图5、图6与图9是半导体装置200于多种制作阶段的部分剖视图。图14是制作半导体装置200的方法的流程图。
如图2所示，半导体装置包括基板(未图示以简化附图)。在一些实施例中，基板可包含基体硅基板。在其他实施例中，基板可包括半导体元素(如结晶结构的硅或锗)、半导体化合物(如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)或上述的组合。在其他实施例中，基板可包含绝缘层上硅基板。绝缘层上硅基板的制作方法可采用注入氧隔离、芯片接合及/或其他合适方法。基板亦可包含多种隔离结构如浅沟槽隔离结构，以及浅沟槽隔离结构定义的主动区。
半导体装置200包括不同布局密度等级的多个区域。举例来说，图2显示半导体装置200的区域200A与区域200B。区域200A可对应逻辑装置及/或输入/输出装置，其布局密度较低，且相邻的晶体管构件之间的空间较宽(比如比区域200B中相邻的晶体管构件之间的空间宽)。相反地，区域200B可对应静态随机存取记忆装置及/或其他逻辑装置，其布局密度较高，比如高于区域200A中装置的布局密度。区域200B中相邻的晶体管构件之间的空间，可小于区域200A中相邻的晶体管构件之间的空间。区域200A可称作稀疏区域，而区域200B可称作密集区域。在一些实施例中，密集的区域200B的图案密度，至少为稀疏的区域200A的图案密度的两倍(比如前者的单位面积的晶体管数目至少为后者的两倍)。
区域200A与200B均包括主动区。在一些实施例中，主动区可垂直凸起高于非平面结构的隔离结构，比如图2中的装置鳍状物210与220至222。装置鳍状物210与220至222在X方向中水平延伸，并在Z方向中垂直向上凸起，且Z方向垂直于X方向及Y方向所定义的水平平面。装置鳍状物210与220至222可作为鳍状场效晶体管装置的主动区。装置鳍状物210与220至222不同于下述的虚置鳍状物。可由硬掩模230至233分别图案化装置鳍状物210与220至222。硬掩模230至233可包含介电材料。装置鳍状物210与220至222可包含半导体材料如硅或硅锗，或III-V族化合物如砷化镓、砷化镓铟、磷化铟、或类似物。
半导体装置200亦包括虚置鳍状物240、241、250、与251。这些虚置鳍状物240、241、250、与251亦可称作介电结构或混合鳍状物。虚置鳍状物240、241、250、与251于X方向中水平延伸，并于Z方向中垂直地向上凸起。虚置鳍状物240、241、250、与251可夹设于装置鳍状物210与220至222之间。如上所述，虚置鳍状物有助于调整整个鳍状物图案的密度、强化装置鳍状物的机械强度及/或增进形成方法的能力。在一些实施例中，虚置鳍状物240、241、250、与251可包含一或多种介电材料如高介电常数的介电材料，比如氮氧化硅、碳氮氧化硅、碳氧化硅、氧化铪、氧化锆、氧化铝或上述之组合。
此制作阶段的虚置鳍状物240、241、250与251以及装置鳍状物210与220至222在Z方向中具有实质上类似的鳍状物高度(差异在几个百分点内)，其中硬掩模230至233的高度算作装置鳍状物的鳍状物高度的一部分。虚置鳍状物240与241在Y方向中的横向尺寸，可各自大于虚置鳍状物250与251(或装置鳍状物210与220至222)的横向尺寸(至少宽两倍)。虚置鳍状物240、241、250与251的垂直及水平尺寸设置以最佳化其功能，比如调整装置鳍状物210与220至222的整体图案密度或加强装置鳍状物210与220至222的机械强度。
值得注意的是，装置鳍状物210以及虚置鳍状物240与241位于稀疏的区域200A中，而装置鳍状物220至222以及虚置鳍状物250与251位于密集的区域200B中。由于稀疏的区域200A与密集的区域200B之间的图案密度差异，本发明实施例对这些区域进行的制作工艺不同。举例来说，虚置鳍状物240与241的高度减少程度，可大于虚置鳍状物250与251的高度减少程度，且使虚置鳍状物高度减少的方法可为一或多道蚀刻工艺。
如图3所示，可形成间隔物259于装置鳍状物210与220至222及虚置鳍状物240、241、250与251的每一者上。间隔物259可包含介电材料如低介电常数的介电材料、氧化硅、氮化硅或类似物。在一些实施例中，间隔物259可视作虚置鳍状物240、241、250与251的一部分。
接着可形成栅极结构260至263于装置鳍状物210与220至222以及虚置鳍状物240、241、250与251上。栅极结构260至263各自在Y方向中水平延伸，并在Z方向中垂直向上延伸。栅极结构260至263各自部分地包覆装置鳍状物210与220至222以及虚置鳍状物240、241、250与251的上表面与侧表面。直接位于栅极结构260至263下的装置鳍状物210与220至222的部分，可作为晶体管的通道区。栅极结构260至263可分别包含栅极270至273。在一些实施例中，栅极270至273可为虚置栅极，比如虚置的多晶硅电极。在后续的栅极置换工艺中，可将这些虚置的栅极270至273置换成金属栅极。栅极结构260至263亦包含掩模层280至283与290至293于栅极270至273上。掩模层280至283与290至293可用于图案化材料层(如多晶硅层)，以定义栅极270至273。可以理解的是，栅极结构260至263亦包含栅极介电层，比如高介电常数(比如介电常数大于约4)的栅极介电层。栅极介电层可位于栅极270至273下，且未图示于此以简化附图。
在形成栅极结构260至263之后，可进行一或多道蚀刻工艺295，以部分地移除装置鳍状物210与220至222上的硬掩模230至233，直到露出装置鳍状物210与220至222。如图3所示，一或多道蚀刻工艺295亦可移除虚置鳍状物240、241、250与251的上侧部分以及间隔物259的上侧部分。
图4分开图示稀疏的区域200A与密集的区域200B，以各自显示区域200A与200B中的额外构件。举例来说，稀疏的区域200A还包括装置鳍状物211与212及虚置鳍状物242，而密集的区域200B还包括装置鳍状物223至225及虚置鳍状物252与253。进行蚀刻工艺300以选择性地蚀刻半导体装置200，使稀疏的区域200A的虚置鳍状物240至242凹陷，但不使密集的区域200B的虚置鳍状物250至253凹陷。举例来说，可形成保护层如光刻胶掩模于密集的区域200B上，并选择性地形成于稀疏的区域200A之部分上而不形成于虚置鳍状物240至242上。因此在蚀刻工艺300时，保护层可保护密集的区域200B中的构件与稀疏的区域200A中的装置鳍状物210至212，而稀疏的区域200A中的虚置鳍状物240至242暴露至蚀刻。
由图4可知，部分地移除虚置鳍状物240至242可打开装置鳍状物210至212之间的空间，因此自装置鳍状物210至212横向外延成长的后续步骤不再受到限制。与此同时，由于蚀刻工艺300不影响虚置鳍状物250至253，虚置鳍状物250至253仍可作为隔离结构，以避免密集区域中相邻的晶体管之间产生不想要的桥接。
图5与图6是稀疏的区域200A与密集的区域200B的部分剖视图，以进一步说明本发明实施例中，选择性地使稀疏的区域200A中的虚置鳍状物240至242凹陷的步骤。此剖视图可沿着图4中的Z方向与Y方向所定义的平面。
图5所示的制作阶段可对应图3所示的制作阶段。虽然蚀刻工艺295部分地蚀刻稀疏的区域200A中的虚置鳍状物240与241以及密集的区域200B中的虚置鳍状物250与251，以打开装置鳍状物210、211与220至222(比如移除形成其上的硬掩模层)，但未选择性地蚀刻稀疏的区域200A中的虚置鳍状物204与241以明显减少其高度。换言之，此制作阶段未进行上述的蚀刻工艺300。
此制作阶段的虚置鳍状物240与241可具有高度310(在Z方向中量测)。在一些实施例中，高度310可介于约25nm至约105nm之间。装置鳍状物210与211可具有高度312，且高度312与高度310的差异不大。举例来说，高度312与高度310的差异为百分之几纳米，且高度312可大于或小于高度310。在一些实施例中，高度312介于约30nm至约100nm之间。可设置高度310与312，使虚置鳍状物可提供足够的机械强度，而装置鳍状物可具有足够高度以利后续外延成长源极/汲极的外延层。
图5亦清楚显示稀疏的区域200A与密集的区域200B之间的图案密度差异。举例来说，稀疏的区域200A中鳍状物与鳍状物之间具有距离316(在Y方向中量测)，而密集的区域200B中鳍状物与鳍状物之间具有距离318(亦在Y方向中量测)。区域200A与200B中鳍状物与鳍状物之间的距离，系装置鳍状物的中心至最靠近的相邻装置鳍状物的中心的距离，而相邻的装置鳍状物之间具有至少一虚置鳍状物。举例来说，装置鳍状物210与211之间具有距离316，而装置鳍状物221与222之间具有距离318。如图5所示，距离316实质上大于距离318。举例来说，距离316至少为距离318的两倍。在一些实施例中，距离316比距离318大至少40nm。由于稀疏的区域200A中的空间较宽(参考距离316与318之间的差异)，即使减少虚置鳍状物240与241的高度310，成长于装置鳍状物210与211上的外延层仍不易彼此桥接。与此相较，若密集的区域200B中的虚置鳍状物250与251的高度减少，则成长于装置鳍状物221与222上的外延层可能彼此桥接。如此一来，本发明实施例实质上减少稀疏的区域200A中的虚置鳍状物240与241的高度，但不减少密集的区域200B中的虚置鳍状物高度。
如图6所示，进行一或多道蚀刻工艺300(如搭配图4说明的上述内容)。如上所述，可形成保护层320覆盖密集的区域200B中的构件以及稀疏的区域200A中的装置鳍状物210与211。在一些实施例中，保护层320可为光刻胶层，但其他实施例的保护层320可为另一硬掩模层。蚀刻工艺300可将虚置鳍状物240至241的高度，由高度310降低至高度330。
在一些实施例中，高度330比蚀刻前的虚置鳍状物240与241的高度310低至少约20nm。举例来说，高度330可介于约5nm至约70nm之间。在一些实施例中，高度330与高度310的比例可介于约1:20至1:1.1之间。这些范围设置可让高度330够小，而不会限制后续形成的源极/汲极层的横向成长。与此同时，高度330不会太小，使虚置鳍状物240与241仍符合调整整体鳍状物图案密度、加强装置鳍状物的机械强度与类似功效的初始目的。
如图7所示的三维透视图，密封间隔物360可形成于稀疏的区域200A与密集的区域200B中的栅极270至273的侧表面上。密封间隔物360可包含介电材料组成，且其形成方法可为沉积介电材料之后进行一或多道蚀刻工艺。值得注意的是，在形成密封间隔物360之前，不需进行上述的蚀刻工艺300。在一些实施例中，可先形成密封间隔物360，接着可进行蚀刻工艺300以选择性地使稀疏的区域200A中的虚置鳍状物240至242凹陷。
如图8的三维透视图与图9的剖视图所示，进行外延成长工艺400以成长稀疏的区域200A与密集的区域200B所用的源极/汲极外延层。举例来说，外延层410至412可形成于稀疏的区域200A中，而外延层430至433可形成于密集的区域200B中。外延层410至412与外延层430至433可包含半导体材料如硅、磷化硅、或硅锗，或III-V族化合物如砷化镓、砷化镓铟、磷化铟或类似物。外延层410至412与430至433可作为晶体管的源极/汲极区，并可称作源极/汲极的外延层。在一些实施例中，源极/汲极的外延层410至412的形成方法，可为使装置鳍状物210至212的部分凹陷，之后成长源极/汲极的外延层410至412于凹陷的装置鳍状物上。可类似地形成源极/汲极的外延层430至433于装置鳍状物220至225上。应理解的是，使虚置鳍状物240与241的高度减少的制作阶段，可不同于上述制作阶段，只要在进行外延成长工艺400之前进行即可。
如图8与9所示，由于部分地移除稀疏的区域200A中的虚置鳍状物240至242(并减少其高度)，因此实质上不阻碍源极/汲极的外延层410至412的横向成长。举例来说，源极/汲极的外延层410至412可向外横向成长，且不止于虚置鳍状物240至242的侧壁。相反地，虚置鳍状物240与241的上表面仍可低于源极/汲极的外延层410与411最外侧的横向凸出的点440。在一些实施例中，虚置鳍状物240与241的上表面甚至可低于源极/汲极的外延层410与411最底侧的点445。可以理解的是，点440与445不必为单点，亦可为区域或多个点。
如上所述，稀疏的区域200A中装置的目标包括外延应力所需的大尺寸外延层、降低硅化物电阻所需的大侧壁表面积及/或即将形成其上的导电接点所需的大着陆面积及/或工艺容许范围。由于源极/汲极的外延层410至412可具有不受限制的横向成长，进而形成大尺寸的源极/汲极外延层，以符合稀疏的区域200A中装置的目的，因此本发明实施例可最佳化稀疏的区域200A中的装置效能。
与此同时，由于本发明实施例保护区域200B免于蚀刻工艺300，因此实质上不减少区域200B中虚置鳍状物250至253的高度。在一些实施例中，源极/汲极的外延层430至433可横向成长至物理接触虚置鳍状物250至253。值得注意的是，间隔物259可视作虚置鳍状物250至253的一部分。因此虚置鳍状物250至253的未减少的高度，指的是其可适当地帮助源极/汲极的外延层430至433彼此隔离。这可帮助密集的区域200B中的装置达到其目标之一，比如避免晶体管之间产生不想要的电性桥接并保持高图案密度。在此方式中，本发明实施例可同时达到稀疏的区域200A中的装置与密集的区域200B中的装置的不同目标。值得注意的是，来自相邻晶体管的外延层可合并在一起，以形成密集区域中一些源极/汲极的外延层(如外延层430与432)。然而上述结构依据装置设计且刻意，并非不想要的结构。
如图10所示，将形成于栅极270至273上的掩模层280至283与掩模层290至293移除。之后形成层间介电层500。层间介电层500亦可称作第0层的层间介电层。层间介电层500可包含介电材料如低介电常数的介电材料，即介电常数小于氧化硅的介电常数的介电材料。在非局限性的例子中，低介电常数的介电材料可包括掺杂氟的氧化硅、掺杂碳的氧化硅、多孔氧化硅、多孔的掺杂碳的氧化硅、旋转涂布的有机聚合物介电层、旋转涂布的硅为主的聚合物介电层或上述的组合。在其他实施例中，层间介电层500可包含氧化硅、氮化硅或上述的组合。此外，层间介电层500可提供半导体装置200的多种构件之间的电性隔离。
如图11所示，形成切割图案530与531。切割图案530与531可包含在图案化工艺时适于作为掩模的介电材料。举例来说，切割图案530形成于虚置鳍状物241上与栅极270及271的部分上，而切割图案531形成于虚置鳍状物250上与栅极270及271的部分上。接着可进行一或多道蚀刻工艺，以蚀刻移除切割图案530与531未保护的虚置鳍状物240与251的部分以及装置鳍状物210与220至222。部分移除虚置鳍状物240与251及装置鳍状物210与220至222可形成凹陷，如图11所示的凹陷550至555。这些凹陷将填充后续形成的材料(如金属栅极材料)，以建立半导体装置200的多种构件之间的电性连接。
值得注意的是，图11的透视图的Y-Z平面是栅极270的剖视图，而非栅极270之外的剖视图(如图10所示)。如此一来，图11未显示源极/汲极的外延层。
如图12所示，进行栅极置换工艺。具体而言，移除栅极270至273，且移除方法可采用一或多道蚀刻工艺。之后分别置换成金属栅极570至573。金属栅极570至573可各自包含一或多个功函数金属层以调整晶体管的功函数，以及一或多个填充金属层以作为金属栅极的主要导电部分。值得注意的是，金属栅极570至573不只置换虚置栅极，亦填入图11所示的凹陷550至555。
如图12所示，形成层状物600至603与620至623，以提供半导体装置200的多种构件所需的电性隔离。在此考量下，层状物600至603形成于金属栅极570至573上，而层状物620至623形成于源极/汲极的外延层410至412与源极/汲极的外延层430至433上。与图11类似，图12的透视图中的Y-Z平面为金属栅极570的剖面，因此图12未显示源极/汲极的外延层。应理解的是，金属栅极570至573以及源极/汲极的外延层410至412与430至433所用的导电接点，其形成方法可为蚀刻开口及/或凹陷于层状物600至603与层状物620至623中，并将导电材料填入蚀刻的开口及/或凹陷中，以提供电性连接至金属栅极570至573以及源极/汲极的外延层410至412与430至433。
图13显示稀疏的区域200A与密集的区域200B的三维透视图。图13中的制作阶段与图12中的制作阶段相同。然而图13中的Y-Z平面，为源极/汲极的外延层410至412与源极/汲极的外延层430至433的剖视图，而非金属栅极570的剖视图。图13清楚显示本发明实施例中，虚置鳍状物240至242的高度减少，以避免限制稀疏的区域200A中源极/汲极的外延层410至412的横向成长。与此同时，稀疏的区域200A中虚置鳍状物的高度减少，实质上不影响密集的区域200B中虚置鳍状物250至253的高度。如此一来，虚置鳍状物250至253仍可避免密集的区域200B中源极/汲极的外延层430至433之间的电性桥接。
图14是本发明一实施例中，方法900的流程图。方法900包含的步骤910形成多个第一装置鳍状物与多个第一虚置鳍状物于芯片的第一区中，并形成多个第二装置鳍状物与多个第二虚置鳍状物于芯片的第二区中。第一区的图案密度低于第二区。
在一些实施例中，多个第一装置鳍状物与第二装置鳍状物包括III-V族化合物材料的半导体材料，且多个第一虚置鳍状物与第二虚置鳍状物包括介电结构。
在一些实施例中，多个第一装置鳍状物、第二装置鳍状物、第一虚置鳍状物与第二虚置鳍状物具有实质上相同的高度。在一些实施例中，每一第一虚置鳍状物的横向尺寸实质上大于每一第二虚置鳍状物的横向尺寸。
方法900包括步骤920，其形成多个栅极结构于多个第一装置鳍状物、第一虚置鳍状物、第二装置鳍状物与第二虚置鳍状物上。
方法900包括步骤930，其进行一或多道蚀刻工艺，使多个第一虚置鳍状物的高度减少量大于多个第二虚置鳍状物的高度减少量。在一些实施例中，步骤930包括进行第一蚀刻工艺以减少多个第一虚置鳍状物与多个第二虚置鳍状物的高度，并在第一蚀刻工艺之后进行第二蚀刻工艺，以减少多个第一虚置鳍状物的高度但不减少多个第二虚置鳍状物的高度。
方法900包括步骤940，其外延成长多个第一外延层于多个第一装置鳍状物上，并外延成长多个第二外延层于多个第二装置鳍状物上。高度减少的多个第一虚置鳍状物，实质上不限制多个第一外延层的横向成长。在步骤930之后进行步骤940。在一些实施例中，外延成长包括横向成长多个第一外延层，使多个第一外延层的部分成长高于多个第一虚置鳍状物的上表面。在一些实施例中，外延成长包括横向成长多个第二外延层，直到多个第二外延层物理接触多个虚置鳍状物。
可以理解的是，在方法900的步骤910至940之前、之中或之后可进行额外工艺。举例来说，方法900可包含栅极置换工艺，其中栅极结构为虚置结构，且可置换成含金属栅极的栅极结构。为简化说明，此处不详述其他额外步骤。
总之，本发明实施例在制作鳍状场效晶体管时，形成介电结构如虚置鳍状物。虚置鳍状物形成在较低图案密度的稀疏区域以及较高图案密度的密集区域中。图案密度依装置的不同种类而定。举例来说，稀疏区域中的装置可包含逻辑装置及/或输入/输出装置，其对效能(如速度、功率、或类似效能)或工艺容许范围(如接点着陆面积)的考量比对高晶体管密度的考量优先。相反地，密集区域中的装置可包含记忆装置(如静态随机存取记忆体)或其他种类的逻辑装置，其对高晶体管密度的考量比对效能的考量优先。依据本发明实施例，稀疏区域(非密集区域)中的虚置鳍状物高度减少，可避免限制源极/汲极层的横向外延成长。
由上述内容可知，本发明实施例比现有的鳍状场效晶体管装置提供更多优点。然而可以理解的是，其他实施例可提供额外优点，此处不需说明所有优点，且所有实施例不必具有特定优点。优点之一为稀疏区域中的虚置鳍状物高度降低，可让稀疏区域中的源极/汲极外延层不受虚置鳍状物局限。由于装置鳍状物(以及成长其上的外延层)彼此之间的空间充足，稀疏区域中的任何地方不太可能发生桥接。在稀疏区域中完全成长源极/汲极的外延层，可最佳化参数如外延应力、较大的表面积以用于形成硅化物、增加接点着陆的工艺容许范围、或类似点参数，进而增进稀疏区域中的装置效能。另一优点在于不对密集区域中的虚置鳍状物进行使虚置鳍状物高度降低的工艺，因此依然避免密集区域中的电性桥接。在此方式中，本发明实施例同时降低稀疏区域与密集区域中装置的顾虑。其他优点包括与现有的鳍状场效晶体管制作方法相容，因此本发明实施例不需额外处理，其实施方式简单且成本低。
上述进阶的光刻工艺、方法与材料可用于许多应用，比如鳍状场效晶体管。举例来说，上述内容适于图案化鳍状物，以产生间隔更紧密的结构，此外可依据本发明的上述实施例，处理鳍状场效晶体管的鳍状物之形成方法所用的间隔物(亦称作芯)。
本发明一实施例关于半导体装置。半导体装置包括第一装置鳍状物与第二装置鳍状物，各自位于半导体装置的第一区中。第一区具有第一图案密度。第一虚置鳍状物位于第一区中。第一虚置鳍状物位于第一装置鳍状物与第二装置鳍状物之间。第一虚置鳍状物具有第一高度。第三装置鳍状物与第四装置鳍状物，各自位于半导体装置的第二区中。第二区具有第二图案密度，且第二图案密度大于第一图案密度。第二虚置鳍状物位于第二区中。第二虚置鳍状物位于第三装置鳍状物与第四装置鳍状物之间。第二虚置鳍状物具有第二高度，且第二高度大于第一高度。
在一些实施例中，第二图案密度至少为第一图案密度的两倍。
在一些实施例中，第一虚置鳍状物与第二虚置鳍状物各自包含介电材料。
在一些实施例中，第二高度比第一高度大至少20nm。
在一些实施例中，第一高度与第二高度的比例界于约1:20至1:1.1之间。
在一些实施例中，第一虚置鳍状物的宽度至少为第二虚置鳍状物的宽度的两倍。
在一些实施例中，第一装置鳍状物与第二装置鳍状物隔有第一距离；第三装置鳍状物与第四装置鳍状物隔有第二距离；以及第一距离至少为第二距离的两倍。
在一些实施例中，第一装置鳍状物为第一形态的逻辑装置或输入/输出装置的一部分，而第二装置鳍状物为第二形态的逻辑装置或记忆装置的一部分，且第二形态的逻辑装置不同于第一形态的逻辑装置。
在一些实施例中，半导体装置还包括：第一外延层，成长于该第一装置鳍状物上；第二外延层，成长于该第二装置鳍状物上，其中该第一外延层与该第二外延层彼此分开，且该第一虚置鳍状物位于该第一外延层与该第二外延层下；一第三外延层，成长于该第三装置鳍状物上；一第四外延层，成长于该第四装置鳍状物上，其中该第二虚置鳍状物位于该第三外延层与该第四外延层之间，并物理接触该第三外延层与该第四外延层。
在一些实施例中，第一虚置鳍状物的上表面位于第一外延层与第二外延层的最外侧的横向凸起之下。
本发明另一实施例关于半导体装置。半导体装置包括多个第一鳍状结构，其各自包含第一半导体材料。多个第一源极/汲极外延层，形成于第一鳍状结构上。多个第一介电结构，夹设于第一鳍状结构之间。多个第二鳍状结构，其各自包含第二半导体材料。多个第二源极/汲极外延层，形成于第二鳍状结构上。多个第二介电结构，夹设于第二鳍状结构之间。第一鳍状结构、第二鳍状结构、第一介电结构、与第二介电结构各自垂直地向上凸起。相邻的第一鳍状结构之间的第一距离，实质上大于相邻的第二鳍状结构之间的第二距离。每一第一介电结构实质上比每一第二介电结构短但宽。第一源极/汲极外延层的部分位于第一介电结构的上表面上。第二源极/汲极外延层的部分物理接触第二介电结构。
在一些实施例中，第一鳍状结构包括第一形态的逻辑装置或输入/输出装置的鳍状结构；第二鳍状结构包括第二形态的逻辑装置或静态随机存取记忆装置的鳍状结构，且第二形态的逻辑装置与第一形态的逻辑装置不同；第一距离至少为第二距离的两倍；每一第一介电结构比每一第二介电结构短至少20nm；以及每一第一介电结构的宽度至少为每一第二介电结构的宽度的两倍。
本发明又一实施例包括半导体装置的制作方法。形成多个第一装置鳍状物与多个第一虚置鳍状物于基板的第一区中，并形成多个第二装置鳍状物与多个第二虚置鳍状物于基板的第二区中。第一区的图案密度小于第二区的图案密度。形成多个栅极结构于第一装置鳍状物、第一虚置鳍状物、第二装置鳍状物与第二虚置鳍状物上。进行一或多道蚀刻工艺，使第一虚置鳍状物的高度减少程度大于第二虚置鳍状物的高度减少程度。在进行一或多道蚀刻工艺之后，外延成长多个第一外延层于第一装置鳍状物上，并外延成长多个第二外延层于第二装置鳍状物上。第一外延层的横向成长实质上不受高度减少的第一虚置鳍状物限制。
在一些实施例中，形成第一装置鳍状物、第一虚置鳍状物、第二装置鳍状物与第二虚置鳍状物的步骤包括：形成多个鳍状物，其包括半导体材料作为第一装置鳍状物与第二装置鳍状物；以及形成多个介电结构，作为第一虚置鳍状物与第二虚置鳍状物。
在一些实施例中，形成第一装置鳍状物与第一虚置鳍状物的步骤，以及形成第二装置鳍状物与第二虚置鳍状物的步骤，使第一装置鳍状物、第二装置鳍状物、第一虚置鳍状物与第二虚置鳍状物具有实质上相同的高度。
在一些实施例中，第一虚置鳍状物的每一者之横向尺寸，实质上大于第二虚置鳍状物的每一者的横向尺寸。
在一些实施例中，进行一或多道蚀刻工艺的步骤包括：进行第一蚀刻工艺以减少第一虚置鳍状物与第二虚置鳍状物的高度；以及在进行第一蚀刻工艺之后进行第二蚀刻工艺，以减少第一虚置鳍状物的高度但不减少第二虚置鳍状物的高度。
在一些实施例中，外延成长的步骤包括横向成长多个第一外延层，使第一外延层的部分成长为高于第一虚置鳍状物的上表面。
在一些实施例中，外延成长的步骤包括横向成长第二外延层，直到第二外延层物理接触第二虚置鳍状物。
在一些实施例中，形成多个栅极结构的步骤包括形成多个虚置栅极结构，且还包括将虚置栅极结构置换成多个含金属栅极的栅极结构。
上述实施例的特征有利于本技术领域中具有通常知识者理解本发明。本技术领域中具有通常知识者应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中具有通常知识者亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。

Claims (1)

1.一种半导体装置，包括：
一第一装置鳍状物与一第二装置鳍状物，各自位于一半导体装置的一第一区中，且该第一区具有一第一图案密度；
一第一虚置鳍状物，位于该第一区中，其中该第一虚置鳍状物位于该第一装置鳍状物与该第二装置鳍状物之间，且该第一虚置鳍状物具有一第一高度；
一第三装置鳍状物与一第四装置鳍状物，各自位于该半导体装置的一第二区中，该第二区具有一第二图案密度，且该第二图案密度大于该第一图案密度；以及
一第二虚置鳍状物，位于该第二区中，其中该第二虚置鳍状物位于该第三装置鳍状物与该第四装置鳍状物之间，该第二虚置鳍状物具有一第二高度，且该第二高度大于该第一高度。
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