CN110931428A - 分割多个半导体管芯的方法 - Google Patents

分割多个半导体管芯的方法 Download PDF

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CN110931428A
CN110931428A CN201910883081.7A CN201910883081A CN110931428A CN 110931428 A CN110931428 A CN 110931428A CN 201910883081 A CN201910883081 A CN 201910883081A CN 110931428 A CN110931428 A CN 110931428A
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迈克尔·J·塞登
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Abstract

本发明题为“分割多个半导体管芯的方法”。本发明公开了分割多个半导体管芯的方法的实施方式。实施方式可包括：在耦接在半导体衬底的第一侧上的背面金属层中形成图案，其中半导体衬底包括多个半导体管芯。该方法可包括在所述背面金属层中的图案处基本上蚀刻穿过半导体衬底的厚度，并且射流烧蚀耦接到半导体衬底的第二侧的钝化材料层以分割多个半导体管芯。

Description

分割多个半导体管芯的方法
技术领域
本文档的各方面整体涉及用于分割衬底的系统和方法。更具体的实施方式涉及半导体衬底。
背景技术
半导体衬底用于形成各种半导体器件。半导体器件通常分布在多个管芯中的半导体衬底的平坦表面上。使用分割工艺(比如锯切)将多个管芯彼此分开。
发明内容
分割多个半导体管芯的方法的实施方式可包括：在耦接在半导体衬底的第一侧上的背面金属层中形成图案，其中半导体衬底包括多个半导体管芯。该方法可包括在背面金属层中的图案处基本上蚀刻穿过半导体衬底的厚度，并且射流烧蚀耦接到半导体衬底的第二侧的钝化材料层以分割多个半导体管芯。
分割多个半导体管芯的方法的实施方式可以包括以下各项中的一者、全部或任一者：
该方法还可包括从第一带拆卸半导体衬底并且将半导体衬底安装到第二带。
从第一带拆卸半导体衬底还可包括在基本上蚀刻穿过半导体衬底的厚度之后拆卸。
该方法还可包括在基本上蚀刻穿过半导体衬底的厚度之后将半导体衬底安装到第一带。
射流烧蚀钝化材料层还可包括从半导体衬底的第二侧射流烧蚀。
射流烧蚀钝化材料层还可包括从半导体衬底的第一侧射流烧蚀。
基本上蚀刻穿过半导体衬底的厚度还包括等离子体蚀刻。
半导体衬底的厚度可小于50微米。
半导体衬底的厚度可以是25微米。
背面金属可具有介于1微米至15微米之间的厚度。
背面金属可具有介于1微米至3微米之间的厚度。
分割多个半导体管芯的方法的实施方式可包括在耦接在半导体衬底的第一侧上的背面金属层中形成图案，其中半导体衬底可包括多个半导体管芯。该方法可包括将半导体衬底安装到第一带并且在背面金属层中的图案处基本上蚀刻穿过半导体衬底的厚度。该方法还可包括射流烧蚀耦接到半导体衬底的第二侧的钝化材料层以分割多个半导体管芯。
分割多个半导体管芯的方法的实施方式可以包括以下各项中的一者、全部或任一者：
该方法还可包括从第一带拆卸半导体衬底并且将半导体衬底安装到第二带。
从第一带拆卸半导体衬底还可包括在基本上蚀刻穿过半导体衬底的厚度之后拆卸。
射流烧蚀钝化材料层还可包括从半导体衬底的第二侧射流烧蚀。
射流烧蚀钝化材料层还可包括从半导体衬底的第一侧射流烧蚀。
基本上蚀刻穿过半导体衬底的厚度还可包括等离子体蚀刻。
半导体衬底的厚度可小于50微米。
半导体衬底的厚度可以是25微米。
背面金属可具有介于1微米至15微米之间的厚度。
对于本领域的普通技术人员而言，通过说明书和附图并且通过权利要求书，上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述实施方式，在附图中类似标号表示类似元件，并且：
图1是在其上具有钝化层和背面金属层的半导体衬底的侧视图；
图2是在背面金属层的图案化之后图1的衬底的侧视图；
图3是在将衬底材料向下蚀刻到钝化层之后图2的衬底的侧视图；
图4是在射流烧蚀期间拆卸和安装之后图3的衬底的侧视图；
图5是在钝化层的烧蚀之后示于图4中的两个分割管芯的侧视图。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的符合预期射流烧蚀系统和相关方法的许多附加的部件、组装工序和/或方法元素将显而易见地与本公开的特定实施方式一起使用。因此，例如，尽管公开了特定实施方式，但是此类实施方式和实施部件可以包括符合预期操作和方法的本领域已知用于此类射流烧蚀系统和相关方法以及实施部件和方法的任何形状、尺寸、样式、类型、型号、版本、量度、浓度、材料、数量、方法元素、步骤等。
对于厚度小于50微米的半导体管芯，存在特定的处理挑战。管芯处理、管芯强度以及用管芯执行处理操作全都存在特定挑战，因为管芯和晶圆破损可显著降低产率并且/或者影响器件可靠性。管芯强度受到传统分割选项的负面影响，比如锯切，这引起管芯破碎以及沿着管芯通道的破裂。在锯切工艺期间形成的这些碎片和裂缝最终可在操作和可靠性测试期间传播，从而导致管芯失效。
参见图1，在本文档公开的各种实施方式中，半导体衬底2包括多个半导体管芯4(两个随后在附图中示出)，该多个半导体管芯已使用半导体制造工艺进行处理以在其中或在其上形成一个或多个半导体器件(未示出)。在完成制造工艺之后(或在一些实施方式中，在其一些部分期间)，半导体衬底2在半导体衬底2的与一个或多个半导体器件已在其上形成为期望衬底厚度6的侧面相对的侧面上减薄。使用背面研磨、打磨、湿法蚀刻、其任何组合或用于在衬底的最大平坦表面上基本上均匀地去除背面损坏和/或半导体衬底2的材料的任何其他技术来进行减薄工艺。在各种实施方式中，通过非限制性示例，半导体衬底4可以是单晶硅、多晶硅、非晶硅、玻璃、蓝宝石、红宝石、砷化镓、碳化硅、绝缘体上硅以及任何其他半导体衬底类型。
在各种实施方式中，减薄工艺可在晶圆周围产生边缘环(比如在加利福尼亚州圣克拉拉的迪思科科技美国公司(Disco Hi-Tec America,Inc.,Santa Clara,California)销售的TAIKO背面研磨工艺中存在的边缘环)。边缘环用于在减薄之后在结构上支撑晶圆，使得在后续处理步骤期间不需要使用晶圆载体。在各种实施方式中，在半导体衬底2已被安装到背面研磨带之后，可以进行减薄工艺，无论是否在背面研磨期间形成边缘环。在各种实施方式中，可采用各种背面研磨带，包括与后续等离子体蚀刻操作兼容的那些背面研磨带。
在减薄工艺之后，形成在半导体衬底2中的各种管芯4需要彼此分割，因此它们随后可封装到半导体封装中。在各种实施方式中，在减薄工艺之后，通过非限制性示例，通过溅射、蒸发或另一种金属沉积工艺将背面金属层10施加到半导体管芯。在各种实施方式中，在晶圆由边缘环支撑或由背面研磨带支撑的同时进行沉积工艺。然而，在其他实施方式中，衬底可从背面研磨带拆卸并且安装到另一个支撑带以用于随后的处理步骤。
图1示出在背面金属沉积工艺和减薄工艺之后半导体衬底2的实施方式。在各种实施方式中，如图所示，衬底2与带14(在各种实施方式中，其可为背面研磨或其他支撑带)耦接。然而，在其他实施方式中，在工艺的该阶段处，晶圆可不与带14耦接(诸如当使用边缘环时)。如图所示，一个或多个半导体管芯4(尚未单独可见)被钝化材料层16覆盖。在各种实施方式中，通过非限制性示例，钝化材料16可包含氮化硅、氧化物、金属电测试结构、电测试焊盘、二氧化硅、聚酰亚胺、金属焊盘、残余凸块下金属化(UBM)、它们的任何组合，以及能够促进一个或多个半导体管芯之间的电连接或热连接并且/或者保护一个或多个半导体管芯免受污染的任何其他层或材料。因此，如本文所用，术语“钝化材料”和“钝化层”包含上述材料中的任一种，无论材料是否被沉积以用作钝化材料或者材料是否仅在管芯通道区中形成非等离子体可蚀刻部分或层。
如图1所示，半导体衬底2的总厚度8是衬底厚度6、背面金属10的厚度18和钝化材料16的厚度12的相加厚度。在各种实施方式中，背面金属的厚度可在约1微米至约15微米之间变化。在特定实施方式中，背面金属的厚度可在约1微米至约3微米之间。在各种实施方式中，半导体衬底2的总厚度8可小于约50微米。在特定实施方式中，半导体衬底的总厚度8可在约25微米至约35微米之间。在各种实施方式中，总厚度8可为约25微米。
参见图2，示出了在背面金属层10的图案化之后的衬底2。可以使用各种光刻工艺中的任一种来完成图案化，这些光刻工艺涉及施加光致抗蚀剂；曝光，显影，然后移除光致抗蚀剂；使用适当的蚀刻剂蚀刻背面金属10，以及移除光致抗蚀剂。在背面金属层10的图案化区域/管芯通道20中蚀刻和图案化背面金属层10之后暴露衬底材料的情况下，衬底的材料准备好进行蚀刻。在各种实施方式中，衬底材料然后一直向下蚀刻到钝化层16或朝向钝化层16蚀刻。然而，在其他实施方式中，蚀刻可部分地穿过或基本上穿过衬底2的厚度6向下到钝化层16或朝向钝化层16进行(在各种实施方式中，可使用等离子体蚀刻工艺来进行蚀刻)。通常，用于蚀刻衬底2的材料的等离子体蚀刻化学物质不蚀刻钝化层的材料或通道中的任何金属结构(电测试/对准特征等)，从而在蚀刻衬底之后留下多个仍未分割的半导体管芯。图3中示出了在蚀刻衬底2之后的半导体管芯4。
参见图4，示出在从原始(第一)带14拆卸并安装到新带22(在各种实施方式中，其可以是拾取带)之后图3的衬底2。如图所示，管芯4仍通过至少钝化层16的材料耦接在一起。在其中衬底仅被部分分割或基本上分割的那些实施方式中，半导体材料的一些部分仍可将多个管芯耦接在一起。对于其中使用边缘环的那些实施方式，边缘环仍可用于在拆卸和安装过程期间支撑管芯4。在其中采用边缘环并且在不安装到背面研磨带的情况下处理衬底的一些实施方式中，可以翻转并安装衬底，而无需在蚀刻步骤之后首先拆卸衬底。
图4示出流体射流24被施加到半导体管芯40之间的通道20的位置，从而使钝化层16的材料(保留在通道20中的任何其他金属结构)被烧蚀掉。虽然水可以用作用于烧蚀的液体，但是在各种方法实施方式中可以采用其他流体、气体、流体的组合以及流体和气体的组合。
虽然在各种实施方式中并且如图4所示，在蚀刻衬底后翻转衬底2之后，将流体射流24施加到衬底2的钝化层侧(第二侧)26，但在其他实施方式中，衬底2可以不翻转，并且可以将流体射流24施加到通道区域，以从衬底的背面金属侧(第一侧)28烧蚀钝化层的材料。虽然衬底2在图2至图4中被示为具有蚀刻穿过的衬底2的材料的全厚度6，但在如前所讨论的一些实施方式中，衬底材料的一部分厚度可保持未蚀刻来为衬底增加足够强度，以使其可以拆卸、翻转和安装。然后可以施加射流烧蚀工艺并且也将其用于移除通道20中的钝化材料和衬底的剩余材料。然而，在一些实施方式中，在施加射流烧蚀之前，可以不拆卸和翻转衬底2。在此类实施方式中，已经观察到钝化层的材料被驱动到带中并且在流体射流的压力下成功地分离各种管芯。
参见图5，示出在钝化材料16的射流烧蚀之后的半导体管芯4。现在可以从支撑带22中拾取它们并准备用于随后的封装操作。
如图2和图3所示，图案化的背面金属用作衬底蚀刻工艺的图案化。因此，可能不需要附加光刻处理来进行衬底蚀刻工艺。然而，在一些实施方式中，在射流烧蚀工艺期间，可以使用光刻步骤来保护管芯上的金属或其他材料。另外，因为半导体衬底2的材料用于在水射流烧蚀工艺期间引导水的流动(即，通过阻止流体流动，衬底材料导致钝化材料在流体流的压力下屈服，或者将流体流的能量集中在钝化材料上)，所以不需要进行附加光刻步骤来促进烧蚀工艺。光刻步骤的这种减少减少了在减薄工艺之后涉及晶圆的总处理步骤的数量，这可以通过减少衬底破损来增加工艺的总产率。此外，由于射流烧蚀用于完全清除通道区域，因此不需要在设计中添加特殊设计(比如退出管芯和/或使用部分管芯)，从而增加每个晶圆的总管芯。此外，可能不需要使用不包括电测试或对准特征的特殊通道设计来实现等离子体衬底蚀刻工艺。另外，不使用任何锯切分割工艺可能导致良好的管芯增加并且由于在锯切工艺期间引起的管芯破碎和破裂的减少而增加管芯强度。
在各种方法实施方式中，背面金属可具有介于1微米至3微米之间的厚度。
在以上描述提到射流烧蚀系统和相关方法以及实施部件、子部件、方法和子方法的特定实施方式的地方，应当易于显而易见的是，可在不脱离其实质的情况下做出多种修改，并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他射流烧蚀系统和相关方法。

Claims (10)

1.一种分割多个半导体管芯的方法，所述方法包括：
在耦接在半导体衬底的第一侧上的背面金属层中形成图案，所述半导体衬底包括多个半导体管芯；
在所述背面金属层中的所述图案处基本上蚀刻穿过所述半导体衬底的厚度；以及
射流烧蚀钝化材料层，所述钝化材料层耦接到所述半导体衬底的第二侧以分割所述多个半导体管芯。
2.根据权利要求1所述的方法，还包括从第一带拆卸所述半导体衬底并且将所述半导体衬底安装到第二带。
3.根据权利要求2所述的方法，其中从所述第一带拆卸所述半导体衬底还包括在基本上蚀刻穿过所述半导体衬底的所述厚度之后拆卸。
4.根据权利要求1所述的方法，还包括在基本上蚀刻穿过所述半导体衬底的厚度之后将所述半导体衬底安装到第一带。
5.根据权利要求1所述的方法，其中射流烧蚀所述钝化材料层还包括从所述半导体衬底的所述第二侧射流烧蚀。
6.根据权利要求1所述的方法，其中射流烧蚀所述钝化材料层还包括从所述半导体衬底的所述第一侧射流烧蚀。
7.根据权利要求1所述的方法，其中基本上蚀刻穿过所述半导体衬底的所述厚度还包括等离子体蚀刻。
8.根据权利要求1所述的方法，其中所述半导体衬底的所述厚度小于50微米。
9.根据权利要求1所述的方法，其中所述半导体衬底的所述厚度为25微米。
10.根据权利要求1所述的方法，其中所述背面金属包括介于1微米至15微米之间的厚度。
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