CN110930927A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110930927A CN110930927A CN201911249586.4A CN201911249586A CN110930927A CN 110930927 A CN110930927 A CN 110930927A CN 201911249586 A CN201911249586 A CN 201911249586A CN 110930927 A CN110930927 A CN 110930927A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area, wherein a scanning driving circuit, a first type clock signal line and a second type clock signal line are arranged in the non-display area, the first type clock signal line is electrically connected to the scanning driving circuit, and the second type clock signal line is arranged in parallel to the first type clock signal line; the first type of clock signal line comprises at least two first clock signal lines, and the second type of clock signal line comprises at least one second clock signal line; the whole time sequence on the second type clock signal line and at least part of the whole time sequence on the first type clock signal line are in the same frequency and reverse direction; wherein, the same frequency reversal means that the frequency is the same, and the effective potential is opposite in relative height; the effective potential is set to a non-zero potential. Therefore, at least part of electromagnetic radiation can be counteracted by utilizing the reverse clock signal on the second type of clock signal line, so that the electromagnetic interference can be improved, and the influence of the display panel on peripheral electronic products can be reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of Display technology, Liquid Crystal Display (LCD) panels and Organic Light Emitting Diode (OLED) Display panels gradually become two major Display panels in the Display field, and LCD panels and OLED Display panels are widely used in devices or scenes capable of integrating Display functions, known by those skilled in the art, such as computers, mobile phones, wearable devices, and vehicles.
Generally, the operation of electronic products causes Interference to other electronic products in the periphery, which can be referred to as Electromagnetic Interference (EMI), and the electronic products subjected to the EMI have reduced performance or even fail to operate normally. Based on this, when the display panel is integrally arranged in some devices or applied to some scenes, for example, when the display panel is applied to a vehicle-mounted display, as a vehicle-mounted display screen, the display panel may generate electromagnetic interference to other vehicle-mounted electronic products.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for reducing electromagnetic interference radiated to the periphery by the display panel, thereby reducing the electromagnetic interference to other vehicle-mounted electronic products when the display panel is used as a vehicle-mounted display screen.
In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes a display area and a non-display area surrounding the display area, where a scan driving circuit, a first type clock signal line and a second type clock signal line are disposed in the non-display area, the first type clock signal line is electrically connected to the scan driving circuit, and the second type clock signal line is disposed in parallel to the first type clock signal line;
the first type of clock signal line comprises at least two first clock signal lines, and the second type of clock signal line comprises at least one second clock signal line; the whole time sequence on the second type clock signal line and at least part of the whole time sequence on the first type clock signal line are in the same frequency and reverse direction;
wherein, the same frequency reversal means that the frequency is the same, and the effective potential is opposite in relative height; the effective potential is set to a non-zero potential.
In a second aspect, embodiments of the present invention provide a display device, which includes any one of the display panels provided in the first aspect.
The display panel provided by the embodiment of the invention is provided with at least two first clock signal lines by arranging the first clock signal lines, and the second clock signal lines comprise at least one second clock signal line; the whole time sequence on the second type clock signal line and at least part of the whole time sequence on the first type clock signal line are in the same frequency and reverse direction; the same-frequency reverse direction refers to the same frequency, the effective potentials are opposite in relative height, and the effective potentials are set to be non-zero potentials, so that when the magnitude of the energy radiated outwards by the display panel is considered, the overall time sequence on the second type of clock signal line can correspondingly generate a reverse electromagnetic field, and the reverse electromagnetic field can weaken (even offset) the interference electromagnetic field correspondingly generated by the overall time sequence on the first type of clock signal line, so that the interference energy radiated outwards by the display panel can be reduced, the problem that interference is caused to other electronic products (such as other electronic products around a vehicle-mounted display screen) around the display panel after the interference energy is radiated out can be weakened, and the improvement of the performance of other electronic products on the vehicle can be realized, namely the normal operation of the electronic products can be facilitated.
Drawings
FIG. 1 is a timing diagram illustrating a driving method of a display panel according to the related art;
FIG. 2 is a schematic diagram illustrating an EMI effect corresponding to a driving timing of the display panel of FIG. 1;
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a driving timing sequence according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another driving timing sequence provided in the embodiment of the present invention;
fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;
FIG. 9 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;
fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
In the structure of the existing display panel, the display panel includes a display area and a non-display area; in the display area, scanning lines and data lines are arranged in a crossed manner to limit a sub-pixel area, and sub-pixels are arranged in the sub-pixel area; in the non-display region, a driver circuit including a scan driver circuit which is also commonly referred to as a shift register circuit and a data driver circuit which is commonly referred to as a multiplexer circuit is provided. The shift register circuit comprises shift registers which are arranged in a cascade mode, wherein part of input ends of the shift registers at each stage are electrically connected with a clock signal line, the output ends of the shift registers at each stage are electrically connected with scanning lines corresponding to the sub-pixels at the same row, and the scanning lines provide scanning signals (also called grid opening signals) for the sub-pixels at the same row which are electrically connected with the scanning lines; the multi-path selection circuit comprises a plurality of multi-path selection units, the control end of each multi-path selection unit corresponds to the output end one by one to realize the gating of the output end and the input end, the output end is correspondingly connected with the data line, and the data line is used for writing data signals into the sub-pixels under the action of the data selection control signal line. The principle of the display panel generating electromagnetic interference is exemplarily described below with reference to fig. 1 and 2.
Referring to fig. 1 and 2, in the prior art, a first clock signal CKV1 'and a second clock signal CKV 2' are input to a scan driving circuit, and correspondingly generate scan signals in accordance with their timings, where the scan signals (also called Gate signals, shown as Gate1 ', Gate 2', Gate3 ', … … and Gate' in fig. 1, and the value of n may be 4, 5, 6, and other positive integers) are scanned one by one in a progressive manner; during the scan signal enable period (high period in fig. 1) of the current stage, the clock control signal (shown as MUX0 in fig. 1) controls each data line to write the data signal to the sub-pixel of the current row. Wherein, the scanning time of each line can be called as a line scanning period TH-syncThe scanning period is the same as the clock period corresponding to the clock signal; the scanning frequency corresponding to the line scanning period is fH-sync，fH-sync＝1/TH-sync. Taking the MUX unit 1:3 as an example (as shown in fig. 1), the MUX0 includes three clock control sequences, which are shown as SW01, SW02 and SW03 in fig. 1, so that the overall frequency of the clock control signal MUX0 is 3 times the scan frequency. Because the clock period and the scanning period are fixed, the clock frequency and the scanning frequency are fixed, so that an energy peak value appears at a fixed frequency position of a low frequency band of the vehicle gauge, namely the energy peak value appears periodically, and when a larger energy value at the energy peak value radiates outwards, other electronic products on the vehicle are easily interfered by electromagnetic waves and cannot work normally. The EMI test results are shown in FIG. 2, in which the abscissa X represents frequency in Hertz (Hz) and the ordinate Y represents DB value, i.e., the intensity of radiation energy in absolute units(a.u.) the EMI test result is obtained by adopting a pure counting method; wherein, L011 and L012 respectively represent the average value and the maximum value of the same vehicle specification required limit value, and L021 and L022 respectively represent the magnitude of the EMI radiation energy at different frequencies obtained by the test. As can be seen from fig. 2, energy peaks occur at positions at which the scanning frequency is multiplied. Thus, the energy at the energy peak is radiated to the periphery of the display panel, which may affect the normal operation of other electronic products in the vehicle.
In view of the above problems, embodiments of the present invention provide a display panel and a display device, in which a second type of clock signal line is provided to provide a clock signal that is in the same frequency as and in the opposite direction (also written as "inverted phase") to a clock signal on a first type of clock signal line, that is, an inverted clock signal, so as to form an inverted electromagnetic field relative to an interference electromagnetic field, and the inverted electromagnetic field is used to weaken the interference electromagnetic field, so as to weaken electromagnetic interference caused by the fixed clock frequency and scanning frequency, that is, to improve electromagnetic interference, and to avoid the problem that the interference energy is radiated to the periphery to cause interference to other electronic products on the vehicle, thereby facilitating the improvement of the performance of other electronic products on the vehicle, that is, facilitating the normal operation of the vehicle-mounted.
The following describes an exemplary display panel provided by an embodiment of the present invention with reference to fig. 3 to 16.
Illustratively, referring to fig. 3, 4 and 5, the display panel 90 includes a display area 920 and a non-display area 910 surrounding the display area 920; a scan driving circuit 950, a first type clock signal line 960 and a second type clock signal line 970 are disposed in the non-display region 910, the first type clock signal line 960 is electrically connected to the scan driving circuit 950, and the second type clock signal line 970 is disposed in parallel with the first type clock signal line 960; the first type of clock signal line 960 includes at least two first clock signal lines (shown as a first sub-line 961 and a second sub-line 962), and the second type of clock signal line 970 includes at least one second clock signal line (shown as a fifth sub-line 971 and a sixth sub-line 972, which are exemplary 971 for the second clock signal line unless otherwise specified); the overall timing on the second type clock signal line 970 is at least partially in phase reversal with the overall timing on the first type clock signal line 960; wherein, the same frequency reversal means that the frequency is the same, and the effective potential is opposite in relative height; the effective potential is set to a non-zero potential.
The display area 920 of the display panel 90 is used for displaying an image to be displayed.
For example, the display panel 90 may be an LCD panel, an OLED display panel, or other types of display panels known to those skilled in the art, and the embodiment of the invention is not limited thereto.
The non-display area 910 of the display panel 90 is used to provide the scan driving circuit 950, the anti-static circuit 942, the integrated circuit 940, the data driving circuit 944 and other circuit structures known to those skilled in the art, which is not limited in the embodiments of the present invention.
Illustratively, the non-display area 910 is shown in FIG. 3, by way of example only, as being disposed around the display area 920. In other embodiments, the non-display area 910 may be further configured to half surround the display area 920, or the non-display area 910 is adjacent to the display area 920 in the left and right directions, or other relative positions known to those skilled in the art may be adopted, which is not limited in this embodiment of the present invention.
The scan driving circuit 950 is used for generating a scan signal according to a clock signal provided by a first type clock signal line 960; the circuit element structure and the operation principle of the scan driving circuit 950 can adopt any structure and the corresponding operation principle known to those skilled in the art, and are not described in detail nor limited in the embodiments of the present invention.
Illustratively, the scan driving circuit 950 includes a plurality of scan driving units 955 arranged IN cascade, each scan driving unit 955 including a first clock input terminal CK1, a second clock input terminal CK2, a scan trigger signal receiving terminal IN, and a scan signal output terminal OUT. The display panel 90 may further include scan lines 931 and data lines 932, where the scan lines 931 and the data lines 932 intersect to define a plurality of sub-pixel regions 934, and the sub-pixels 933 are disposed in the sub-pixel regions 934. The first sub-line 961 is electrically connected to the first clock input terminal CK1, the second sub-line 962 is electrically connected to the second clock input terminal CK2, and the scan line 931 is electrically connected to the scan signal output terminal OUT 1. The display panel 90 further includes a scan shift register trigger signal line 953, the scan shift register trigger signal line 953 is electrically connected to a scan trigger signal receiving terminal IN1 of the first stage scan driving unit 955, and the scan trigger signal receiving terminal IN of the next stage scan driving unit 955 is electrically connected to a scan signal output terminal OUT of the previous stage scan driving unit 955 through a scan shift signal line 9311.
For example, the scan line 931 and the data line 932 may intersect vertically or not, and the embodiment of the invention is not limited thereto.
First, fig. 3 shows only a scan line 931, a data line 932, a first type clock signal line 960, and a second type clock signal line 970 in straight lines. In the actual product structure of the display panel 90, the actual shapes of the scan lines 931, the data lines 932, the first type clock signal lines 960, and the second type clock signal lines 970 can be set according to the actual requirements of the display panel 90, which is not limited in the embodiment of the present invention.
Next, it should be noted that fig. 3 illustrates only the sub-pixel region 934 as a rectangle. In the actual product structure of the display panel 90, the shape of the sub-pixel region 90 may be set according to the wiring manner of the display panel 90 and other requirements, which is not limited in the embodiment of the invention.
Again, it should be noted that fig. 3 only shows that the scan lines 931 and the data lines 932 are extended from the display area 920 to the non-display area 910. In other embodiments, the lengths of the scan lines 931 and the data lines 932 and the relative position relationship between the scan lines and the data lines and the boundary of the display area 920 may also be set according to actual requirements of the display panel 90, which is not limited by the embodiment of the present invention.
The second type clock signal line 970 is not electrically connected to the scan driving circuit 950, but is only used for providing a clock signal having the same frequency and the same direction as the overall timing sequence of the first type clock signal line 960, and the clock signal correspondingly generates a reverse electromagnetic field. The overall timing on the first type clock signal line 960 correspondingly generates an interference electromagnetic field, which propagates to the periphery of the display panel to generate electromagnetic radiation. In the embodiment of the present invention, the reverse electromagnetic field having the same frequency and the reverse direction as the interference electromagnetic field is generated by setting the whole time sequence on the second type clock signal line 970, and the vector field of the reverse electromagnetic field can be superimposed on the vector field of the interference electromagnetic field, so that the energy value of the interference electromagnetic field radiated to the periphery by the display panel is weakened, and the electromagnetic interference phenomenon is improved.
Exemplarily, fig. 4 shows the frequency and phase relationship between the second clock signal CKV20 on the second type clock signal line 970 and the clock signal on the first type clock signal line 960 (shown as the first sub-clock signal CKV11 on the first sub-line 961 and the second sub-clock signal CKV12 on the second sub-line). Referring to FIG. 4, taking the high level potentials of CKV11 and CKV12 as the effective potentials, TWidthRepresenting the duration of the effective potential, TGapRepresenting the duration of the ineffective potential, the duration T of at least part of the effective potentialWidthIn addition, the second clock signal CKV20 is at a low level, and the low level of CKV20 is at an active level, which is herein understood to be an enable level. In this way, the signal timing on at least a portion of the second type clock signal line 970 and the signal timing on the first type clock signal line 960 can be inverted in the same frequency, so as to reduce the electromagnetic interference by means of mutual cancellation of the vector fields of the electromagnetic field.
Illustratively, the disable potential is set to 0V, the effective potentials of the clock signals CKV11 and CKV12 on the first type clock signal line 960 may be +8V to +10V, and the effective potential of the second clock signal CKV20 on the second type clock signal line 970 may be-10V to-15V.
It is understood that "the effective potentials are opposite to each other" means that one of the effective potentials is higher than the reference potential and the other effective potential is lower than the reference potential on the premise that the non-enabled potentials are the same reference potential. Usually, the reference potential is 0V, and one of the effective potentials on the first type clock signal line and the second type clock signal line is a positive potential and the other is a negative potential.
In other embodiments, the effective potential may also adopt other potential value ranges known to those skilled in the art, and the embodiments of the present invention are not described or limited again.
Optionally, with reference to fig. 5 and 6, the amplitude a20 of the effective potential of the signal CKV20 on the second type clock signal line 970 is greater than the amplitude a10 of the effective potential of the signals (CKV11 and CKV12) on the first type clock signal line 960.
The timing of the scanning signals on the scanning lines 931 can be controlled by the timing of the signals on the first-type clock signal line 960, so that the overall timing of the scanning signals on each scanning line corresponding to one frame of the display screen is consistent with the overall timing on the first-type clock signal line 960. Based on this, in the prior art, the electromagnetic interference caused by the overall timing of the first type clock signal line 960 includes not only the electromagnetic interference caused by the interfering electromagnetic field radiated outward by the first type clock signal line 960 itself, but also the electromagnetic interference caused by the interfering electromagnetic field radiated outward by the scan line 931 in accordance with the timing thereof. Thus, the overall timing of the clock signals on the second type clock signal line 970 is set such that the overall timing on the first type clock signal line 960 is maintained in the same frequency and opposite direction, and the overall timing on the scan line 931 is also maintained in the same frequency and opposite direction, so that the electromagnetic field generated by the clock signals on the second type clock signal line 970 can cancel at least part of the interference electromagnetic field on the first type clock signal line 960 and at least part of the interference electromagnetic field on the scan line 931.
Therefore, the arrangement of A20> A10 can increase the amplitude of the effective potential in the reverse magnetic field, which is beneficial to enabling the electromagnetic radiation generated on the first type clock signal line and the scanning signal line to be completely offset by the electromagnetic radiation of the reverse magnetic field in a vector addition mode, namely completely eliminating the electromagnetic interference generated by the clock signal on the first type clock signal line and the scanning signal on the scanning line, and greatly improving the problem that the interference energy generated in the display panel radiates to the periphery to cause the electromagnetic interference on other electronic products.
Illustratively, when the disable potential is set to 0V, the effective potentials of the clock signals CKV11 and CKV12 on the first type clock signal line 960 may be +8V to +10V, and the effective potential of the clock signal CKV20 on the second type clock signal line 970 may be-13V to-15V.
In other embodiments, the effective potential may also adopt other potential value ranges known to those skilled in the art, and the embodiments of the present invention are not described or limited again.
Optionally, with continued reference to fig. 4 and 5, the first type of clock signal line 960 includes two first clock signal lines, a first sub-line 961 and a second sub-line 962; the second type of clock signal line 970 includes one second clock signal line 971, shown as a fifth sub-line 971; the clock signal on the first clock signal line includes a plurality of consecutive first clock segments TC10The clock signal on the second clock signal line 971 includes a plurality of second clock segments T in seriesC20(ii) a First clock segments (respectively with first sub-clock segments T) on two first clock signal linesC11And a second sub-clock segment TC12Shown) are sequentially spaced, a second clock segment is spaced from TC20First clock period TC10Correspond in sequence, and the second clock segment TC20And the corresponding first clock period TC10The effective potentials of (2) are opposite in sign.
With this arrangement, the second clock signal on the second clock signal line 971 can be made to coincide in timing with the overall timing of the clock signals of the first sub-line 961 and the second sub-line 962; that is, the timing at which the level of the clock signal on the first sub-line 961 changes corresponds to the timing at which the level of the second clock signal changes, and the timing at which the level of the clock signal on the second sub-line 962 changes also corresponds to the timing at which the level of the second clock signal changes; therefore, the time sequence of the second clock signal can effectively cover the electromagnetic interference generated by the clock signals on the first sub-line 961 and the second sub-line 962, and the effect of eliminating the electromagnetic interference phenomenon is achieved. It is to be understood that "the timing at which the level changes" and "the timing at which the level changes" in this paragraph are both understood as the timing at which the level of the clock signal is switched between the high level and the low level, and the potential floating during actual use is ignored.
It should be noted that "opposite" merely means that the signs of the potentials are different, i.e., the potentials are positive, negative, and the absolute value of the potential is not limited.
Alternatively, referring to fig. 7 and 8, the number of the second clock signal lines is equal to the number of the first clock signal lines, and the timing on each second clock signal line is set to be in one-to-one correspondence with the timing on one first clock signal line and in the same frequency reverse direction.
According to the arrangement, the interference electromagnetic field correspondingly generated by the clock signal on each first clock signal line is at least partially offset by the reverse electromagnetic field correspondingly generated by the clock signal on one second clock signal line, so that the time sequence of each second clock signal line only keeps the same frequency and reverse direction with the time sequence on one first clock signal line, and the time sequence setting mode of the clock signal on the second clock signal line is simple, and the programming difficulty of a driving algorithm is favorably reduced.
For example, in fig. 7, the number of the second clock signal lines is equal to the number of the first clock signal lines, and both the second clock signal lines and the first clock signal lines are two; the first clock signal line is a first sub-line 961 and a second sub-line 962, and the loaded clock signals are a first sub-clock signal CKV11 and a second sub-clock signal CKV 12; the second clock signal lines are respectively a fifth sub-line 971 and a sixth sub-line 972, and the loaded clock signals are respectively a fifth sub-clock signal CKV21 and a sixth sub-clock signal CKV22, which are superposed to correspond to the overall timing of the second clock signal CKV 20. Meanwhile, the fifth sub-clock signal CKV21 is in the same frequency and opposite direction as the first sub-clock signal CKV11, and the sixth sub-clock signal CKV22 is in the same frequency and opposite direction as the second sub-clock signal CKV 12.
In other embodiments, the number of the first clock signal lines may also be 3, 4 or more, and may be set according to the actual requirement of the display panel 90, which is not limited in the embodiment of the present invention. The number of the second clock signal lines may be set to be equal to the number of the first clock signal lines, corresponding to the number of the first clock signal lines.
It should be noted that fig. 7 only exemplarily shows that two first clock signal lines are disposed next to each other, two second clock signal lines are disposed next to each other, and the second clock signal lines are both located on a side of the first clock signal lines away from the display area, but do not constitute a limitation on the display panel provided in the embodiment of the present invention. In other embodiments, the relative position relationship between the first clock signal line and the second clock signal may also be set according to the actual requirements of the display panel, which is not limited in the embodiments of the present invention.
Optionally, referring to fig. 7 and 9, the second-type clock signal line 970 includes at least two second clock signal lines (for example, two second clock signal lines are shown in fig. 7, which are respectively the fifth sub-line 971 and the sixth sub-line 972), and the timings on the at least two second clock signal lines are the same and are in the same frequency and opposite direction to the overall timing on the first-type clock signal line 960.
With the arrangement, on the premise that the signal time sequence and the effective potential on the second type of clock signal line are the same, by increasing the number of the second clock signal lines, the signal homodromous superposition on each second clock signal line is utilized, the size of the effective potential on the single second clock signal line can be reduced, so that the amplitude of the effective potential on the second clock signal line is equivalent to that of the effective potential on the first clock signal line, and the additional arrangement of a voltage boosting and reducing circuit or a device can be avoided, namely, the second clock signal can be loaded on the second clock signal line only by utilizing the existing integrated circuit module in the display panel, thereby being beneficial to reducing the technical realization difficulty and reducing the electromagnetic interference and ensuring that the overall cost of the display panel is lower.
For example, in fig. 9, the fifth sub-clock signal CKV21 and the sixth sub-clock signal CKV22 are superimposed in the same frequency and direction to form the second clock signal CKV 20. The amplitude of the effective potential of the second clock signal CKV20 is greater than the amplitude of the effective potential of the first sub-clock signal CKV11 and greater than the amplitude of the effective potential of the second sub-clock signal CKV 12; meanwhile, both the amplitude of the effective potential of the fifth sub-clock signal CKV21 and the amplitude of the effective potential of the sixth sub-clock signal CKV22 may be smaller than the amplitude of the effective potential of the second clock signal CKV20, may also be smaller than the amplitude of the effective potential of the first sub-clock signal CKV11, and may also be smaller than the amplitude of the effective potential of the second sub-clock signal CKV 12.
In other embodiments, the number of the second clock signal lines may also be 3, 4 or more, and the number of the second clock signal lines may be greater than the number of the first clock signal lines, and may be set according to actual requirements of the display panel, which is not limited in this embodiment of the present invention.
Hereinafter, the relative positions of the first type clock signal line and the second type clock signal line are exemplarily described taking the shape of the display area as a quadrangle as an example. In other embodiments, the overall shapes of the display area, the non-display area and the display panel may also be set according to actual requirements of the display panel, which is not limited in the embodiments of the present invention.
Optionally, referring to fig. 5 and 10, the display area 920 is a quadrilateral, the quadrilateral includes a first edge 901, a second edge 902, a third edge 903, and a fourth edge 904, which are sequentially connected end to end, and the first type clock signal line 960 is disposed in the non-display area 910 corresponding to the first edge 901 and/or the third edge 903; correspondingly, the second type clock signal line 970 is at least disposed in the non-display area 910 corresponding to the first side 901 and/or the third side 903.
The second type clock signal line 970 is disposed adjacent to the first type clock signal line 960 to achieve the effect of reducing the electromagnetic interference.
Illustratively, referring to fig. 5, when the first type clock signal line 960 is disposed in the non-display region 910 corresponding to the first side 901 and the third side 903, the second type clock signal line 970 is disposed in the non-display region 910 corresponding to the first side 901 and the third side. For example, in an actual product structure of the display panel 90, the non-display area 910 corresponding to the first side 901 and the third side 903 may be a left and right frame area of the display panel 90, and the display panel 90 may implement scanning bilateral driving.
Illustratively, referring to fig. 10, when the first type clock signal line 960 is disposed in the non-display area 910 corresponding to the first edge 901, the second type clock signal line 970 is correspondingly disposed in the non-display area 910 corresponding to the first edge 901. Illustratively, the display panel 90 may implement a single-side scan driving.
In other embodiments, the first type clock signal line 960 and the second type clock signal line 970 may also be disposed in the non-display area 910 corresponding to the third side 903, which is not limited in this embodiment of the present invention.
Optionally, referring to fig. 11 and 12, the second type clock signal line 970 is further disposed in the non-display area 910 corresponding to the second side 902 and/or the fourth side 904.
So set up, through increasing the length of second type clock signal line 970, can realize the energy accumulation of reverse electromagnetic field to under the condition that reverse electromagnetic field's demand intensity is the same, through increasing the length of second type clock signal line 970, can reduce the amplitude of the effective potential on second type clock signal line 970 when improving electromagnetic interference, be favorable to the technological realization degree of difficulty.
For example, in fig. 11 and 12, the non-display area 910 corresponding to the second edge 902 is an upper frame area of the display panel 90, and the second-type clock signal line 970 in the upper frame area is set to be a complete line segment connecting the second-type clock signal lines 970 in the left and right frames, that is, the second-type clock signal line 970 is a single second clock signal line.
In other embodiments, the second type clock signal line 970 may also be configured to be disconnected in the upper frame area, that is, the second type clock signal line 970 includes two second clock signal lines, which may be configured according to actual requirements of the display panel 90, and this is not limited in this embodiment of the present invention.
Optionally, with continued reference to fig. 5 and 12, the second type clock signal line 970 is disposed on a side of the first type clock signal line 960 facing away from the display area 920.
The first clock signal line 960 is electrically connected to the scan driving circuit 950, and the output terminal of the scan driving circuit 950 loads the scan signal to the scan line in the display area 920; the reverse electromagnetic field provided by the second type clock signal line is used for neutralizing the interference electromagnetic field on the first type clock signal line and the scanning line, and the interference electromagnetic field is an electromagnetic field radiated to the periphery by the display panel.
Based on this, in the first aspect, the reverse electromagnetic field can be arranged in the path of the outward radiation of the interference electromagnetic field, thereby being beneficial to reducing the electromagnetic interference; in the second aspect, the first type of clock signal lines connected with the scanning driving circuit are convenient to be closer to the scanning driving circuit, so that the wiring is convenient, the design difficulty of the wiring is small, and the process difficulty is small; in the third aspect, the influence of the reverse electromagnetic field on the signal inside the display area of the display panel can be reduced, thereby being beneficial to ensuring that the display panel has a better display effect.
Alternatively, referring to fig. 13 and 14, each of the second clock signal lines 971 is disposed between two adjacent first clock signal lines of the first-type clock signal lines 960.
Wherein, the closer the second clock signal line 971 is to the single first clock signal line, the stronger the attenuation of the electromagnetic field from the reverse direction is.
Based on this, the above arrangement can make the second clock signal line 971 have a stronger weakening effect on two adjacent first clock signal lines, thereby being beneficial to better reducing electromagnetic interference.
Exemplarily, only two first clock signal lines and one second clock signal line between the two first clock signal lines are exemplarily shown in fig. 13 and 14.
In other embodiments, when the number of the first clock signal lines and the second clock signal lines is more, the second clock signal lines may be disposed between two adjacent first clock signal lines that are the same; or the first clock signal line and the second clock signal line are arranged at intervals, and may be arranged according to the actual requirement of the display panel 90, which is not limited in the embodiment of the present invention.
On the basis of fig. 13, alternatively, referring to fig. 15 and 16, the distance between the second clock signal line 971 and two adjacent first clock signal lines is equal along the direction 100 in which the display area 920 points to the non-display area 910.
With such an arrangement, the electromagnetic field in the second clock signal line 971 can attenuate the interfering electromagnetic fields in the two adjacent first clock signal lines, thereby being beneficial to reducing the electromagnetic interference.
Illustratively, fig. 15 exemplarily shows that the first-type clock signal line 960 includes three first clock signal lines, i.e., a first sub-line 961, a second sub-line 962 and a third sub-line 963, and exemplarily shows that the second clock signal line 971 is located between the second sub-line 962 and the third sub-line 963, a distance between the second clock signal line 971 and the third sub-line 963 is shown as D1, a distance between the second clock signal line 971 and the second sub-line 962 is shown as D2, and D1 is D2.
In other embodiments, the second clock signal line 971 may be disposed between the first sub-line 961 and the second sub-line 962, which is not limited in the embodiments of the present invention.
Illustratively, referring to fig. 16, the first type of clock signal line 960 includes two first clock signal lines, a first sub-line 961 and a second sub-line 962, and the second type of clock signal line 970 includes one second clock signal line 971; a distance D3 between the second clock signal line 971 and the first sub-line 961 is equal to a distance D2 between the second clock signal line 971 and the second sub-line 962 in the direction 100 in which the display area 920 points to the non-display area 910.
First, it should be noted that fig. 15 and 16 only exemplarily show that the direction 100 pointing to the non-display area 910 along the display area 920 is horizontal to the right. In other embodiments, the direction pointing to the non-display area 910 along the display area 920 may also be an upward right-oblique direction, a horizontal left direction, an upward left-oblique direction, a downward left-oblique direction, or other selectable directions, which may be set according to actual requirements of the display panel, and the embodiment of the present invention does not limit this.
Next, it should be noted that, in fig. 15 and 16, the distance between two adjacent clock signal lines is shown with reference to only the center of the width of the clock signal line (including the first clock signal line and the second clock signal line) in the direction 100 in which the display area 920 points to the non-display area 910. In other embodiments, the direction 100 pointing to the non-display area 910 along the display area 920 may also be used, and the adjacent boundaries of two adjacent clock signal lines define the distance between two adjacent clock signal lines as a reference point; or define the distance between two adjacent clock signal lines in other ways known to those skilled in the art, which is not described again nor limited in this embodiment of the present invention.
On this basis, it should be noted that the value of the distance between two adjacent clock signal lines may be set according to actual requirements such as a frame width requirement and a wiring requirement of the display panel, which is not limited in the embodiment of the present invention.
Optionally, with continued reference to fig. 11, 12, or 14, the display panel 90 further includes an integrated circuit module 940, where the integrated circuit module 940 is disposed in the non-display area 910 corresponding to the first edge 901; the input end of the first clock signal line and the input end of the second clock signal line 971 are both electrically connected to the integrated circuit module 940; the second type clock signal line 970 is also disposed in the non-display area 910 corresponding to the fourth edge 904.
The integrated circuit module 940 may be an integrated circuit disposed in a lower frame region of the display panel 90, and the integrated circuit is configured to convert an external signal into a recognizable signal inside the display panel.
For example, if the display panel is applied to a mobile phone, the mobile phone may include a main board (including a driving system) and an Integrated Circuit (IC) connecting the main board and the display panel. Based on this, the IC receives the signal output by the motherboard.
For example, if the display panel is applied to a computer, the computer may include a graphics card and an IC connecting the graphics card and the display panel. Based on this, the IC receives the signal output by the graphics card.
In other embodiments, when the display panel is applied to other display devices (or called electronic devices), the IC obtains an external signal from the overall control system of the display device, and the present invention does not limit the actual product structure form of the overall control system.
On the basis of the above embodiments, an embodiment of the present invention further provides a display device. For example, referring to fig. 17, the display device 70 includes a display panel 90, and the display surface, 90 may be any one of the display panels provided in the foregoing embodiments, so that the display device 70 also has the beneficial effects of the display panel 90 provided in the foregoing embodiments, and the same points can be understood by referring to the foregoing description, and are not described in detail below.
For example, the display device 70 may be a mobile phone, a computer, a smart wearable device (e.g., a smart watch), a vehicle-mounted display screen, a vehicle-mounted touch screen, or other types of display devices known to those skilled in the art, and the embodiments of the invention are not limited thereto. When the display device 70 is applied to a vehicle such as an automobile, a ship, or an airplane to serve as a display screen, it may be a local structure independent from the inherent structure of the vehicle, or may be integrated with other structural components of the vehicle, for example, the display device 70 may be integrated with a front windshield, or may be integrated with a table top around an instrument panel, which is not limited in the embodiments of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (13)
1. A display panel is characterized by comprising a display area and a non-display area surrounding the display area, wherein a scanning driving circuit, a first type clock signal line and a second type clock signal line are arranged in the non-display area, the first type clock signal line is electrically connected to the scanning driving circuit, and the second type clock signal line is arranged in parallel to the first type clock signal line;
the first type of clock signal line comprises at least two first clock signal lines, and the second type of clock signal line comprises at least one second clock signal line; the whole time sequence on the second type clock signal line and at least part of the whole time sequence on the first type clock signal line are in the same frequency and reverse direction;
wherein, the same frequency reversal means that the frequency is the same, and the effective potential is opposite in relative height; the effective potential is set to a non-zero potential.
2. The display panel according to claim 1, wherein the amplitude of the effective potential of the signal on the second type clock signal line is larger than the amplitude of the effective potential of the signal on the first type clock signal line.
3. The display panel according to claim 1, wherein the first type of clock signal line includes two first clock signal lines, and the second type of clock signal line includes one second clock signal line;
the clock signal on the first clock signal line comprises a plurality of continuous first clock segments, and the clock signal on the second clock signal line comprises a plurality of continuous second clock segments; two on the first clock signal line first clock section interval sets up in proper order, the second clock section with first clock section corresponds in proper order, just the effective potential of second clock section with it corresponds the effective potential positive negative phase of first clock section is opposite.
4. The display panel according to claim 1, wherein the number of the second clock signal lines is equal to the number of the first clock signal lines, and the timing on each of the second clock signal lines is set to have a one-to-one correspondence to the timing on one of the first clock signal lines and a same frequency reverse.
5. The display panel according to claim 1, wherein the second type of clock signal line comprises at least two second clock signal lines, and the timings of the at least two second clock signal lines are the same and are in the same frequency and opposite direction to the overall timing of the first type of clock signal lines.
6. The display panel according to claim 1, wherein the display area is a quadrilateral, the quadrilateral comprises a first edge, a second edge, a third edge and a fourth edge which are sequentially connected end to end, and the first type clock signal line is disposed in the non-display area corresponding to the first edge and/or the third edge; correspondingly, the second type of clock signal line is at least arranged in the non-display area corresponding to the first edge and/or the third edge.
7. The display panel according to claim 6, wherein the second type of clock signal line is further disposed in a non-display region corresponding to the second edge and/or the fourth edge.
8. The display panel according to claim 6, wherein the second type clock signal line is disposed on a side of the first type clock signal line facing away from the display area.
9. The display panel according to claim 6, wherein each of the second clock signal lines is disposed between two adjacent first clock signal lines of the first class of clock signal lines.
10. The display panel according to claim 9, wherein a distance between the second clock signal line and two adjacent first clock signal lines is equal in a direction in which the display area points to the non-display area.
11. The display panel according to claim 9, wherein the first type of clock signal line includes two first clock signal lines, a first sub-line and a second sub-line, respectively, and the second type of clock signal line includes one second clock signal line;
and the distance between the second clock signal line and the first sub-line is equal to the distance between the second clock signal line and the second sub-line along the direction of pointing to the non-display area from the display area.
12. The display panel according to claim 6, wherein the display panel further comprises an integrated circuit module disposed in the non-display region corresponding to the first edge;
the input end of the first clock signal line and the input end of the second clock signal line are both electrically connected with the integrated circuit module; the second type of clock signal line is also arranged in the non-display area corresponding to the fourth edge.
13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.
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| CN201911249586.4A CN110930927A (en) | 2019-12-09 | 2019-12-09 | Display panel and display device |
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| CN201911249586.4A CN110930927A (en) | 2019-12-09 | 2019-12-09 | Display panel and display device |
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