CN108469706B

CN108469706B - Display panel

Info

Publication number: CN108469706B
Application number: CN201810203690.9A
Authority: CN
Inventors: 蔡尧钧; 庄铭宏
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-01-19
Filing date: 2018-03-13
Publication date: 2021-07-27
Anticipated expiration: 2038-03-13
Also published as: TW201933309A; CN108469706A; TWI645391B

Abstract

A display panel includes a pixel array and a plurality of gate driving units. The pixel array is arranged in the display area and comprises a plurality of pixel units. The plurality of gate driving units are coupled to the plurality of pixel units along a first direction and are arranged in a non-display area outside the display area, wherein the non-display area comprises a side area positioned on the display panel and a corner area positioned on the display panel, the plurality of gate driving units comprise at least one first gate driving unit arranged in the corner area, and a plurality of second gate driving units arranged in the side area. The at least one first gate driving unit and the second gate driving unit adjacent to the corner region are coupled to each other through the first routing region between the at least one first gate driving unit and the second gate driving unit by a plurality of routing lines, and the spacing distance between the at least one first gate driving unit and the second gate driving unit is N times of the length of a row of pixel units in the pixel array in the second direction, wherein N is at least 1.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a corner arrangement of a display panel.

Background

With the rapid development of display devices, people are using various display devices frequently, and the frequency ratio of the display devices and the aesthetic feeling of display screens are emphasized, and especially, the design of thin frames (slim borders) and the streamlined design of corners of the display devices are pursued further.

Nowadays, in order to realize the design of slim border panels, a Gate On Array (GOA) technique is usually used to integrate a Gate driving circuit on an Array substrate, so as to achieve the design of thin-frame display panels. However, the use of only GOAs on both sides of the display panel can result in right angles at the corners of the panel and still result in a thick bezel.

Therefore, how to further reduce the frame size of the display device, have a higher screen area ratio and have a streamlined corner becomes a big issue today.

Disclosure of Invention

One embodiment of the present invention provides a display panel including a pixel array and a plurality of gate driving units. The pixel array is arranged in the display area and comprises a plurality of pixel units. The plurality of gate driving units are coupled to the plurality of pixel units along a first direction and are arranged in a non-display area outside the display area, wherein the non-display area comprises a side area positioned on the display panel and a corner area positioned on the display panel, the plurality of gate driving units comprise at least one first gate driving unit arranged in the corner area, and a plurality of second gate driving units arranged in the side area. The at least one first gate driving unit and the second gate driving unit adjacent to the corner region are coupled to each other through the first routing region between the at least one first gate driving unit and the second gate driving unit by a plurality of routing lines, and the spacing distance between the at least one first gate driving unit and the second gate driving unit is N times of the length of a row of pixel units in the pixel array in the second direction, wherein N is at least 1.

Through the arrangement mode, the invention can further reduce the frame of the display panel and has streamline design at the corner.

This invention is intended to provide a simplified summary of the invention in order to provide the reader with a basic understanding of the invention, and is not intended to identify key or critical elements of the embodiments or to delineate the scope of the invention.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the invention;

FIG. 2A is a schematic diagram of an edge of a display panel according to an embodiment of the invention;

FIG. 2B is a block diagram of a gate driving unit disposed in a pixel unit of a display panel according to an embodiment of the invention;

FIG. 2C is a schematic circuit diagram of a gate driving unit in a display panel according to an embodiment of the invention;

FIG. 3A is a schematic diagram of an edge of a display panel according to an embodiment of the invention;

FIG. 3B is a block diagram of a gate driving unit disposed in a pixel unit of a display panel according to an embodiment of the invention;

FIG. 3C is a schematic circuit diagram of a gate driving unit in a display panel according to an embodiment of the invention;

FIG. 4A is a schematic diagram of an edge of a display panel according to an embodiment of the invention;

FIG. 4B is a block diagram of a gate driving unit disposed in a pixel unit of a display panel according to an embodiment of the invention;

FIG. 4C is a schematic circuit diagram of a gate driving unit in a display panel according to an embodiment of the invention;

FIG. 5A is a schematic diagram of an edge of a display panel according to an embodiment of the invention;

FIG. 5B is a block diagram of a gate driving unit disposed in a pixel unit of a display panel according to an embodiment of the invention;

FIG. 5C is a schematic circuit diagram of a gate driving unit in a display panel according to an embodiment of the invention; and

fig. 5D is a circuit diagram of a gate driving unit in a display panel according to an embodiment of the invention.

Wherein, the reference numbers:

100: display panel

110: display area

120: non-display area

121: side edge area

122: corner area

230. 330, 331, 340, 341, 430, 530, 531, 540, 541: gate driving unit

S: gate drive signal

250: area without circuit

251: transmission line

350: routing area

351: wiring

160: pixel array

161: pixel unit

X, Y: direction of rotation

h1, h2, h31, h32, h4, h51, h 52: length in Y direction

w1, w 2: length in X direction

U2D, SR [ N-1], SR [ N +1], SR [ N +2], D2U, VGH, GOFF, CK, XDONB, RST, XCK, CK1, CK3, CK 4: voltage of

SR [ N ], SR [ N-1], SR [ N +1 ]: gate drive signal

M1, M2, M3, M4, M5, M7, M8, M9, M10, M13, M14, M15, M10a, M10c, M13a, M13b, M14a, M14b, M15a, M15 b: transistor with a metal gate electrode

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

the following detailed description of the embodiments with reference to the drawings is not intended to limit the scope of the disclosure, but rather to limit the order in which the structures are implemented, and any structures described in this specification which result in a device having equivalent functionality will be capable of being rearranged. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.

The terms "first," "second," …, and the like as used herein do not denote any order or importance, nor are they used to limit the present invention, but rather are used to distinguish one element from another element or operation described in the same technical language.

As used herein, coupled or connected means that two or more elements are in direct or indirect physical or electrical contact with each other, and coupled or connected means that two or more elements are in operation or act on each other.

In the present invention, the plurality of pixel units of the display panel in the corner region are arranged in an arc shape, but not limited thereto. According to different requirements, a plurality of pixel units in the corner region of the display panel have different arrangement modes.

In the present invention, the first direction is an X direction, and the second direction is a Y direction, but the invention is not limited thereto.

Fig. 1 shows a schematic diagram of a display panel 100 according to an embodiment of the invention. As shown in fig. 1, the display panel 100 includes a display area 110 and a non-display area 120, wherein the non-display area 120 may be disposed around or around the display area 110, or located on the upper, lower, left and right sides of the display area 110.

In some embodiments, the display area 110 includes a plurality of pixel units 161, wherein the plurality of pixels are arranged in the display area 110 in rows and columns, i.e., the pixel array 160, wherein the length of the pixel unit 161 in the Y direction is h 1.

In some embodiments, the non-display area 120 is used for disposing one or more driving circuits (e.g., including a Gate On Array (GOA), a SOURCE/Gate driver (SOURCE/GATE DRIVER) and/or a Timing controller (Timing controller) for driving the plurality of pixel units 161 and a plurality of signal transmission lines (not shown) for connecting the plurality of pixel units 161 and the driving circuits.

For example, in some embodiments, the non-display region 120 is provided with a gate driving circuit, which may be disposed on one side or opposite left and right sides of the display region 110. The non-display region 120 may also be provided with a source driver circuit and/or an Integrated Circuit (IC), which may be disposed on the upper side of the display region 110. In some embodiments, the driving method of the display panel 100 of the invention is a double-sided staggered single-drive (such as the driving methods shown in fig. 2B, fig. 3B, fig. 4B, and fig. 5B) in order to reduce the size of the frame and achieve the effect of a thin frame (Slim Border), but not limited thereto, any other driving method, such as a double-sided double-drive, is within the scope of the invention.

As shown in fig. 1, the non-display area 120 includes a side area 121 and a corner area 122, wherein the side area 121 is located at the left and right sides of the display panel 100 or the left and right sides with respect to the display area 110, and the corner area 122 is located at the corner of the display panel 100 or the upper left, lower left, upper right and lower right with respect to the display area 110.

Fig. 2A shows a schematic diagram of an edge of a display panel 100 according to an embodiment of the invention. To describe the arrangement of the elements in the display area 110 and the non-display area 120 in more detail, fig. 2A only shows an enlarged schematic view of the edge area of the display panel 100. For ease of understanding, similar elements of fig. 1 and 2A will be designated with the same reference numerals.

As shown in fig. 2A, the non-display area 120 further includes a circuit-free area 250 in addition to the side area 121 and the corner area 122 shown in fig. 1, wherein the circuit-free area 250 is located between the display area 110 and the side area 121.

In some embodiments, the side region 121 includes a plurality of gate driving units 230, and the circuit-free region 250 includes a plurality of transmission lines 251, wherein the plurality of gate driving units 230 are coupled to the corresponding at least one row of pixel units 161 via the plurality of transmission lines 251 on the circuit-free region 250.

In some embodiments, the gate driving unit 230 is configured to output a gate driving signal S to drive at least one row of pixel units 161 in the pixel array 160. In some embodiments, the gate driving units 230 may be implemented by GOA, but not limited thereto, and any circuit capable of driving the pixel array 160 is within the scope of the invention.

In some embodiments, the plurality of transmission lines 251 are used for transmitting a plurality of gate driving signals S from the gate driving unit 230 to at least one corresponding row of pixel units 161 in the pixel array 160 to control the display frame of the display panel 100. In some embodiments, the transmission line 251 may be implemented by a signal transmission line, but is not limited thereto, and any line capable of transmitting the gate driving signal S is within the scope of the present invention.

In some embodiments, as shown in fig. 2A, each gate driving unit 230 is configured to output a gate driving signal S to drive a row of pixel units 161, and a length h2 of each gate driving unit 230 in the Y direction is smaller than a total length h1 of two rows of pixel units 161 in the Y direction.

Fig. 2B is a schematic circuit block diagram illustrating a configuration of the gate driving unit 230 relative to the pixel unit 161 in the display panel 100 according to an embodiment of the invention. As shown in fig. 2B, the gate driving units 230 are configured to perform a dual-side single-drive driving method, and specifically, the gate driving units 230 on the left side of the pixel array 160 and the gate driving units 230 on the right side of the pixel array 160 alternately transmit the gate driving signal S to the corresponding row of pixel units 161 according to a timing signal to drive the corresponding row of pixel units 161.

Fig. 2C is a schematic circuit diagram of a gate driving unit 230 in the display panel 100 according to an embodiment of the invention. In some embodiments, the circuit configuration and the specific connection relationship of the elements in the gate driving unit 230 are as shown in fig. 2C, wherein the nth stage gate driving unit 230 is configured to generate a corresponding gate driving signal SR [ N ], i.e., the gate driving signal S shown in fig. 2A and 2B, to drive a corresponding row of pixel units 161.

Fig. 3A is a schematic diagram of an edge of a display panel 100 according to an embodiment of the invention. To describe the arrangement of the elements in the display area 110 and the non-display area 120 in more detail, fig. 3A only shows an enlarged schematic view of the edge area of the display panel 100. For ease of understanding, like elements in fig. 3A will be designated with the same reference numerals as fig. 1 and 2A.

In some embodiments, as shown in fig. 3A, the side region 121 includes a plurality of gate driving units 340, and the corner region 122 includes a plurality of gate driving units 330 and a plurality of routing regions 350, wherein the plurality of gate driving units 340, the plurality of gate driving units 330 and the routing regions 350 include a plurality of traces 351.

In some embodiments, as shown in fig. 3A, the plurality of gate driving units 330 and the plurality of gate driving units 340 are respectively coupled to the pixel array 160 along the X direction, the gate driving unit 331 of the plurality of gate driving units 330 adjacent to the side region 121 and the gate driving unit 341 of the plurality of gate driving units 340 adjacent to the corner region 122 are coupled to each other through the plurality of traces 351 in the trace region 350 therebetween, and the adjacent two of the plurality of gate driving units 330 are coupled to each other through the plurality of traces 351 in the trace region 350 therebetween.

In some embodiments, the routing area 350 is configured to allow a plurality of traces 351 to be routed along the layout of the pixel units 161 at the edge of the pixel array 160, so that the plurality of gate driving units 330 are disposed closer to the pixel array 160. In some embodiments, the traces 351 are used to connect the gate driving units 340, the gate driving units 330, and the trace regions 350.

In some embodiments, as shown in fig. 3A, each gate driving unit 330 is configured to output a gate driving signal S to drive a corresponding row of pixel units 161 in the pixel array 160, and each gate driving unit 340 is configured to output a gate driving signal S to drive a corresponding row of pixel units 161 in the pixel array 160. In some embodiments, the length h31 of the gate driving unit 330 in the Y direction is the length h1 of one row of pixel units 161 in the Y direction, the length h32 of the gate driving unit 340 in the Y direction is the total length 2h1 of two rows of pixel units 161 in the Y direction, and the length h33 of the routing area 350 in the Y direction is the length h1 of one row of pixel units 161 in the Y direction, but the invention is not limited thereto, and the length h33 of the routing area 350 in the Y direction is an integral multiple of the length h1 of one row of pixel units 161 in the Y direction.

In some embodiments, as shown in fig. 3A, the length w1 of the gate driving unit 330 in the X direction is longer than the length w2 of the gate driving unit 340 in the X direction, because the layout area of the gate driving unit 330 is the same as that of the gate driving unit 340, the length w2 of the gate driving unit 330 in the X direction is greater than the length w1 by compressing the total length 2h1 of the two columns of pixel units 161 in the Y direction to the length h1 of the one column of pixel units 161 in the Y direction.

Fig. 3B is a schematic circuit block diagram illustrating the arrangement of the

gate driving units

330 and 340 relative to the pixel unit 161 in the display panel 100 according to an embodiment of the invention. As shown in fig. 3B, the

gate driving units

330 and 340 are configured to perform a dual-side single-drive driving method, and specifically, the gate driving units 330 on the left side of the pixel array 160 and the gate driving units 330 on the right side of the pixel array 160 alternately transmit the gate driving signals S to a corresponding row of pixel units 161 according to a timing signal, and after all the gate driving units 330 transmit the gate driving signals S, the gate driving units 340 on the left side of the pixel array 160 and the gate driving units 340 on the right side of the pixel array 160 sequentially transmit the gate driving signals S to the corresponding row of pixel units 161 in turn.

Fig. 3C shows a circuit diagram of the gate driving unit 330 and the gate driving unit 340 in the display panel 100 according to an embodiment of the invention. In some embodiments, the circuit configuration and the specific connection relationship of the elements in the

gate driving units

330 and 340 are as shown in fig. 3C, wherein the nth stage gate driving unit 330 or the nth stage gate driving unit 340 is configured to generate the corresponding gate driving signal SR [ N ], i.e., the gate driving signal S shown in fig. 3A and 3B, to drive the corresponding row of pixel units 161.

Fig. 4A is a schematic diagram of an edge of a display panel 100 according to an embodiment of the invention. To explain the arrangement of the elements in the display area 110 and the non-display area 120 in more detail, fig. 4A only shows an enlarged schematic view of the edge area of the display panel 100. For ease of understanding, similar elements in fig. 4A will be designated with the same reference numerals as fig. 1, 2A and 3A.

In some embodiments, as shown in fig. 4A, the side region 121 and the corner region 122 each include a plurality of gate driving units 430 and a plurality of routing regions 350, wherein the plurality of gate driving units 430 and the routing regions 350 each include a plurality of traces 351.

In some embodiments, as shown in fig. 4A, a plurality of gate driving units 430 are respectively coupled to the pixel array 160 along the X direction, and two adjacent gate driving units 430 are coupled to each other via a plurality of traces 351 in the trace region 350 therebetween.

In some embodiments, the gate driving unit 430 shown in fig. 4A is a common (Co-used) circuit, but is not limited thereto, and any other circuit capable of reducing the height of a single-stage circuit is within the scope of the present invention.

In some embodiments, as shown in fig. 4A, the traces 351 are used to connect the gate driving units 430 and the trace regions 350.

In some embodiments, each gate driving unit 430 is configured to output two gate driving signals S to drive two corresponding columns of pixel units 161 in the pixel array 160. In some embodiments, the length h4 of the gate driving unit 430 in the Y direction is equal to the total length 3h1 of the three columns of pixel units 161 in the Y direction.

Fig. 4B is a schematic circuit block diagram illustrating a configuration of the gate driving unit 430 relative to the pixel unit 161 in the display panel 100 according to an embodiment of the invention. As shown in fig. 4B, the gate driving units 430 are configured to perform a dual-side single-drive driving method, and specifically, the gate driving units 430 located at the left side of the pixel array 160 and the gate driving units 430 located at the right side of the pixel array 160 alternately transmit the gate driving signals S to the two corresponding rows of pixel units 161 according to a timing signal.

Fig. 4C is a circuit diagram of a gate driving unit 430 in the display panel 100 according to an embodiment of the invention. In some embodiments, the circuit configuration and the specific connection relationship of the elements in the gate driving unit 430 are as shown in fig. 4C, wherein the nth stage gate driving unit 430 is configured to generate the corresponding gate driving signal SR [ N ] and the gate driving signal SR [ N +2], i.e., the two gate driving signals S shown in fig. 4A and 4B, to drive the two rows of pixel units 161.

Fig. 5A is a schematic diagram of an edge of a display panel 100 according to an embodiment of the invention. To describe the arrangement of the elements in the display area 110 and the non-display area 120 in more detail, fig. 5A only shows an enlarged schematic view of the edge area of the display panel 100. For ease of understanding, similar elements in fig. 5A will be designated with the same reference numerals as fig. 1, 2A and 3A.

In some embodiments, as shown in fig. 5A, the side region 121 includes a plurality of gate driving units 540, the corner region 122 includes a plurality of gate driving units 530 and a plurality of routing regions 350, wherein the plurality of gate driving units 540, the plurality of gate driving units 530 and the plurality of routing regions 350 include a plurality of routing lines 351.

In some embodiments, as shown in fig. 5A, the plurality of gate driving units 530 and the plurality of gate driving units 540 are coupled to the pixel array 160 along the X direction, the gate driving units 531 adjacent to the side region 121 in the plurality of gate driving units 530 and the gate driving units 541 adjacent to the corner region 122 in the plurality of gate driving units 540 are coupled to each other via the plurality of traces 351 in the trace region 350 therebetween, and the adjacent two in the plurality of gate driving units 530 are coupled to each other via the plurality of traces 351 in the trace region 350 therebetween.

In some embodiments, the gate driving unit 530 shown in fig. 5A is a common (Co-used) circuit, but is not limited thereto, and any other circuit capable of reducing the height of a single-stage circuit is within the scope of the present invention.

In some embodiments, as shown in fig. 5A, the traces 351 are used to connect the gate driving units 540, the gate driving units 530 and the trace regions 350.

In some embodiments, as shown in fig. 5A, each gate driving unit 530 is configured to output two gate driving signals S for driving two corresponding columns of pixel units 161 in the pixel array 160, and each gate driving unit 540 is configured to output one gate driving signal S for driving two corresponding columns of pixel units 161 in the pixel array 160. In some embodiments, the length h51 of the gate driving unit 530 in the Y direction is equal to the total length 3h1 of the three rows of pixel units 161 in the Y direction, and the length h52 of the gate driving unit 540 in the Y direction is equal to the total length 2h1 of the two rows of pixel units 161 in the Y direction.

Fig. 5B is a schematic circuit block diagram illustrating the arrangement of the

gate driving units

530 and 540 in relation to the pixel unit 161 in the display panel 100 according to an embodiment of the invention. As shown in fig. 5B, the

gate driving units

530 and 540 are configured to perform a dual-side single-drive driving method, and specifically, the gate driving units 530 on the left side of the pixel array 160 and the gate driving units 530 on the right side of the pixel array 160 alternately transmit the gate driving signals S to the two corresponding rows of pixel units 161 according to a timing signal, and after all the gate driving units 530 transmit the gate driving signals S, the gate driving units 540 on the left side of the pixel array 160 and the gate driving units 540 on the right side of the pixel array 160 sequentially transmit the gate driving signals S to the two corresponding rows of pixel units 161 in turn.

Fig. 5C is a circuit diagram of a gate driving unit 530 in the display panel 100 according to an embodiment of the invention. In some embodiments, the circuit configuration and the specific connection relationship of the elements in the gate driving unit 530 are as shown in fig. 5C, wherein the nth stage gate driving unit 530 is configured to generate the corresponding gate driving signal SR [ N ] and the gate driving signal SR [ N +2], i.e., the two gate driving signals S shown in fig. 5A and 5B, to drive the two rows of pixel units 161.

Fig. 5D is a circuit diagram of a gate driving unit 540 in the display panel 100 according to an embodiment of the invention. In some embodiments, the circuit configuration and the specific connection relationship of the elements in the gate driving unit 540 are as shown in fig. 5D, wherein the nth stage gate driving unit 540 is configured to generate a corresponding gate driving signal SR [ N ], i.e., the gate driving signal S shown in fig. 5A and 5B, to drive a corresponding row of pixel units 161.

In summary, the lengths h2, h31, h32, h4, h51, and h52 of each

gate driving unit

230, 330, 340, 430, 530, and 540 in the Y direction are reduced, and the adjacent two are connected by the plurality of wires 351, so as to further increase the screen ratio of the display panel 100, and the corner region 122 has a streamlined bending design.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display panel, comprising:

the pixel array is arranged in a display area and comprises a plurality of pixel units; and

a plurality of gate driving units coupled to the pixel units along a first direction and disposed in a non-display region outside the display region, wherein the non-display region includes a side region located on the display panel and a corner region located on the display panel, at least one first gate driving unit of the gate driving units is disposed in the corner region, and a plurality of second gate driving units of the gate driving units are disposed in the side region;

wherein a second gate driving unit adjacent to the corner region among the at least one first gate driving unit and the plurality of second gate driving units is coupled to each other through a first routing region therebetween by a plurality of routing lines, wherein a spacing interval between the at least one first gate driving unit and the second gate driving unit adjacent to the corner region is N times a length of a row of pixel units in the pixel array in a second direction, and N is at least 1; and is

The length of the at least one first gate driving unit adjacent to the second gate driving unit in the corner region in the second direction is the length of a row of pixel units in the pixel array in the second direction; the length of each of the second gate driving units in the second direction is equal to the length of a plurality of rows of pixel units in the pixel array in the second direction.

2. The display panel of claim 1, wherein the at least one first gate driving unit is configured to output a gate driving signal for driving a corresponding row of pixel cells in the pixel array, and wherein each of the plurality of second gate driving units is configured to output a gate driving signal for driving a corresponding row of pixel cells in a plurality of rows of pixel cells in the pixel array.

3. The display panel of claim 1, wherein the length of the at least one first gate driving unit in the second direction is equal to the length of a plurality of rows of pixel cells in the pixel array in the second direction.

4. The display panel according to claim 3, wherein the length of each of the second gate driving units in the second direction is equal to the length of a plurality of rows of pixel units in the pixel array in the second direction.

5. The display panel according to claim 4, wherein the at least one first gate driving unit is configured to output a plurality of gate driving signals for driving a plurality of rows of corresponding pixel cells in the plurality of rows of pixel cells in the pixel array, and each of the plurality of second gate driving units is configured to output at least one gate driving signal for driving at least one row of corresponding pixel cells in the plurality of rows of pixel cells in the pixel array.

6. The display panel of claim 1, wherein the gate driving units comprise a plurality of first gate driving units disposed in the corner region, and two adjacent first gate driving units of the first gate driving units are coupled to each other through a second routing region therebetween by the routing lines.

7. The display panel of claim 6, wherein two adjacent first gate driving units of the first gate driving units are spaced apart from each other by a distance equal to a length of a row of pixel units in the pixel array in the second direction.

8. The display panel of claim 1, wherein at least one of the pixel units adjacent to the corner region is irregularly arranged.