CN101779227A - Display panel and display - Google Patents
Display panel and display Download PDFInfo
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- CN101779227A CN101779227A CN200880102824A CN200880102824A CN101779227A CN 101779227 A CN101779227 A CN 101779227A CN 200880102824 A CN200880102824 A CN 200880102824A CN 200880102824 A CN200880102824 A CN 200880102824A CN 101779227 A CN101779227 A CN 101779227A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
In a display panel (1), an active element has an active matrix type pixel region (AR1) employing a three terminal element and the pixel region (AR1) has a nonrectangular shape because the number of the three terminal elements connected with each scanning signal line (GL) of the pixel region (AR1) is determined arbitrarily depending on the position where each scanning signal line (GL) is provided. A shift register (4) for driving the scanning signal line (GL) is formed in a region adjacent to the extending direction of the scanning signal line (GL) in the pixel region (AR1) for the pixel region (AR1) on a panel substrate. Consequently, a display panel with the nonrectangular pixel region of odd-shape in which the routing region of peripheral wiring can be reduced on the outside of the pixel region is attained.
Description
Technical field
The present invention relates to the special-shaped display panel of non-rectangle, particularly relate to the driving of scan signal line.
Background technology
Consider especially to be equipped on portable equipment, proposed to make display part to become the circle different, oval-shaped special-shaped display panels (for example patent documentation 1) with rectangle (quadrilateral).
Fig. 9 represents the vertical view of the special-shaped display panels of patent documentation 1 record.
The figure shows the structure on the 1st light-transmitting substrate 111 that becomes the side in 2 adhesive base plates that constitute display panels.Viewing area DA is oval.Light-transmitting substrate 111 is according to the shape of viewing area DA, forms the cut polygon in bight of rectangular substrate, and cut bight becomes the space that is provided with of other component parts when being assembled into mobile phone etc.Enclosing on the face of liquid crystal by the rectangular multi-strip scanning line X that sets
1..., X
nAnd signal wire Y
1..., Y
mSweep trace X
1..., Xn is connecting a side 111 of substrate on the DA of viewing area
1With with this side 111
1A relative side 111
2The 1st direction on extend.Signal wire Y
1..., Y
mOn the DA of viewing area, connecting a side 111 of substrate
3With with this side 111
3A relative side 111
4The 2nd direction on extend.The 1st direction and the 2nd direction are mutually orthogonal.
At a side 111
4Be formed with the driver mounting zone 121 of mounting driver LSI, driver LSI and above-mentioned sweep trace X
1..., X
nWith signal wire Y
1..., Y
mConnect and the output control signal above-mentioned sweep trace X
1..., X
nWith signal wire Y1 ..., Y
mBe directed into this driver mounting zone 121 outward via viewing area DA.The 1st light-transmitting substrate 111 forms array base palte in this way.
Each pixel of viewing area DA is the existing structure that possesses pixel electrode, auxiliary capacitance electrode, pixel transistor, opposite electrode and color filter etc., and the number of the pixel transistor that is connected with sweep trace is represented the pixel count that is connected with this sweep trace.
Patent documentation 1: Japanese publication communique " spy open 2006-276360 communique (open day: on October 12nd, 2006) "
Patent documentation 2: Japanese publication communique " spy open 2002-258819 communique (open day: on September 11st, 2002) "
Summary of the invention
The problem that invention will solve
But in above-mentioned existing special-shaped display panels, the bight of rectangular substrate is cut off, and therefore need be provided with from driver mounting zone 121 on the narrow zone between viewing area DA and the section and be connected to sweep trace X
1..., the distribution of Xn.The quantity of this distribution is corresponding with the resolution of viewing area DA, is to be 480 so big quantity under the situation of VGA at the panel resolution for example.Even on above-mentioned the 1st direction by odd-numbered line and even number line boot scan line X the other way around on the contrary mutually
1..., Xn, still respectively having nearly at above-mentioned narrow zone, 240 distribution passes through.Therefore, the problem of peripheral distribution can appear being very difficult to be provided with in special-shaped display panels.
The present invention finishes in view of above-mentioned problem in the past, and its purpose is to realize a kind of display panel and display device of the special-shaped pixel region that possesses non-rectangle of the cabling zone that can reduce the outer peripheral distribution of pixel region.
In order to solve above-mentioned problem, display panel of the present invention, possess and adopt the pixel region of 3 terminal components as the active array type of active component, and the number of above-mentioned 3 terminal components that are connected with each scan signal line of above-mentioned pixel region is the position to be set and the number of arbitrary decision according to each said scanning signals line, make above-mentioned pixel region become the shape of non-rectangle thus, it is characterized in that: the shift register that drives the said scanning signals line be formed on the display panel substrate on the direction that the said scanning signals line extends in above-mentioned pixel region with above-mentioned pixel region adjacent areas in.
According to foregoing invention, in pixel region, the number of 3 terminal components that are connected with each scan signal line of pixel region is the position to be set and the number of arbitrary decision according to each scan signal line, make pixel region become the shape of non-rectangle thus, and the shift register of driven sweep signal wire be formed on the display panel substrate on the direction that scan signal line extends in pixel region with the pixel region adjacent areas in.Therefore, do not need that the location guide beyond the adjacent areas is outside pixel region on the direction of extending pixel region with shared driver of data signal line etc. and scan signal line with scan signal line, and the distribution that only needs will to offer several degree of shift register from this other position is directed to shift register and gets final product.
According to above situation, has following effect: the display panel that can realize to reduce the special-shaped pixel region cabling zone, that possess non-rectangle of the outer peripheral distribution of pixel region.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: arrange the peripheral parts along adjacent above-mentioned pixel region at different levels of above-mentioned shift register, and the periphery of the above-mentioned display panel substrate of the part adjacent with above-mentioned shift register presents the shape of bending direction of the above-mentioned peripheral part of the above-mentioned pixel region that has reflected the above-mentioned periphery of being positioned at of above-mentioned display panel substrate inboard.
According to foregoing invention, have following effect: the zone that is formed with shift register only accounts for required minimal area, thereby can make correspondingly miniaturization of display panel, can be installed in the equipment of the special-shaped feature of performance.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: comprise a plurality of level with following relation in the above-mentioned shift register: each level structure is according to the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line, set above-mentioned 3 terminal components between the off period at least one side's from the transition stage of conduction period between the off period of the transition stage of conduction period and above-mentioned 3 terminal components output impedance.
According to foregoing invention, have following effect: pixel region is the abnormity of non-rectangle, even the size that postpones of the distribution of scan signal line is different each other at scan signal line thus, the distribution delay that the output impedance of each level structure that also can be by setting shift register makes the integral body under level and the state that scan signal line is connected is in the scan signal line unanimity that becomes each other.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: comprise a plurality of level with following relation in the above-mentioned shift register: each level structure is according to the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line, the output impedance of at least one side in setting between off period of conduction period of above-mentioned 3 terminal components and above-mentioned 3 terminal components.
According to foregoing invention, have following effect: the output impedance of the level of the conduction period of 3 terminal components can inherit 3 terminal components between the off period to the transition stage of conduction period, and between the off period of 3 terminal components the level output impedance can inherit 3 terminal components from the transition stage of conduction period between the off period, therefore during the output impedance of at least one side between the off period of the conduction period of setting 3 terminal components according to the number of 3 terminal components that connect with corresponding scan signal line and 3 terminal components, the distribution delay that can make the integral body under level and the state that scan signal line is connected is in the scan signal line unanimity that becomes each other.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: comprise the above-mentioned a plurality of above-mentioned level with above-mentioned relation in the above-mentioned level except that elementary and final level of above-mentioned shift register.
According to foregoing invention, have following effect: pixel region is the abnormity of non-rectangle, even the size of the distribution of scan signal line delay is different each other at scan signal line thus, the output impedance of each level structure that also can be by setting shift register, the distribution delay that makes the integral body under level and the state that scan signal line is connected is in the scan signal line unanimity that becomes each other.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: the assigned position of above-mentioned each level structure in level in the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register possesses following the 1st transistor: the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line is many more, the described the 1st transistorized channel width is big more, so that above-mentioned output impedance reduces.
According to foregoing invention, has following effect: postpone bigger scan signal line for distribution, increase the output impedance that the 1st transistorized channel width reduces level structure.Therefore, the distribution delay that can make the integral body under level and the state that scan signal line is connected is in the scan signal line unanimity that becomes each other.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: the assigned position of above-mentioned each level structure in level in the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register possesses following the 1st transistor: the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line is many more, the described the 1st transistorized channel length is more little, so that above-mentioned output impedance reduces.
According to foregoing invention, has following effect: postpone bigger scan signal line for distribution, reduce the output impedance that the 1st transistorized channel length reduces level structure.Therefore, the distribution delay that can make the integral body under level and the state that scan signal line is connected is in the scan signal line unanimity that becomes each other.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: above-mentioned each level structure of above-mentioned shift register is to comprise as above-mentioned the 1st transistor and the transistorized structure that is provided with at the efferent to the said scanning signals line output scanning signal of correspondence.
According to foregoing invention, have following effect: the 1st transistor is arranged on the transistor of efferent of the level of shift register, therefore can easily set output impedance.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: above-mentioned efferent possess the high side that generates sweep signal voltage pull-up unit and generate the drop-down unit of voltage of the downside of sweep signal, above-mentioned the 1st transistor is the transistor as above-mentioned pull-up unit.
According to foregoing invention, have following effect: the 1st transistor is arranged on the transistor as pull-up unit of efferent of the level of shift register, therefore can easily set output impedance.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: above-mentioned efferent possess the high side that generates sweep signal voltage pull-up unit and generate the drop-down unit of voltage of the downside of sweep signal, above-mentioned the 1st transistor is the transistor as above-mentioned drop-down unit.
According to foregoing invention, have following effect: the 1st transistor is arranged on the transistor as pull-up unit that the efferent of the level of shift register is provided with, and therefore can easily set output impedance.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: the assigned position of above-mentioned each level structure in level in the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register possesses following the 1st capacity cell: the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line is many more, the capacitance of described the 1st capacity cell is big more, so that above-mentioned output impedance reduces.
According to foregoing invention, have following effect: postpone bigger scan signal line for distribution, the capacitance that increases the 1st capacity cell reduces the output impedance of level structure.Therefore, the distribution delay that can make the integral body under level and the state that scan signal line is connected is in the scan signal line unanimity that becomes each other.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: in above-mentioned each level structure of above-mentioned shift register, along with the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line increases, the channel width of all crystals pipe that comprises in above-mentioned each level structure is identical or increase.
According to foregoing invention, has following effect: can easily set output impedance.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: in above-mentioned each level structure of above-mentioned shift register, along with the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line increases, the capacitance of all capacity cells that comprise in above-mentioned each level structure is identical or increase.
According to foregoing invention, has following effect: can easily set output impedance.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: the falling waveform from high to low of sweep signal is step-like.
According to foregoing invention, has following effect: can eliminate and on identical scan signal line, produce the distribution that distribution postpones.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: the asserts signal of input is corresponding respectively with each grade and generate respectively to the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register.
According to foregoing invention, has following effect: can set asserts signal according to output impedance at different levels, shift register is stably worked.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: be display panels.
According to foregoing invention, has following effect: in the display panel of the special-shaped pixel region that possesses non-rectangle, can reduce the cabling zone of the outer peripheral distribution of pixel region.
In order to solve above-mentioned problem, display panel of the present invention is characterised in that: possess above-mentioned display panel.
According to foregoing invention, has following effect: possess the less display panel in cabling zone of the outer peripheral distribution of pixel region, therefore can realize that the zone that will dwindle is used for the compact display apparatus of other purposes of device.
Fully understand other purpose, the feature and advantage of invention by the following record meeting that illustrates.In addition, can understand advantage of the present invention with reference to accompanying drawing by following explanation.
Description of drawings
Fig. 1 represents embodiments of the present invention, is the vertical view of the structure of expression display device.
Fig. 2 is the circuit diagram with the structure of the pixel that display device possessed of equivalent electrical circuit presentation graphs 1.
Fig. 3 is the circuit block diagram of level (stage) structure of the shift register that display device possessed of presentation graphs 1.
Fig. 4 is the block diagram of structure example of the shift register that display device possessed of presentation graphs 1.
Fig. 5 is the circuit diagram of level structure example of the shift register of presentation graphs 4.
Fig. 6 is the oscillogram of the adhesive phenomenon of pixels illustrated, and (a) distribution of expression sweep signal postpones the pick-up voltage under the less situation, and (b) distribution of expression sweep signal postpones the pick-up voltage under the bigger situation.
Fig. 7 is the oscillogram of sweep signal waveform of the shift register that display device the possessed output of presentation graphs 1, (a) represents common waveform, (b) waveform of the step-like decline of expression.
Fig. 8 is the vertical view of shape example of the special-shaped pixel region of expression non-rectangle, (a) represents each shape example to (f).
Fig. 9 is the vertical view of the structure of the existing display device of expression.
Description of reference numerals:
1: liquid crystal indicator; 4: shift register; AR1: pixel region; S: level.
Embodiment
According to the following explanation an embodiment of the invention of Fig. 1 to Fig. 8.
Fig. 1 represents the structure of the display panels (display panel) 1 of present embodiment.
Be divided into pixel region AR1 and outer regions AR2 on the TFT substrate 2.Pixel region AR1 is by the rectangular pixel PIX that is provided with ... the zone, integral body is oval.Pixel PIX ... in also can comprise obsolete pixel in the actual displayed, pixel region AR1 is not must be corresponding with the panel open area when display panels 1 is assembled into display device.Obsolete pixel PIX usually is configured under the light shielding part as dummy pixel etc. in the actual displayed.Outer regions AR2 is positioned at around the pixel region AR1, possesses driver 3, shift register 4, scan signal line GL ..., data signal line SL ... and distribution group 5.
Shift register 4 is arranged among the outer regions AR2 in side's side adjacent areas with the short-axis direction of pixel region AR1 in the mode on the TFT substrate 2 of being produced on amorphous silicon or many silicon.This shift register 4 possesses a plurality of level Ss corresponding with each scan signal line GL, the timing of the clock signal that utilization is received by distribution group 5, the grid start dialing signal is shifted to another distolateral level from a distolateral level, and to each scan signal line output sequential scanning signal.
In Fig. 1, shift register 4 for example possesses S from the side near driver 3
1～S
2n2n the level S ...These grades S ... arrange peripheral part along adjacent pixel region AR1.Distribution group 5 is along level S ... arrangement and be configured near the shift register 4.In addition, the periphery of the TFT substrate 2 of the part adjacent with shift register 4 presents the shape of bending direction of the peripheral part of the pixel region AR1 that is in this periphery inboard that has reflected TFT substrate 2, is crooked akin shape with the peripheral part of broken line and pixel region AR1 at this as polygonal limit.In addition, though not shown, the periphery of TFT substrate 2 (display panel substrate) can be the such arbitrary shapes such as periphery of Fig. 9.
Scan signal line GL ... be the distribution that sweep signal is provided to pixel PIX, be configured on the short-axis direction of pixel region AR1, extend.At this scan signal line GL ... number be the 2n that equates with the progression of shift register 4.Data signal line SL ... be the distribution that data-signal is provided to pixel PIX, be configured on the long axis direction of pixel region AR2, extend.
The structure of Fig. 2 remarked pixel PIX.
Pixel PIX is and corresponding setting of cross part of scan signal line GL and data signal line SL, possesses TFT11, liquid crystal capacitance CL and auxiliary capacitor Ccs.The grid of TFT11 (G) is connected with scan signal line GL, and source electrode (S) is connected with data signal line SL, and drain electrode (D) is connected with pixel electrode 12.Liquid crystal capacitance CL is formed in pixel electrode 12 and keeps electric capacity between the opposite electrode 13 of relative voltage Vcom, and auxiliary capacitor Ccs is formed in pixel electrode 12 and applies electric capacity between the electrode 14 of auxiliary capacitor voltage such as relative voltage Vcom.In addition, also there is the stray capacitance Cgd that is formed between pixel electrode 12 and the scan signal line GL on the pixel PIX.
TFT11 is 3 terminal components as active component in the pixel of active array type.TFT11 becomes conducting state applying under the situation that makes the sweep signal during pixel PIX is in selection to grid by scan signal line GL, becomes cut-off state applying under the situation that makes the sweep signal during pixel PIX is in non-selection to grid by scan signal line GL.In the conduction period of TFT11, provide data-signal from the source electrode and the drain electrode of data signal line SL by TFT11 to pixel PIX, between the off period of TFT11, the state that the data-signal that pixel PIX provided during keeping selected last time is written into.
From the structure of above-mentioned pixel PIX as can be known, be respectively equipped with a TFT11 among each pixel PIX, be connected with the TFT11 of the quantity corresponding on each scan signal line GL with its length in pixel region AR1 ...At this, pixel region AR1 is oval, and therefore the number of the TFT that is connected near the scan signal line GL of minor axis is many more.Like this, in the display panel of the special-shaped pixel region that possesses non-rectangle (quadrilateral), each scan signal line GL is connected with the TFT that the corresponding number in position is set with scan signal line GL.
In the present embodiment, as mentioned above, driven sweep signal wire GL ... shift register 4 be formed on the TFT substrate 2 at scan signal line GL ... on the direction of in pixel region AR1, extending among the outer regions AR2 adjacent with pixel region AR1.Therefore, do not need scan signal line GL ... from with data signal line SL ... shared driver 3 grades are at scan signal line GL ... on the direction of extending with pixel region AR1 adjacent areas beyond location guide to pixel region AR1 outside, but only the need distribution that will offer several degree of shift register 4 from this other position is directed to shift register 4 and gets final product.
According to above situation, can realize to reduce the display panel of the special-shaped pixel region cabling zone, that possess non-rectangle of the outer peripheral distribution of pixel region.
Below, Fig. 3 represents k level S of shift register 4
k(the structure of 2≤k≤2n-1).Wherein, elementary level S
1And the level S of final level
2nBe the structure that makes the malformation of Fig. 3, this is and identical in the past method.
Level S
kDraw on possessing/drop-down control part 20, on draw portion's (pull-up unit) 21 and pull-down section (drop-down unit) 22.
On draw/drop-down control part 20 will export control signal ctl and output to and draw portion 21 and pull-down section 22.On draw portion 21 and pull-down section 22 to constitute to scan signal line GL output scanning signal efferent.With level S
kDuring the non-selection of the pixel PIX that connects, output control signal ctl indication is to the grid voltage of scan signal line GL output low (Low), the voltage Vgl of the downside of the sweep signal that pull-down section 22 provides from distribution group 5 to scan signal line GL output.Level S
kUtilize according to the timing of the clock signal C K that provides from distribution group 5 movable signal, generate the used asserts signal Set of trigger at the corresponding levels from the specified quantity of the level S output of prime.As the back was illustrated, this was corresponding with the situation of setting output impedance at different levels by each grade, and is corresponding with each grade and generate asserts signal Set.Its concrete structure can be realized by the existing structure that utilizes logical circuit, on-off element.About elementary level S
1Level S with final level
2n, with level S
kSimilarly set under the situation of output impedance, also can be as mentioned above according to output impedance and level corresponding generation asserts signal Set separately, not with level S
kSimilarly set under the situation of output impedance, with level S
kSeparately, get final product with the independent corresponding generation asserts signal Set of level.According to the generating structure of above asserts signal Set, shift register is stably worked.
Level S
kUtilize this asserts signal Set to generate the shift signal and the output control signal ctl of level output backward.Output control signal ctl indication is to the grid voltage of scan signal line GL output high (High), on draw the voltage Vgh of the high side of the sweep signal that portion 21 provides from power circuit to scan signal line GL output.Thus, with level S
kBegin during the selection of the pixel PIX that connects.After this, when from after the specified signal of specified quantity of level S output of level be input to a grade S as reset signal Reset
kThe time, output control signal ctl indication to scan signal line GL output voltage V gl, finishes during the selection of pixel PIX from pull-down section 22 to the low grid voltage of scan signal line GL output.In addition, reset signal Reset is optional.
In addition, the signal system among Fig. 3 is an example, can be arbitrarily.
In Fig. 3, on draw portion 21 and pull-down section 22 to constitute by n channel-type TFT respectively.On draw the drain electrode of the TFT of portion 21 to be connected with the power supply of voltage Vgh, on draw the source electrode of the TFT of portion 22 to be connected with the power supply of voltage Vgl.The power supply of voltage Vgh also can be the power supply of clock signal.On draw the source electrode of portion 21 and the drain electrode of pull-down section 22 to interconnect, its tie point is connected with scan signal line GL.In this case, ctl indicates when scan signal line GL exports high grid voltage when the output control signal, and making the TFT that draws portion 21 is that conducting state and the TFT that makes pull-down section 22 are cut-off state.In addition, ctl indicates when scan signal line GL exports low grid voltage when the output control signal, and making the TFT that draws portion 21 is that cut-off state and the TFT that makes pull-down section 22 are conducting state.
As the concrete structure of shift register 4, for example shown in Figure 4, can adopt the structure shown in Figure 6 of patent documentation 2.
In Fig. 4, level SRC
1～SRC
193S at different levels with shift register 4 are suitable respectively.In addition, clock signal C K, CKB and suitable through distribution group 5 to the mutual anti-phase clock signal that shift register 4 provides from driver 3.Commencing signal ST is with suitable to the start dialing signal that shift register 4 provides through distribution group 5 from driver 3.The output signal OUT of level
1, OUT
2... output to the scan signal line GL that is connected.
In addition, for example shown in Figure 5 as the structure at different levels of the shift register of Fig. 4, can adopt the structure shown in Figure 7 of patent documentation 2.Pull-up unit 180 with above-mentioned on draw portion 21 suitable, drop-down unit 182 is suitable with above-mentioned pull-down section 22.Beyond the pull-up unit 180 of Fig. 5 and the drop-down unit 182 part with above-mentioned on draw/drop-down unit controls portion 20 is suitable.In addition, the capacitor C of Fig. 5 is a bootstrap capacitor, is input as at source electrode under the situation of AC effectively.When the last current potential that draws the drain electrode of portion 21 changed, through bootstrap capacitor C, grid potential can change.From between the off period when conduction period changes, grid potential can uprise.The big more then grid potential of electric capacity is big more, so output impedance diminishes.
At this, the influence that the special-shaped shape that the regional AR1 of pixels illustrated presents non-rectangle is brought display quality.From the waveform of the sweep signal of the S at different levels output of shift register 4 near situation by high and the low desirable rect.p. that forms under, shown in the dotted line of Fig. 6 (a), sweep signal descends precipitously.At this moment, the TFT11 of pixel PIX shifts to cut-off state from conducting state, promptly between the off period, change from conduction period, but, as shown in Figure 2, in pixel PIX, between pixel electrode 12 and scan signal line GL, there is stray capacitance Cgd, therefore can be created in the so-called adhesive phenomenon (pull-in effect) that front and back pixel electrode current potential changes of ending of TFT11.
When representing the change amount of pixel electrode current potential of this moment with pick-up voltage Δ V, the pixel electrode current potential becomes after the ending of TFT11 from by the value that has preceding reduced Δ V.Fig. 6 (a) represents this situation with solid line.Scan signal line GL is long more in pixel region AR1, and the distribution that summation caused of the grid capacitance of the TFT11 that the wiring resistance of scan signal line GL and distribution electric capacity are connected with scan signal line GL postpones big more.Therefore, the number of the TFT11 that is connected with the roughly proportional scan signal line GL of the length of scan signal line GL is represented the size that the distribution of this scan signal line GL postpones.If distribution postpones big, then sweep signal becomes the waveform of the passivation significantly that descends shown in Fig. 6 (b).At this moment, compare with Fig. 6 (a), pick-up voltage Δ V diminishes along with the increase of distribution delay.Therefore, in image-region AR1, can distribute in the generation face on the pixel electrode current potential for equalized data signal, display quality can reduce.
Therefore, in the present embodiment,,, decide the structure of the S at different levels of shift register 4 promptly according to the size of distribution delay according to the number of the TFT11 that is connected with scan signal line GL.Each level structure of shift register 4 particularly becomes the structure of setting output impedance according to the number of the TFT11 that connects with corresponding scan signal line GL.In this case, if it is different and different that the level structure of elementary and final level is compared with the level structure of other grade S because of the mode of signal input and output, also each level structure that removes grade S elementary and final grade can be made as the structure of setting output impedance according to the number of the TFT11 that is connected with corresponding scan signal line GL.
And especially in the present embodiment, the number of the TFT11 that connects with corresponding scan signal line GL is many more, constitute each level structure efferent on draw the channel width of transistor (the 1st transistor) of portion 21 big more.Make the transistorized channel width of drawing portion 21 on the formation become big, can make thus between the off period of TFT11 to the transition stage of conduction period, draw the transistorized conducting resistance of portion 21 to diminish on the formation, i.e. output impedance diminishes.
Therefore, distribution according to scan signal line GL postpones to set the channel width of drawing portion 21, just can make the distribution delay of the series circuit integral body of drawing portion 21 and scan signal line GL and even the rising waveform of sweep signal become consistent each other at scan signal line GL.In addition, also can be in last level of drawing beyond the portion 21 assigned position possess the 1st transistor and set output impedance less, wherein, how described number the more the 1st transistorized channel width of the TFT11 that is connected with scan signal line GL be big more.
With adjusting the structure of drawing the channel width of portion 21 on above-mentioned, can make the rising waveform of sweep signal become consistent each other at scan signal line GL, therefore can begin regularly unified each other the writing of video data of scan signal line GL pixel PIX, even the special-shaped display device of non-rectangle, also same with the display device of rectangle, can be to the pixel PIX that is connected with each scan signal line ... carry out uniform sequential scanning based on the sweep signal of 1 identical horizontal period.
In addition, each level structure also can be following structure: the number of the TFT11 that connects with corresponding scan signal line GL is many more, and the channel width of transistor (the 1st transistor) of pull-down section 22 that constitutes efferent is big more.Strengthen to constitute the transistorized channel width of pull-down section 22, can make from conduction period of TFT11 the transition stage between the off period, the transistorized conducting resistance that constitutes pull-down section 22 diminishes, i.e. output impedance diminishes.From draw/drop-down control part 20 pulls down the fixing voltage of grid output of portion 22, and this moment, pull-down section 22 became conducting state at the drain electrode of linear areas, the point of certain voltage between the source electrode.After this, GL is sidelong electricity along with scan signal line, and the drain potential of pull-down section 22 reduces, and drain electrode, voltage between source electrodes diminish, and the result is that the direction that the working point of pull-down section 22 increases to channel resistance in linear areas gradually moves.During this period, more can be because channel width is big more in the upper side work of linear areas, so pull-down section 22 can be in the as far as possible little regional work of channel resistance, output impedance diminishes.
In the structure of the channel width of adjusting above-mentioned pull-down section 22, can make the falling waveform of sweep signal become consistent each other at scan signal line GL, therefore can make pick-up voltage Δ V become consistent each other at scan signal line GL, improve display quality.
Therefore, postpone to set the channel width of pull-down section 22 according to the distribution of scan signal line GL, the distribution of the series circuit integral body of pull-down section 22 and scan signal line GL is postponed and even the falling waveform of sweep signal becomes consistent each other at scan signal line GL.In addition, also can possess following the 1st transistor at the assigned position in pull-down section 22 level in addition and set output impedance less, wherein, how described number the more the 1st transistorized channel width of the TFT11 that is connected with scan signal line GL be big more.
Draw on can carrying out at least the above-mentioned channel width of portion 21 set and the above-mentioned channel width setting of pull-down section 22 at least one side.In addition, draw the action of portion 21 and pull-down section 22 as follows on above-mentioned: carried out TFT11 between the off period after the transformation of conduction period, on draw portion 21 transistor under the situation that keeps the conducting state of last self between tour through conduction period of TFT11, and, carried out TFT11 after the transformation of conduction period between the off period, the transistor of pull-down section 22 under the situation that keeps the conducting state of last self between tour through between the off period of TFT11.Therefore, between the conduction period and off period of TFT11, as long as draw each transistorized grid, the voltage between source electrodes of portion 21 and pull-down section 22 identical on the level chien shih, the magnitude relationship of level output impedance each other is just identical with separately transition stage before this corresponding to the magnitude relationship of channel width.Thus, draw under portion 21 is continuously applied forward voltage to TFT11 in the conduction period of TFT11 the situation, in being continuously applied under the situation of cut-off voltage to TFT11 between the off period of TFT11 last in pull-down section 22, each level structure that also can following formation shift register 4: among at least one side between the conduction period of TFT11 and off period, the number of the TFT11 that connects with corresponding scan signal line GL is many more, and output impedance is set more for a short time.
In addition, also can be to make the TFT11 of pixel PIX under low level sweep signal, become conducting state, under the sweep signal of high level, become the structure of cut-off state, therefore also can be with pull-down section 22 as applying the device of forward voltage to TFT11 in conduction period of TFT11, with on draw portion 21 as the device that between the off period of TFT11, applies cut-off voltage to TFT11.
In addition, also can consider following structure: TFT11 between the off period to the transition stage of conduction period, on draw both transistors of portion 21 and pull-down section 22 to become conducting state.Flow through the electric current that draws portion 21 and be diverted to pull-down section 22 sides and scan signal line GL side when making, the electric current that then flows to scan signal line GL side can change along with the channel resistance of pull-down section 22.Therefore, for example, as long as will on draw the transistor size of portion 21 to be set to fix at inter-stage, the transistor size of following setting pull-down section 22: the many more levels of number of the TFT11 that connects with corresponding scan signal line GL, transistor size is more little, output impedance is set more for a short time, will increase to the electric current of scan signal line GL side flow.Reduce channel width for reducing transistor size.In addition, for setting output impedance less, also can increase the channel length of pull-down section 22.
In addition, also can separate with above-mentioned record or with above-mentioned record simultaneously, each level structure of following setting shift register 4: set output impedance less thereby the assigned position in level possesses the 1st capacity cell, wherein, how described more the 1st capacity cell capacitance of number of the TFT11 that connects with corresponding scan signal line GL be big more.
Also can be along with increasing with TFT11 number that corresponding scan signal line GL connects, the channel width of all crystals pipe that comprises in each level structure of shift register 4 is identical or increase.
In addition, also can be along with increasing with TFT11 number that corresponding scan signal line GL connects, the capacitance of all capacity cells that comprise in each level structure of shift register 4 is identical or increase.
In addition, it is different each other that above-mentioned distribution postpones at scan signal line GL, but, even on identical scan signal line GL, also can make signal delay occur distributing owing to the distribution of resistance and electric capacity.Be arranged in the pixel PIX from the nearer distance of efferent of the level S of shift register 4 in pixel region AR1, therefore the waveform of sweep signal can produce the pick-up voltage Δ V of the size shown in Fig. 6 (a) near the situation of Fig. 6 (a).On the other hand, be arranged in the pixel PIX of efferent larger distance from the level S of shift register 4 in pixel region AR1, the distribution delay of scan signal line GL can impact, and there is the tendency near Fig. 6 (b) such waveform in sweep signal.At this moment, compare with Fig. 6 (a), pick-up voltage Δ V diminishes along with the increase of above-mentioned distance.Therefore, on identical scan signal line GL, for identical data-signal, distributing in the face can appear in the pixel electrode current potential, and display quality reduces.
Therefore, make like that with Fig. 7 (a) waveform of the sweep signal that the S at different levels of shift register 4 export is relative from the common waveform that voltage Vgh directly rises to voltage Vgl, as the waveform a1 of Fig. 7 (b), make from the waveform passivation in advance of the sweep signal of the S outputs at different levels of shift register 4, make first half between decrement phase during tilt from voltage Vgh among the T1, and after voltage being reduced partway, make voltage be reduced to voltage Vgl etc. to descend step-likely.Thus, the falling waveform of the optional position sweep signal on identical scan signal line GL all can be roughly consistent, can make pick-up voltage Δ V unanimity.
Above-mentioned display panels 1 can be accommodated in the cabinet as display device with light source cell, control circuit, power supply unit etc.Display panels 1 possesses the image-region AR1 of non-rectangle, thus as long as the part that does not want in the bight of section base board etc. just can be used to constitute other parts of display device in the excision position configuration.
In above embodiment, illustrated that image-region AR1 is oval-shaped situation, but the shape of the special-shaped image-region AR1 of non-rectangle also can be other shape.For example, can enumerate shown in (e) of the semicircular ring shape shown in (d) of the toroidal shown in (c) of the semicircle shown in (b) of round-shaped, the Fig. 8 shown in (a) of Fig. 8, the broken semicircle that lacks, Fig. 8, Fig. 8, Fig. 8 with straight line or curve a part of bight of rectangles such as rectangle is tilted to cut off after (f) of shape, Fig. 8 shown in quadrilaterals such as hexagon, octagon beyond polygonal shape etc.
In addition, in above embodiment, only in side's side of the direction of extending with scan signal line GL and image-region AR1 adjacent areas, be provided with shift register, but be not limited thereto, also can be on the direction of extending with scan signal line GL shift register be set in the zone of the both sides adjacent respectively with image-region AR1.In this case, can determine corresponding shift register respectively, make odd-numbered line different with the shift register of even number line correspondence to each scan signal line GL.In addition, except shift register being separated, also can be structure from identical timing to each scan signal line GL that import identical signal from the shift register of both sides with by odd-numbered line and even number line.
In addition, in above embodiment, enumerated 3 terminal components of TFT, but be not limited thereto, also can adopt other 3 terminal components such as common MOS transistor as pixel PIX.
In addition, in above embodiment, enumerated and adopted the situation of liquid crystal, but be not limited thereto, can be applied to usually in the display medium that EL display unit etc. drives with the matrix distribution as display medium.
In addition, in above embodiment, adopt the efferent of n channel-type TFT, but also can constitute efferent with any polarity such as p channel-type TFT, the ambipolar TFT of pn as the level S of shift register 4.
The invention is not restricted to above-mentioned embodiment, can carry out various changes in the scope shown in the claim.That is, the technological means that will suitably change in the scope shown in the claim makes up the embodiment that is obtained and is also contained in the technical scope of the present invention.
As mentioned above, display panel of the present invention possesses the pixel region of employing 3 terminal components as the active array type of active component, and the number of above-mentioned 3 terminal components that are connected with each scan signal line of above-mentioned pixel region is the number that the position arbitrary decision is set according to each said scanning signals line, be in the display panel of shape of non-rectangle at above-mentioned pixel region thus, the shift register that drives the said scanning signals line be formed on the direction that the said scanning signals line on the display panel substrate extends in above-mentioned pixel region with above-mentioned pixel region adjacent areas in.
According to above situation, has the effect of the display panel of the special-shaped pixel region cabling zone, that possess non-rectangle that can realize to reduce the outer peripheral distribution of pixel region.
The embodiment of detailed description summary of the invention or embodiment are only for clear and definite technology contents of the present invention, should not only limit to this concrete example and the explanation of narrow sense ground, can in the scope of spirit of the present invention and the claim of being put down in writing, carry out various changes and implement.
Industrial utilizability
The present invention can generally be applicable to display unit.
Claims (17)
1. display panel, possess and adopt the pixel region of 3 terminal components as the active array type of active component, and the number of above-mentioned 3 terminal components that are connected with each scan signal line of above-mentioned pixel region is the position to be set and the number of arbitrary decision according to each said scanning signals line, make above-mentioned pixel region become the shape of non-rectangle thus, described display panel is characterised in that:
The shift register that drives the said scanning signals line be formed on the display panel substrate, on the direction that the said scanning signals line extends in above-mentioned pixel region with above-mentioned pixel region adjacent areas in.
2. display panel according to claim 1 is characterized in that:
Arrange the peripheral parts along adjacent above-mentioned pixel region at different levels of above-mentioned shift register,
The periphery of the above-mentioned display panel substrate of the part adjacent with above-mentioned shift register presents the shape of bending direction of the above-mentioned peripheral part of the above-mentioned pixel region that has reflected the above-mentioned periphery of being positioned at of above-mentioned display panel substrate inboard.
3. display panel according to claim 1 and 2 is characterized in that:
Comprise a plurality of level with following relation in the above-mentioned shift register: each level structure is according to the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line, set above-mentioned 3 terminal components between the off period at least one side's from the transition stage of conduction period between the off period of the transition stage of conduction period and above-mentioned 3 terminal components output impedance.
4. display panel according to claim 3 is characterized in that:
Comprise a plurality of level with following relation in the above-mentioned shift register: each level structure is according to the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line, the output impedance of at least one side in setting between off period of conduction period of above-mentioned 3 terminal components and above-mentioned 3 terminal components.
5. according to claim 3 or 4 described display panels, it is characterized in that:
Comprise above-mentioned a plurality of above-mentioned level in the above-mentioned level except that elementary and final level of above-mentioned shift register with above-mentioned relation.
6. according to each the described display panel in the claim 3 to 5, it is characterized in that:
The assigned position of above-mentioned each level structure in level in the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register possesses following the 1st transistor: the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line is many more, the described the 1st transistorized channel width is big more, so that above-mentioned output impedance reduces.
7. according to each the described display panel in the claim 3 to 5, it is characterized in that:
The assigned position of above-mentioned each level structure in level in the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register possesses following the 1st transistor: the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line is many more, the described the 1st transistorized channel length is more little, so that above-mentioned output impedance reduces.
8. according to claim 6 or 7 described display panels, it is characterized in that:
Above-mentioned each level structure of above-mentioned shift register comprises that the transistor that is arranged on to the efferent of the said scanning signals line output scanning signal of correspondence is as above-mentioned the 1st transistor.
9. display panel according to claim 8 is characterized in that:
Above-mentioned efferent possess the high side that generates sweep signal voltage pull-up unit and generate the drop-down unit of voltage of the downside of sweep signal,
Above-mentioned the 1st transistor is the transistor as above-mentioned pull-up unit.
10. display panel according to claim 8 is characterized in that:
Above-mentioned efferent possess the high side that generates sweep signal voltage pull-up unit and generate the drop-down unit of voltage of the downside of sweep signal,
Above-mentioned the 1st transistor is the transistor as above-mentioned drop-down unit.
11. each the described display panel according in the claim 3 to 10 is characterized in that:
The assigned position of above-mentioned each level structure in level in the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register possesses following the 1st capacity cell: the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line is many more, the capacitance of described the 1st capacity cell is big more, so that above-mentioned output impedance reduces.
12. each the described display panel according in the claim 3 to 5 is characterized in that:
In above-mentioned each level structure of above-mentioned shift register, along with the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line increases, the channel width of all crystals pipe that comprises in above-mentioned each level structure is identical or increase.
13. each the described display panel according in the claim 3 to 5 is characterized in that:
In above-mentioned each level structure of above-mentioned shift register, along with the number of above-mentioned 3 terminal components that connect with corresponding said scanning signals line increases, the capacitance of all capacity cells that comprise in above-mentioned each level structure is identical or increase.
14. each the described display panel according in the claim 3 to 13 is characterized in that:
The falling waveform from high to low of sweep signal is step-like.
15. each the described display panel according in the claim 1 to 14 is characterized in that:
The asserts signal of input is corresponding with each grade respectively and generate respectively to the above-mentioned a plurality of above-mentioned level with above-mentioned relation of above-mentioned shift register.
16. each the described display panel according in the claim 1 to 15 is characterized in that:
It is display panels.
17. a display device is characterized in that:
Possesses each the described display panel in the claim 1 to 16.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2007-276330 | 2007-10-24 | ||
| JP2007276330 | 2007-10-24 | ||
| PCT/JP2008/062225 WO2009054166A1 (en) | 2007-10-24 | 2008-07-04 | Display panel and display |
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| Publication Number | Publication Date |
|---|---|
| CN101779227A true CN101779227A (en) | 2010-07-14 |
| CN101779227B CN101779227B (en) | 2012-03-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008801028242A Expired - Fee Related CN101779227B (en) | 2007-10-24 | 2008-07-04 | Display panel and display |
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|---|---|
| US (1) | US8462099B2 (en) |
| CN (1) | CN101779227B (en) |
| WO (1) | WO2009054166A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20100141570A1 (en) | 2010-06-10 |
| WO2009054166A1 (en) | 2009-04-30 |
| US8462099B2 (en) | 2013-06-11 |
| CN101779227B (en) | 2012-03-28 |
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