CN113594186B - Array substrate and display panel - Google Patents
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- CN113594186B CN113594186B CN202110876057.8A CN202110876057A CN113594186B CN 113594186 B CN113594186 B CN 113594186B CN 202110876057 A CN202110876057 A CN 202110876057A CN 113594186 B CN113594186 B CN 113594186B
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- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims description 34
- 230000003071 parasitic effect Effects 0.000 claims description 32
- 239000010409 thin film Substances 0.000 claims description 5
- 239000011148 porous material Substances 0.000 claims 2
- 230000000875 corresponding effect Effects 0.000 description 36
- 230000000694 effects Effects 0.000 description 11
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- 238000010586 diagram Methods 0.000 description 10
- 238000004804 winding Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 5
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- 230000009471 action Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 230000002146 bilateral effect Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The application discloses an array substrate and a display panel. The display panel comprises a display area, an opening area, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of third scanning lines, a plurality of first shift register units, a plurality of second shift register units and a compensation unit; the first scanning line passes through the display area along a first direction; the second scanning line extends to the open hole area in the first direction; the third scanning line extends to the open hole area along the second direction; the output end of the first shift register unit is connected with a corresponding first scanning line and a corresponding second scanning line respectively, and the output end of the second shift register unit is connected with a corresponding third scanning line; the first scanning line passes through the display area and is connected with the second shift register unit, and the compensation unit is connected into a scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line. According to the embodiment of the application, the difference of the wiring capacitances at two sides of the display area can be compensated, and the delay difference of scanning signals can be reduced.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.
Background
At present, with the diversification of electronic product designs, an opening area is usually formed by digging holes in a display area of a display screen of an electronic product, and various electronic components are placed in the opening area. Such as a camera or watch hand, etc. The shapes of the display area and the open area can also be varied.
However, in the array substrate of the electronic product, in order to bypass the opening area in the display area, various wirings are required to be wound in an arc shape near the opening area so as to avoid the opening area. The windings near the open area are too dense, which will form a black border of the non-display area, so that the frame of the open area is too large. Therefore, in the conventional solution, in the pixel row corresponding to the aperture area, the scan lines are disposed on both sides of the display area and extend to the aperture area, so as to avoid the wiring around the aperture area.
In the existing scan line arrangement mode for avoiding winding, the quantity of the scan lines will affect the capacitance value of the parasitic capacitance at the side, when the quantity of the scan lines driven at the two sides of the display area is inconsistent, the capacitance values of the parasitic capacitance at the two sides will be different, so that the delay of the scan signals received by the scan lines at the two sides is different, and a flicker phenomenon occurs during display.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, which can solve the technical problem of different delay of received scanning signals caused by inconsistent numbers of scanning lines arranged on two sides of an open hole area.
In a first aspect, an embodiment of the present application provides an array substrate, where the array substrate includes a display area and an opening area in the display area; the array substrate includes:
a plurality of first scan lines extending from a first side of the display region in a first direction and passing through the display region, the first scan lines not intersecting the aperture region;
a plurality of second scan lines extending from a first side of the display area to the aperture area along the first direction;
a plurality of third scan lines extending from a second side of the display region to the aperture region in a second direction, the first direction being opposite to the second direction;
the display device comprises a display area, a plurality of first shift register units, a first clock signal line, a second clock signal line, a first scanning line and a second scanning line, wherein the first shift register units are arranged on the first side of the display area, the input ends of the first shift register units are connected with the first clock signal line, the output ends of the first shift register units are respectively connected with the corresponding first scanning line and second scanning line, and the plurality of first shift register units are sequentially connected in a cascade manner;
The display device comprises a display area, a plurality of second shift register units, a first clock signal line, a second clock signal line, a third scanning line and a fourth scanning line, wherein the second shift register units are arranged on the second side of the display area, the input ends of the second shift register units are connected with the second clock signal line, the output ends of the second shift register units are connected with the corresponding third scanning line, and the plurality of second shift register units are sequentially connected in cascade;
a first scanning line in a preset range of the distance between the first scanning lines and the second shift register unit passes through the display area and is connected with the second shift register unit;
the compensation unit is connected to a scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line.
In a second aspect, an embodiment of the present application provides a display panel, including an array substrate as above.
Compared with the prior art, the array substrate and the display panel provided by the embodiment of the application have the advantages that the first scanning line which does not cross the open hole area is arranged in the display area, the second scanning line and the third scanning line which extend towards the open hole area are respectively arranged at two sides of the open hole area, and the first scanning line passes through the display area and then is connected with the second shift register unit so as to provide scanning signals, so that the influence on the display effect caused by a large number of windings around the open hole area is avoided. Because one side of the display area is provided with the first scanning line and the second scanning line, and the other side is provided with the third scanning line, if the sum of the numbers of the first scanning line and the second scanning line is different from that of the third scanning line, parasitic capacitances at two sides of the display area are different, and when the clock signal lines are adopted to drive the scanning lines at two sides of the display area respectively, scanning signals received by the scanning lines at two sides generate different signal delays due to the influence of different parasitic capacitance values. When the parasitic capacitance value of one side where the third scanning line is located is lower than that of one side where the first scanning line and the second scanning line are located, the corresponding compensation units are arranged on the scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line, so that the wiring capacitance on the clock signal lines on two sides of the display area can be kept consistent, the signal difference on two sides of the display area caused by different numbers of the scanning lines is reduced, the delay error of scanning signals received by the scanning lines on two sides is reduced, and the synchronism and the coordination of the scanning signals are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of an array substrate according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a compensation unit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a compensation unit according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a compensation unit according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a portion of a circuit structure of a first shift register unit according to an embodiment of the present application;
FIG. 6 is a layout of a partial circuit structure of a second shift register unit according to an embodiment of the present application
FIG. 7 is a schematic diagram of a light emitting control line on an array substrate according to an embodiment of the application;
FIG. 8 is a schematic diagram of a scan line and a light emitting control line according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the application.
In the accompanying drawings:
1. a display area; 2. an opening area; 10. a first scan line; 11. a second scanning line; 12. a third scan line; 20. a first shift register unit; 21. a second shift register unit; 30. a compensation unit; 31. a first compensation capacitor; 32. a second compensation capacitor; 33. a third compensation capacitor; 40. a first clock signal line; 41. a second clock signal line; 50. a first light emitting control line; 51. a second light emission control line; 52. a third light emission control line; 60. a third shift register unit; 61. a fourth shift register unit; 70. a second compensation unit; 80. a third clock signal line; 81. and a fourth clock signal line.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.
Currently, holes are generally dug in a display area of a display screen of an electronic product to form an open area, and various electronic components, such as a camera or a watch pointer, are placed in the open area to realize various functions of the electronic product. The shape of the display area and the shape of the opening area can be various.
The open area in the display area is generally not provided with pixel circuits, and in order to provide a space for the electronic components, various wirings in the display area need to be arc-shaped around the open area to avoid the open area. The dense windings near the open area will form black edges at the junction of the display area and the open area, so that the black frame of the open area is too large, and the normal display effect of the display area is affected.
Aiming at the problem that the display effect is influenced by intensive winding, the existing solution is generally to set scanning lines to extend to an open area from two sides of a display area in pixel rows corresponding to the open area, so that the scanning lines extending from one side are prevented from winding when passing through the open area.
However, in the pixel row corresponding to the aperture region, the scan lines are respectively disposed on both sides of the display region, that is, the corresponding shift register units are respectively disposed, and the number of the shift register units is equal. In the pixel rows not corresponding to the aperture area, the scanning lines are extended from one side of the display area, and the shift register units corresponding to the scanning lines are disposed only on one side of the display area. Accordingly, the display area has more scan lines driven on one side than the other side, and accordingly, the number of shift register units respectively provided on both sides of the display area is also different. When the clock signal lines on two sides of the display area are connected with the shift register units on two sides, corresponding wiring capacitance is generated, the wiring capacitance is related to the number of stages of the shift register units connected on the clock signal lines, and the wiring capacitance on the clock signal lines on two sides of the display area is not the same because the number of the shift register units on two sides of the display area is not the same, so that the waveform delay of the scanning signals output on two sides of the display area is different, and the display effect is affected.
In order to solve the above technical problems, an embodiment of the application provides an array substrate and a display panel. The following first describes an array substrate provided by an embodiment of the present application.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application. The array substrate comprises a display area 1, an opening area 2 in the display area 1, a plurality of first scanning lines 10, a plurality of second scanning lines 11, a plurality of third scanning lines 12, a plurality of first shift register units 20, a plurality of second shift register units 21 and a compensation unit 30.
As shown in fig. 1, the first side and the second side of the display area 1 are two side edges disposed opposite to each other. The first scan line 10 extends from the first side of the display area 1 in the first direction and passes through the display area 1, the first scan line 10 does not cross the aperture area 2 within the display area 1 while passing through the display area 1. That is, the projection of the first scan line 10 perpendicular to the array substrate does not overlap with the projection of the opening area 2 perpendicular to the array substrate.
The second scan line 11 extends from the first side of the display area 1 to the open area 2 along a first direction, and the third scan line 12 extends from the second side of the display area 1 to the open area 2 along a second direction, and the first direction is opposite to the second direction. That is, the second scan line 11 and the third scan line 12 are both located in the pixel row corresponding to the open area 2, the open area 2 divides the corresponding pixel row into two segments, the second scan line 11 is connected to the same row of pixels from the first side of the display area 1 to the open area 2, and the third scan line 12 is connected to the same row of pixels from the second side of the display area 1 to the open area 2. It will be appreciated that, since the aperture area 2 separates each row of pixels passing through the aperture area 2, the number of pixel rows on both sides of the aperture area 2 is the same, and the number of second scan lines 11 and the number of third scan lines 12 are in one-to-one correspondence with the number of pixel rows on both sides of the aperture area 2, and the number of second scan lines 11 is equal to the number of third scan lines 12.
The first shift register unit 20 is disposed on the first side of the display area 1, an input terminal of the first shift register unit 20 is connected to the first clock signal line 40, and an output terminal of the first shift register unit 20 can provide a scan signal for a scan line extending from the first side of the display area 1. While the first scan line 10 and the second scan line 11 each extend from the first side of the display area 1, the first shift register unit 20 may be connected to the first scan line 10 and the second scan line 11, respectively, to provide corresponding scan signals. It will be appreciated that the number of first shift register cells 20 is the sum of the number of first scan lines 10 and second scan lines 11.
The first shift register units 20 may also be sequentially connected in cascade, and when the scan signal is set to be positive, the scan signal output by each first shift register unit 20 is further sent to the next first shift register unit 20, so that the next first shift register unit 20 generates the scan signal according to the clock signal of the first clock signal line 40 and outputs the scan signal to the corresponding scan line. Similarly, when the scan signal is set to the reverse scan, the scan signal output from each first shift register unit 20 is transmitted to the previous first shift register unit 20, so that the previous first shift register unit 20 outputs the corresponding scan signal.
The second shift register unit 21 is disposed on the second side of the display area 1, the input end of the second shift register unit 21 is connected to the second clock signal line 41, the output end of the second shift register unit 21 can provide the scan signal for the scan line extending from the second side of the display area 1, and the third scan line 12 extends from the second side of the display area 1. Accordingly, the second shift register unit 21 may be connected to the corresponding third scan line 12 to provide the corresponding scan signal to the pixels on the third scan line 12. It is understood that the number of the second shift register units 21 may be equal to the number of the third scan lines 12.
The second shift register units 21 may be sequentially arranged in cascade, and may be sent to the adjacent second shift register units 21 when outputting the scan signal according to whether the scan signal is in the normal scan setting or the reverse scan setting, so as to trigger the adjacent second shift register units 21 to generate the scan signal.
Among the plurality of first shift register units 20, each first shift register unit 20 may receive the scan signal output from the adjacent first shift register unit 20 and generate the scan signal through the clock signal output from the first clock signal line 40. After the scan signal output by the first shift register unit 20 passes through the display area 1 from the first side of the display area 1 to the second side of the display area 1 through the first scan line 10, the first scan line 10 may be connected to the second shift register unit 21, so that the second shift register unit 21 receives the scan signal, and thus the second shift register unit 21 is triggered to generate a corresponding scan signal according to the clock signal on the second clock signal line 41. That is, among the plurality of second shift register units 21, the scan signal received by the first second shift register unit 21 is the scan signal transmitted from the first shift register unit 20 to the first scan line 10, and transmitted to the second shift register unit 21 after passing through the display area 1 by the first scan line 10, and after outputting the scan signal, the second shift register unit 21 transmits the scan signal to the adjacent second shift register units 21 through the sequentially cascaded second shift register units 21, so that all the second shift register units 21 sequentially receive the scan signal.
It will be appreciated that since the second scan line 11 extends only to the aperture area 2 and cannot pass completely through the display area 1, the scan signal received by the second shift register unit 21 is transmitted by the first scan line 10. The first scan line 10 may be the first scan line 10 having a distance from the second shift register unit 21 within a preset range. The second shift register unit 21 may receive a scan signal through the first scan line 10, thereby triggering the sequentially cascaded second shift register units 21 to generate the scan signal.
The first shift register unit 20 receives a clock signal via a first clock signal line 40 to generate a scan signal, and the second shift register unit 21 receives a clock signal via a second clock signal line 41 to generate a scan signal. The number of first shift register cells 20 on the first clock signal line 40 is greater than the number of second shift register cells 21 on the second clock signal line 41. Since each shift register cell generates a corresponding parasitic capacitance, and the trace capacitance on the clock signal line is associated with the parasitic capacitance of each shift register cell, when the first shift register cell 20 is more than the second shift register cell 21, the trace capacitance on the first clock signal line 40 is also greater than the trace capacitance on the second clock signal line 41. The wiring capacitance on the clock signal line affects the output delay of the scan signal output by the shift register unit, and when the first clock signal line 40 is different from the wiring capacitance on the second clock signal line 41, the delay difference between the scan signal output by the first shift register unit 20 and the scan signal output by the second shift register unit 21 is caused.
The compensation unit 30 is connected to a scan signal loop formed by the second clock signal line 41, the second shift register unit 21 and the third scan line 12, and the compensation unit 30 can compensate the overall routing capacitance on the second clock signal line 41, so that the routing capacitance on the second clock signal line 41 is equal to or similar to the routing capacitance on the first clock signal line 40.
In this embodiment, by providing the first scan line 10 on the pixel row other than the open area 2 and providing the second scan line 11 and the third scan line 12 on both sides of the pixel row corresponding to the open area 2, it is possible to avoid the occurrence of a black border around the open area 2 due to the winding around the open area 2, and reduce the width of the border between the display area 1 and the open area 2. The first shift register unit 20 may output corresponding scan signals to the first scan line 10 and the second scan line 11, and the first scan line 10 may be further connected with the second shift register unit 21 after extending through the display area 1 to transmit the scan signals to the second shift register unit 21 at the other side of the display area 1 such that the second shift register unit 21 can transmit the scan signals to the third scan line 12. Since the number of the first shift register units 20 and the number of the second shift register units 21 are different, the compensation units 30 may be further disposed on the scan signal circuit formed by the second clock signal line 41, the second shift register units 21 and the third scan line 12, so as to compensate the capacitance difference generated by the number difference of the shift register units at two sides of the display area 1, so that the shift register units at two sides of the display area 1 can generate scan signals with identical or similar waveforms through the first clock signal line 40 and the second clock signal line 41 respectively, and avoid the flicker phenomenon during display caused by the delay difference of the scan signals.
In some embodiments, the compensation value of the compensation unit 30 may be a difference between the parasitic total capacitance of all the first shift register units 20 and the parasitic total capacitance of all the second shift register units 21.
The capacitance value of the routing capacitor on the first clock signal line 40 is related to the number of stages of the first shift register units 20 driven by the routing capacitor, for a plurality of first shift register units 20 that are sequentially cascaded, the capacitance value of the parasitic capacitor formed by each first shift register unit 20 is a, and the number of the first shift register units 20 is n, so that the total parasitic capacitance of all the first shift register units 20 is the product of the single-stage parasitic capacitance of each first shift register unit 20 and the number of the first shift register units 20, i.e. n×a.
The number of second scan lines 11 is the same as the number of third scan lines 12, and the sum of the numbers of second scan lines 11 and first scan lines 10 is the same as the number of first shift register units 20. If the number of second scanning lines 11 is m, the number of first scanning lines 10 is (n-m), the number of third scanning lines 12 is m, and the number of second shift register units 21 is also m. When the parasitic capacitance formed by the first shift register unit 20 is equal to the parasitic capacitance formed by the second shift register unit 21, the total parasitic capacitance of all the second shift register units 21 is the product of the single-stage parasitic capacitance of the second shift register unit 21 and the number, i.e. m×a.
The compensation value of the compensation unit 30 may be an equivalent capacitance value of the compensation unit 30, which may be set as a difference between the parasitic total capacitance of all the first shift register units 20 and the parasitic total capacitance of all the second shift register units 21, i.e., (n-m) ×a. After compensating the trace capacitance on the second clock signal line 41, the actual capacitance on the second clock signal line 41 is the same as the trace capacitance on the first clock signal line 40, and the delays of the scan signals output by the first shift register unit 20 and the second shift register unit 21 are equal.
Note that the compensation unit 30 may be disposed in a scan signal loop formed by the second clock signal line 41, the second shift register unit 21, and the third scan line 12, and the disposed positions may be respective nodes in the scan signal loop.
Referring to fig. 2, in some embodiments, the second clock signal line 41 may include a CK clock signal line and an XCK clock signal line, and the second shift register unit 21 is connected to the CK clock signal line and the XCK clock signal line, respectively. The compensation unit 30 may include:
two first compensation capacitors 31, one first compensation capacitor 31 is connected to the CK clock signal line, and the other first compensation capacitor 31 is connected to the XCK clock signal line.
The second shift register unit 21 may generate corresponding scan signals from the CK clock signal and the XCK clock signal output from the CK clock signal line and the XCK clock signal line and output the same to the third scan line 12 connected to the second shift register unit 21 when receiving the scan signal transmitted from the first scan line 10 or the scan signal transmitted from the adjacent second shift register unit 21.
For the CK clock signal line, it is necessary to access the CK clock signal line through the first compensation capacitor 31 to compensate for the difference in parasitic capacitance of the first shift register unit 20 and the second shift register unit 21. One end of the first compensation capacitor 31 is connected to the CK clock signal line, and the other end thereof may be grounded or connected to the power signal line. Similarly, for the XCK clock signal line, another first compensation capacitor 31 may be provided to be connected to the XCK clock signal line to compensate for the difference between the parasitic capacitances of the first shift register unit 20 and the second shift register unit 21. It will be appreciated that the capacitance of the two first compensation capacitors 31 is equal, and the capacitance is equal to the difference between the parasitic total capacitance of all the first shift register cells 20 and the parasitic total capacitance of all the second shift register cells 21.
Referring to fig. 3, in some embodiments, the compensation unit 30 may further include:
the second compensation capacitors 32 may be disposed outside the display area 1, and each second compensation capacitor 32 is connected to the output terminal of the corresponding second shift register unit 21.
The second shift register unit 21 has an input connected to the second clock signal line 41 and an output connected to the third scanning line 12. The third scan line 12 is located in the display area 1, the second shift register unit 21 is located outside the display area 1, and the second compensation capacitor 32 may be disposed outside the display area 1 and connected to the output terminal of the second shift register unit 21.
The number of second compensation capacitances 32 may be set equal to the number of second shift register units 21. The capacitance value of each second compensation capacitor 32 may be set equal or unequal, and the equivalent capacitance value of all second compensation capacitors 32 is equal to the difference between the parasitic total capacitance of all first shift register cells 20 and the parasitic total capacitance of all second shift register cells 21. One end of each second compensation capacitor 32 is connected to the output terminal of the corresponding second shift register unit 21, and the other end thereof may be grounded or connected to a power signal line.
Referring to fig. 4, in some embodiments, the compensation unit 30 may further include:
the third compensation capacitors 33 are disposed on one side of the display area 1 near the opening area 2, and each third compensation capacitor 33 is connected to a corresponding third scan line 12.
The number of the third compensation capacitances 33 may be set equal to the number of the third scan lines 12, the capacitance value of each third compensation capacitance 33 may be set equal or unequal, and the sum of the equivalent capacitances of all the third compensation capacitances 33 is equal to the difference between the parasitic total capacitance of all the first shift register units 20 and the parasitic total capacitance of all the second shift register units 21. The third compensation capacitor 33 may be disposed on a side of the display area 1 near the open area 2, so as to be disposed in a region where the display area 1 and the open area 2 are intersected. One end of the third compensation capacitor 33 may be connected to the corresponding third scan line 12, and the other end may be grounded or connected to a power signal line.
In the above embodiments, the compensation unit 30 may be disposed on the second clock signal line 41, between the output terminal of the second shift register unit 21 and the display area 1, and on the third scan line 12 near the open area 2 side, respectively. The number of compensation capacitors can be adaptively adjusted when the compensation capacitors are arranged at different positions. The difference value of the wiring capacitance on the clock signal lines at two sides of the display can be compensated through the plurality of compensation capacitors, so that the delay difference of scanning signals output by the shift register units at two sides of the display is avoided.
In some embodiments, the size of the second shift register unit 21 may be smaller than the size of the first shift register unit 20. The size of the shift register unit may include the number of thin film transistors constituting the circuit structure. As shown in fig. 5, the first shift register unit 20 may be a circuit structure composed of 16 thin film transistors. As shown in fig. 6, the second shift register unit 21 may be provided as a circuit structure composed of 12 thin film transistors.
It can be understood that as the number of thin film transistors constituting the shift register unit decreases, the delay of the scan signal output by the shift register unit increases accordingly. Since the trace capacitance and trace resistance on the clock signal line will produce an equivalent delay circuit, when the trace capacitance on the first clock signal line 40 is greater than the trace capacitance on the second clock signal line 41, the delay of the signal waveform on the first clock signal line 40 is also greater than the delay of the second waveform on the second clock signal line 41. By reducing the size of the second shift register unit 21 relative to the first shift register unit 20, the waveform delay of the scanning signal output from the second shift register unit 21 can be increased, and thus the delay of the scanning signal output from the second shift register unit 21 can be increased to coincide with the delay of the scanning signal output from the first shift register unit 20.
It should be noted that, the size of the second shift register unit 21 is smaller than the size of the first shift register unit 20, and the delay increase of the scan signal output from the second shift register unit 21 may be separately realized. The size of the second shift register unit 21 is set smaller than that of the first shift register unit 20, and the size of the second shift register unit 21 may also be combined with the compensation unit 30, for example, the compensation unit 30 only partially compensates the difference between the routing capacitances of the first clock signal line 40 and the second clock signal line 41, where the waveform delay of the scan signal output by the second shift register unit 21 is still smaller than that of the scan signal output by the first shift register unit 20, and by adjusting the size of the second shift register unit 21, the waveform delay of the scan signal output by the second shift register unit 21 may be further adjusted to achieve the consistency of the waveform delays of the scan signals output by the two shift register units. It will be appreciated that when the compensation unit 30 is not provided and the sizes of the first shift register unit 20 and the second shift register unit 21 are not adjusted, there is a delay difference in the scan signals on both sides of the display area 1, thereby affecting the actual display effect.
In some embodiments. When the pixel circuits in the array substrate are arranged in an array, the length of the scan line is positively correlated with the number of the pixel circuits on the scan line, and since the first scan line 10 can pass through the display area 1 and the second scan line 11 can only extend to the open area 2, the number of the pixel circuits on the first scan line 10 near the open area 2 is greater than the number of the pixel circuits on the second scan line 2.
After sampling the waveforms of the scanning signals of the plurality of scanning lines with different numbers of the pixel circuits, it can be determined that when the number ratio of the pixel circuits on the two scanning lines reaches 0.7 times, the delay difference generated by the scanning signals on the two scanning lines reaches 30 nanoseconds, the luminous brightness difference reaches 2.86%, and at the moment, the pixel circuits on the two scanning lines have obvious luminous difference, so that the overall display effect of the display panel is affected. Also, when the difference in the number of pixel circuits on the two scanning lines gradually increases, the difference in delay and the difference in light emission luminance of the two scanning signals will further increase. The Gate Delay time Gate Delay of the scan signal on the scan line with a lower number of pixel circuits is smaller, and the Gate Delay time of the scan signal on the scan line with a higher number of pixel circuits is larger.
When the gate delay time of the scan signal received by the pixel circuit increases, the feedthrough voltage of the pixel circuit decreases, and the pixel voltage and the feedthrough voltage are positively correlated, that is, the pixel voltage also decreases, so that the light-emitting brightness of the pixel circuit decreases due to the decrease of the pixel voltage. After brightness test is performed on the scanning lines with different numbers of pixel circuits, the corresponding relation between the number of the pixel circuits on the scanning lines and the brightness difference is obtained as shown in the following table:
| number of pixel circuits | Luminous current | Difference in brightness |
| 0.5*n | -1.7E-09 | 5.60％ |
| 0.6*n | -1.6E-09 | 3.33％ |
| 0.7*n | -1.6E-09 | 2.86％ |
| 0.8*n | -1.6E-09 | 1.06％ |
| 0.9*n | -1.6E-09 | 1.08％ |
| n | -1.6E-09 | 0.00％ |
As shown in the above table, when the number of pixel circuits on one scanning line is n, the light emission current is-1.6E-09, and the luminance difference is 0 with the light emission luminance of the pixel circuit at this time as a reference. When the number of the pixel circuits on the scanning line is gradually reduced, the light-emitting current of the pixel circuits is also continuously increased, and when the number of the pixel circuits is gradually reduced to 0.7 times or less, the brightness difference is obvious, and the overall display effect of the display panel is affected. Therefore, when there is a large difference in the number of pixel circuits on the scan lines, corresponding pixel compensation is required to avoid the influence on the overall display effect due to the large difference in the brightness of the pixel circuits on different scan lines. The pixel compensation mode may be to connect corresponding equivalent compensation capacitors in series on one side of the scanning line near the aperture area, so that the equivalent delay circuit on the compensated scanning line is consistent with the equivalent delay circuit of the scanning line as the compensation target. The equivalent compensation capacitor may be disposed at other positions besides the side close to the opening area, and is not limited herein.
When the number of the pixel circuits is compensated to be within the range of 0.8 n-n, namely, when the number of the pixel circuits is compensated to be 0.8-1 time, the brightness difference is smaller at the moment, and the brightness is consistent, so that the large difference of the luminous brightness of the pixel circuits on different scanning lines is avoided through the pixel compensation.
It can be understood that the above embodiment of performing pixel compensation on the scan lines with large difference in number of pixel circuits may be implemented separately, or may be combined with at least two of the embodiment of adjusting the size of the shift register unit and the embodiment of providing the compensation unit 30 in the above embodiment, for example, the compensation unit 30 combines with pixel compensation, the compensation unit 30 combines with the size adjustment of the shift register unit, the pixel compensation combines with the size adjustment of the shift register unit, and the like, so as to compensate for the difference in number of pixel circuits on the scan lines and the waveform delay of the scan signal, thereby guaranteeing the display effect of the display panel.
In some embodiments, the plurality of second shift register units 21 sequentially cascaded may include a first stage second shift register unit 21. For the first stage shift register unit, a first scan line 10 satisfying a first preset condition may be determined, and the first scan line 10 is connected to the first stage shift register unit after passing through the display area 1. The first preset condition may be that the distance between the front projection of the first stage shift register unit on the array substrate and the front projection of the first scan line 10 on the array substrate is within a first preset range.
In some embodiments, the plurality of second shift registers sequentially cascaded may further include a last stage second shift register unit 21, for which a first scan line 10 satisfying a second preset condition may be determined, and the first scan line 10 may be connected to the last stage shift register unit after passing through the display area 1. The second preset condition may be that the distance between the front projection of the final stage shift register unit on the array substrate and the front projection of the first scan line 10 on the array substrate is within a second preset range.
It will be appreciated that if there are a plurality of first scan lines 10 satisfying the first preset condition, any one of the first scan lines 10 may be selected to be connected to the first stage second shift register unit 21. Similarly, if there are a plurality of first scanning lines 10 satisfying the second preset condition, any one of the first scanning lines 10 may be selected to be connected to the final stage second shift register unit 21.
After receiving the scanning signal output by the first shift register unit 20, the first scanning line 10 meeting the first preset condition transmits the scanning signal to the first-stage second shift register unit 21, the first-stage second shift register unit 21 sequentially transmits the scanning signal to other second shift register units 21 in cascade connection, and the last-stage shift register unit can send the scanning signal to the first scanning line 10 meeting the second preset condition after receiving the scanning signal, and the first scanning line 10 meeting the second preset condition can realize bilateral driving of the scanning signal through the corresponding first shift register unit 20 and the last-stage shift register unit.
In the above embodiment, the first preset condition may also be the first scan line 10 closest to the first stage shift register unit, that is, closest to the aperture region 2 and close to the first stage shift register unit side. The second preset condition may also be the first scan line 10 closest to the last stage shift register unit, i.e. closest to the aperture region 2 and close to one side of the last stage shift register unit.
In some embodiments, the array substrate may further include a light emitting control line, where the number of light emitting control lines is the same as the number of scanning lines, and each light emitting control line and the corresponding scanning line are connected to the same pixel row. For the same row of pixels, the light emission control signal of the light emission control line and the scan signal of the scan line may be received, and the row of pixels may be controlled to emit light by the light emission control signal and the scan signal together. The extending direction of the light emitting control line may be opposite to the extending direction of the scanning line, so as to realize bilateral driving of the pixels in the same row.
Referring to fig. 7, in the above embodiment, the light emission control lines may include a first light emission control line 50, a second light emission control line 51, and a third light emission control line 52. The first light emitting control line 50 extends from the second side of the display area 1 in the second direction and passes through the display area 1, and the first light emitting control line 50 does not intersect the open area 2. The second light emission control line 51 extends from the second side of the display area 1 to the aperture area 2 in the second direction. The third light-emitting control line 52 extends from the first side of the display area 1 to the opening area 2 along a first direction, and the first direction is opposite to the second direction. It is understood that the number of the first, second and third light emission control lines 50, 51 and 52 corresponds to the number of the first, second and third scan lines 10, 11 and 12, respectively, one by one.
The array substrate may further include a plurality of third shift register units 60, a plurality of fourth shift register units 61, and a second compensation unit 70.
The third shift register unit 60 is disposed on the second side of the display area 1, the input end of the third shift register unit 60 is connected to the third clock signal line 80, the output end of the third shift register unit 60 is connected to the corresponding first light emitting control line 50 and second light emitting control line 51, and the plurality of third shift register units 60 are sequentially connected in cascade.
The fourth shift register unit 61 is disposed on the first side of the display area 1, the input end of the fourth shift register unit 61 is connected to the fourth clock signal line 81, the output end of the fourth shift register unit 61 is connected to the corresponding third light emitting control line 52, and the plurality of fourth shift register units 61 are sequentially cascade-connected.
The number of the third shift register units 60 is the sum of the first light emission control lines 50 and the second light emission control lines 51, and the number of the fourth shift register units 61 is equal to the number of the third light emission control lines 52.
Among the plurality of first light emission control lines 50, the first light emission control line 50 having a distance within a preset range from the fourth shift register unit 61 may be connected to the fourth shift register unit 61 after passing through the display area 1 to transmit a light emission control signal to the fourth shift register unit 61 so that the fourth shift register unit 61 located at the first side of the display area 1 can output a corresponding light emission control signal.
It can be understood that the wiring connection mode of the light emitting control line and the wiring connection direction of the scanning line are mirror images of each other, and the two wiring modes are axisymmetric along a third direction, and the third direction is perpendicular to the first direction and the second direction. Therefore, the number of the third shift register units 60 on the third clock signal line 80 is greater than the number of the fourth shift register units 61 on the fourth clock signal line 81, and by providing the second compensation unit 70, the routing capacitance on the fourth clock signal line 81 can be compensated, so that the signal delays of the light emission control signals output from both sides of the display area 1 are kept consistent, thereby avoiding the delay differences of the light emission control signals.
Referring to fig. 8, fig. 8 shows a schematic structure in which the scanning lines and the light emission control lines commonly control the pixels in the same row, and each row of pixels is connected to one scanning line and one light emission control line, and controls the light emitting device to emit light through the received scanning signals and light emission control signals. .
The technical features corresponding to the embodiments related to the compensation unit 30, the scanning line, the first shift register unit 20, and the second shift register unit 21 can be applied to the second compensation unit 70, the light emission control line, the third shift register unit 60, and the fourth shift register unit 61, respectively, and the same technical effects can be achieved. The specific contents will not be described in detail.
Based on the same inventive concept, as shown in fig. 9, the embodiment of the application further provides a display panel, which includes any one of the array substrates provided by the embodiment of the application.
Because the display panel provided by the embodiment of the application comprises any one of the array substrates provided by the embodiment of the application, the display panel has the technical characteristics corresponding to the array substrates contained in the display panel and can achieve the same effect, and the description is omitted here.
The functional blocks shown in the above-described structural block diagrams may be implemented in hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuitry, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. The foregoing is merely a preferred embodiment of the application, and it should be noted that, due to the limited text expressions, there is objectively no limit to the specific structure, and that, for a person skilled in the art, modifications, adaptations or variations may be made without departing from the principles of the present application, and the above technical features may be combined in any suitable manner; such modifications, variations and combinations, or the direct application of the inventive concepts and aspects to other applications without modification, are contemplated as falling within the scope of the present application.
Claims (10)
1. An array substrate, which comprises a display area and an open area in the display area; the array substrate is characterized by comprising:
a plurality of first scan lines extending from a first side of the display region in a first direction and passing through the display region, the first scan lines not intersecting the aperture region;
a plurality of second scan lines extending from a first side of the display area to the aperture area along the first direction;
a plurality of third scan lines extending from a second side of the display region to the aperture region in a second direction, the first direction being opposite to the second direction;
the display device comprises a display area, a plurality of first shift register units, a first clock signal line, a second clock signal line, a first scanning line and a second scanning line, wherein the first shift register units are arranged on the first side of the display area, the input ends of the first shift register units are connected with the first clock signal line, the output ends of the first shift register units are respectively connected with the corresponding first scanning line and second scanning line, and the plurality of first shift register units are sequentially connected in a cascade manner;
the display device comprises a display area, a plurality of second shift register units, a first clock signal line, a second clock signal line, a third scanning line and a fourth scanning line, wherein the second shift register units are arranged on the second side of the display area, the input ends of the second shift register units are connected with the second clock signal line, the output ends of the second shift register units are connected with the corresponding third scanning line, and the plurality of second shift register units are sequentially connected in cascade;
A first scanning line in a preset range of the distance between the first scanning lines and the second shift register unit passes through the display area and is connected with the second shift register unit;
the compensation unit is connected to a scanning signal loop formed by the second clock signal line, the second shift register unit and the third scanning line.
2. The array substrate of claim 1, wherein the compensation value of the compensation unit is a difference between a total parasitic capacitance of all first shift register units and a total parasitic capacitance of all second shift register units.
3. The array substrate of claim 2, wherein the total parasitic capacitance of all first shift register cells is a product of a single stage parasitic capacitance of the first shift register cells and a number of the first shift register cells, and the total parasitic capacitance of all second shift register cells is a product of a single stage parasitic capacitance of the second shift register cells and a number of the second shift register cells.
4. The array substrate according to claim 2, wherein the second clock signal line includes a CK clock signal line and an XCK clock signal line, and the second shift register unit is connected to the CK clock signal line and the XCK clock signal line, respectively; the compensation unit includes:
And two first compensation capacitors, one of which is connected to the CK clock signal line and the other one is connected to the XCK clock signal line.
5. The array substrate of claim 2, wherein the compensation unit comprises:
the second compensation capacitors are arranged outside the display area, and each second compensation capacitor is connected with the output end of the corresponding second shift register unit.
6. The array substrate of claim 2, wherein the compensation unit comprises:
the display device comprises a display area, a plurality of open pore areas, a plurality of third compensation capacitors, a plurality of second scanning lines and a plurality of first scanning lines, wherein the third compensation capacitors are arranged on one side of the display area, which is close to the open pore areas, and each third compensation capacitor is connected with the corresponding third scanning line.
7. The array substrate of claim 1, wherein a size of the second shift register unit is set smaller than a size of the first shift register unit, the size including the number of thin film transistors constituting a circuit structure.
8. The array substrate according to any one of claims 1 to 7, wherein among the plurality of second shift register units which are sequentially cascaded, a first stage second shift register unit is connected to a first scanning line whose forward projection distance on the array substrate is within a first preset range.
9. The array substrate according to any one of claims 1 to 7, wherein among the plurality of second shift register units that are sequentially cascaded, a final second shift register unit is connected to a first scanning line whose forward projection distance on the array substrate is within a second preset range.
10. A display panel, characterized in that it comprises an array substrate according to any one of claims 1-9.
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| KR102646911B1 (en) * | 2019-03-14 | 2024-03-14 | 삼성디스플레이 주식회사 | Display device |
| CN112445374A (en) * | 2019-09-04 | 2021-03-05 | 三星显示有限公司 | Display device including touch sensing unit |
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