CN110927997A

CN110927997A - Display panel test circuit and test method

Info

Publication number: CN110927997A
Application number: CN201911146966.5A
Authority: CN
Inventors: 吕林鸿
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2020-03-27
Anticipated expiration: 2039-11-21
Also published as: CN110927997B

Abstract

The embodiment of the application discloses a display panel test circuit and a test method, which comprises the following steps: the test signal pads are connected with the display panel; the transistors correspond to the test signal pads one to one, the source electrode of each transistor is connected with a corresponding signal line, the drain electrode of each transistor is connected with the corresponding test signal pad, and the transistors correspond to a common grid electrode; and a control signal pad connected with the common gate. The scheme avoids the short circuit of the test signal pad and improves the display effect of the display panel.

Description

Display panel test circuit and test method

Technical Field

The application relates to the technical field of display, in particular to a display panel test circuit and a test method.

Background

In the manufacturing process of the display panel, the panel performance needs to be detected at each stage to improve the yield of the display panel. To facilitate testing, test signal pads are typically disposed on the substrate for receiving external test signals.

However, when the display panel mother substrate is cut into a plurality of small-sized panels by using the laser cutting technique, conductive foreign matters such as metal debris generated by melting of signal lines between the small-sized display panels or carbon particles generated by carbonization of the flexible substrate are generated at the cut portion, thereby causing short circuit of the test signal pads and causing abnormal display of the display panel.

Disclosure of Invention

The embodiment of the application provides a display panel test circuit and a test method, which are used for solving the problem that a test signal pad is short-circuited to cause abnormal display of a display panel due to conductive foreign matters generated when the display panel is cut by laser.

The application provides a display panel test circuit, includes:

the test signal pads are connected with the display panel;

the transistors correspond to the test signal pads one to one, the source electrode of each transistor is connected with a corresponding signal line, the drain electrode of each transistor is connected with the corresponding test signal pad, and the transistors correspond to a common grid electrode; and

a control signal pad connected with the common gate.

In the display panel test circuit, each transistor comprises a source drain region, and a plurality of source drain regions are arranged at intervals;

wherein the common gate crosses over the plurality of source and drain regions.

In the display panel test circuit, the common grid comprises a plurality of first grid parts and a plurality of second grid parts, the first grid parts are positioned in the source and drain regions, and the second grid parts are arranged between the adjacent first grid parts;

wherein a width of the second gate portion is equal to a width of the first gate portion.

In the test circuit of the display panel, the common gate further includes a third gate portion, and the third gate portion is used for connecting the control signal pad.

In the display panel test circuit of the present application, the first gate portion, the second gate portion, and the third gate portion are formed in the same layer.

In the display panel test circuit, two control signal pads are provided;

the test signal pads are arranged among the control signal pads, and the test signal pads are arranged at intervals.

In the display panel test circuit, a plurality of cutting mark lines are further arranged between the transistors and the signal lines.

In the display panel test circuit described in the present application, the control signal pads include a first control signal pad and a second control signal pad;

wherein the first control signal pad is disposed at one side of the cutting mark line, and the second control signal pad is disposed at the other side of the cutting mark line

In the display panel test circuit described in the present application, the transistor is an N-type transistor or a P-type transistor.

Correspondingly, an embodiment of the present application further provides a testing method for a testing circuit of a display panel, which is applied to the testing circuit of the display panel described above, and the testing method inputs a control signal to the common gate through the control signal pad to control the transistor to be turned off, so that the circuit between the plurality of testing signal pads and the corresponding signal lines is disconnected.

The beneficial effect of this application: the application provides a display panel test circuit and a test method, a transistor is correspondingly arranged at a position where a test signal pad receives a test signal, the transistor is controlled to be closed through a control signal pad, short circuit of the test signal pad is avoided, and the display effect of a display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a test circuit of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of the transistor shown in FIG. 2 along the section line XX';

FIG. 4 is a schematic structural diagram of a display panel testing circuit provided in an embodiment of the present application when a conductive foreign object exists;

FIG. 5 is a schematic diagram of another structure of a test circuit for a display panel according to an embodiment of the present disclosure;

fig. 6 is a flowchart of a testing method for a testing circuit of a display panel according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center", "thickness", "upper", "lower", "vertical", "horizontal", "inner", "outer", "one side", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as being fixed or detachable or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The embodiment of the application provides a display panel test circuit and a test method, and the display panel test circuit is suitable for the flat panel display and the detection field of a liquid crystal display panel or an organic light emitting diode display panel and the like.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The display panel 100 includes a display area 10, a driving circuit area 20, a fan-out structure 30, a panel test area 40, a bonding area 50, and a bending line 60.

The display area 10 has a thin film transistor array and an interlaced array of data lines and scan lines arranged at intervals. The driving circuit region 20 supplies driving signals of scan lines to the display region 10. The fan-out structure 30 includes a plurality of densely arranged data lines for transmitting data signals. The panel test area 40 transmits a test signal to the driving circuit area 20 so that the driving circuit area 20 provides a driving signal of a scan line to the display area 10. The bonding area 50 transmits the test signal into the display area 10 through the data line. The panel test region 40 and the bonding region 50 are bent toward the lower surface of the display panel along the bending line 60, thereby implementing a narrow bezel.

The display panel test circuit proposed in the present application may be disposed in the panel test region 40 and/or the bonding region 50. It should be noted that, in the manufacturing process of the display panel 100, when the display panel motherboard is cut into a plurality of small-sized panels by using the laser cutting technology, conductive foreign matters are generated at the cut portions, and any test area related to the conductive foreign matters and causing a short circuit can be provided with the display panel test circuit. The display panel test circuit will be described in detail below.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a display panel test circuit according to an embodiment of the present disclosure. The display panel test circuit includes a plurality of test signal pads 21, a plurality of transistors 22, and a control signal pad 24. Each test signal pad 21 is connected to the display panel 100. The plurality of transistors 22 correspond one-to-one to the plurality of test signal pads 21. The source of each transistor 22 is connected to a corresponding signal line 25. The drain of each transistor 22 is connected to a respective test signal pad 21. A plurality of transistors 22 correspond to a common gate 23. The control signal pad 21 is connected to the common gate 23.

The test signal pad 21 is a test signal receiving terminal. The test signal pad 21 is connected to the display panel 100 and transmits a test signal into the display panel 100. The transistor 22 is disposed between the test signal pad 21 and the corresponding signal line 25. The source of the transistor 22 may be formed by a part of the signal line 25.

The scribe line 27 is disposed between the transistors 22 and the signal lines 25.

In some embodiments, the transistor 22 is an N-type transistor or a P-type transistor. Specifically, the transistor 22 used in all embodiments of the present application may be a thin film transistor, a field effect transistor, or other devices with the same characteristics. Since the source and the drain of the transistor 22 used here are symmetrically arranged, the source and the drain are interchangeable. In addition, in the embodiment of the present application, in order to distinguish two poles of the transistor 22 except for the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. In the form shown in the drawing, the transistor 22 has a gate at its middle, a source at one end connected to the signal line 25, and a drain at one end connected to the test signal pad 21. Alternatively, when the transistor 22 is a P-type transistor, the gate is turned on when the gate is at a low level, and is turned off when the gate is at a high level. When the transistor 22 is an N-type transistor, the gate is turned on when the gate is at a high level and is turned off when the gate is at a low level.

Specifically, referring to fig. 3, fig. 3 is a schematic cross-sectional structure of the transistor shown in fig. 2 along a section line XX'. The transistor 22 includes a substrate base 221. The substrate base 221 is provided with a buffer layer 222. The buffer layer 222 is provided with an active layer 223 on a side thereof away from the substrate base 221. The side of the active layer 223 remote from the base substrate 221 is provided with a first insulating layer 224. The first insulating layer 224 completely covers the active layer 223. A gate electrode 225 is disposed on a side of the first insulating layer 224 away from the base substrate 221. The side of the gate electrode 225 away from the base substrate 221 is provided with a second insulating layer 226. The second insulating layer 226 completely covers the gate electrode 225. The source 227 and the drain 228 are disposed on the second insulating layer 226 at the same layer and are symmetrical with respect to the gate 225. The second insulating layer 226 is provided with a first via 2261 and a second via 2262, which extend into the first insulating layer 224 to expose a surface of the active layer 224 on a side away from the substrate base 221, respectively. The source and drain

electrodes

227 and 228 are in contact with the active layer 224 through first and second via

holes

2261 and 2262, respectively.

The source 227, the drain 228 and the orthographic projection of the gate 225 on the substrate 221 are partially overlapped. It should be noted that orthographic projections of the source 227, the drain 228 and the gate 225 on the substrate 221 may not coincide completely, so as to avoid generating parasitic capacitance.

In the embodiment of the present application, the transistor 22 is a bottom gate type structure. Note that the transistor 22 may have a top gate structure. Those skilled in the art can make corresponding selections according to the design of the test circuit of the actual display panel. The gate 225, the source 227, and the drain 228 may be made of metal or indium tin oxide. The material of the active layer 223 may be low temperature polysilicon, high temperature polysilicon, metal oxide, organic semiconductor, or the like. As the base substrate 221, a glass substrate can be used if it is a hard substrate. When the base substrate 221 is a flexible substrate, a material such as ultra-thin glass or a polyimide film can be used. The embodiment of the present application is not particularly limited to this.

It is understood that the control signal pad 24 is connected to the common gate 23, and the control signal pad 24 inputs a control signal to the common gate 23 to simultaneously control the on and off of the plurality of transistors 22.

It should be noted that, specific numbers of the test signal pads 21, the transistors 22 and the control signal pads 24 in the embodiment of the present application are not particularly limited, and the numbers of the structures shown in fig. 2 are merely examples, and can be designed and adjusted by those skilled in the art according to actual situations, and are not described herein again.

The embodiment of the application provides a display panel test circuit, set up transistor 22 between test signal pad 21 and corresponding signal line 25, even remaining electrically conductive foreign matter makes the short circuit take place between the signal line 25 when cutting the display panel mother board, as shown in fig. 4, also can close transistor 22 through control signal pad 24 input control signal, make the circuit disconnection between a plurality of test signal pads 21 and corresponding signal line 25, test signal pad 21 short circuit has been avoided, display panel's display effect has been improved.

In the embodiment of the present application, each transistor 22 includes a source/drain region 22A, and a plurality of source/drain regions 22A are spaced apart from each other. The common gate 23 extends across the source/drain regions 22A. It should be noted that the specific structure of the transistor 22 is not particularly limited as long as the transistor 22 can control the connection state between the test signal pad 21 and the corresponding signal line 25, and those skilled in the art can design the transistor according to the specific position where the transistor 22 is disposed.

In the embodiment of the present application, the common gate 23 includes a plurality of first gate portions 231 and a plurality of second gate portions 232. The first gate portion 231 is located in a source-drain region of the transistor 22. The second gate portions 232 are disposed between the adjacent first gate portions 231. Wherein the width of the second gate portion 232 is equal to the width of the first gate portion 231.

It is understood that the second gate portion 232 is connected to the adjacent first gate portion 231, and may transmit a control signal as a signal transmission wire. Thus, the common gate 23 can serve as both the gate of the transistor 22 and the signal transmission line for controlling the signal pad 24. By reducing the additional signal transmission lines, the problem of resistance-capacitance delay (RC delay) caused by the signal transmission lines is avoided, so that each transistor 22 can simultaneously receive the control signal inputted through the control signal pad 24. In addition, since the first gate portion 231 and the second gate portion 232 have the same width, the control signal is less lost during transmission, and the transmission speed is faster.

In addition, the common gate 23 further includes a third gate portion 233, and the third gate portion 233 is used for connecting the control signal pad 24. The third gate portion 233 has an L-shaped structure. One end of the third gate portion 233 is connected to an end of the outermost first gate portion 232. The other end of the third gate portion 233 is connected to the control signal pad 24.

Note that, if the control signal pad 24 is not provided on the same layer as the common gate 23, a through hole is opened, and the third gate portion 233 is connected to the control signal pad 24 through the through hole.

Further, the first gate portion 231, the second gate portion 232, and the third gate portion 233 are formed at the same layer. In this configuration, the first gate portion 231, the second gate portion 232, and the third gate portion 233 can be formed simultaneously by the same process, thereby reducing the number of manufacturing steps of the display panel.

In some embodiments, there are two control signal pads 24. Wherein, a plurality of test signal pads 21 are disposed between two control signal pads 24, and a plurality of test signal pads 21 are disposed at intervals.

Specifically, the distance between adjacent test signal pads 21 is equal to the distance between the control signal pad 24 and the test signal pad 21 adjacent thereto. This structure can carry out effective utilization to the space, does benefit to and realizes narrow frame. Meanwhile, the control signal pads 24 are symmetrically arranged with respect to the test signal pad 21, so that the time for receiving the control signal by the plurality of transistors 22 can be more uniform.

It should be noted that one or more control signal pads 24 may be provided. Control signal pads 24 may also be disposed between test signal pads 21. The distance between adjacent test signal pads 21, and the distance between the control signal pad 24 and the test signal pad 21 adjacent thereto may not be equal. This is not specifically set in the embodiments of the present application.

In some embodiments, please refer to fig. 5, and fig. 5 is another structural schematic diagram of the display panel test circuit provided in the embodiments of the present application. The display panel test circuit shown in fig. 5 is different from the display panel test circuit shown in fig. 2 in that: the display panel test circuit shown in fig. 5 further includes a test area 26.

Wherein test area 26 is located below the plurality of transistors 22. The plurality of transistors 22 are connected to the test area 26 by a plurality of corresponding signal lines 25.

On this basis, the control signal pad 24 includes a first control signal pad 241 and a second control signal pad 242. The first control signal pad 241 is disposed at one side of the cutting mark line 27. The second control signal pad 242 is disposed at the other side of the cutting mark line 27. Two of the first control signal pads 241 and two of the second control signal pads 242 are provided. The first control signal pads 241 are symmetrically disposed at both sides of the test signal pad 22. The second control signal pads 242 are symmetrically disposed on both sides of the test region 26.

It is understood that, in the embodiment of the present application, the common gate 24 further includes a fourth gate portion 234. The fourth gate portion 234 is disposed corresponding to the second control signal pad 242. One end of the fourth gate portion 234 is connected to the third gate portion 233. The other end of the fourth gate portion 234 extends to the test region 26 and is connected to the second control signal pad 242.

Referring to fig. 6, fig. 6 is a flowchart of a testing method for a testing circuit of a display panel according to an embodiment of the present disclosure. With reference to fig. 1 to 5, the method for testing the display panel test circuit includes the following steps:

s101, inputting a control signal to the common grid through the control signal pad, and controlling the transistor to be closed so as to disconnect the lines between the plurality of test signal pads and the corresponding signal lines.

In the method steps of the embodiments of the present application, the test signal pads, the transistors, the common gate, the control signal pads, the scribe lines, and the like can refer to the above contents, and are not described herein again.

In some embodiments, the display panel test circuit provided herein may be disposed in the panel test area 40 as shown in fig. 1. Referring to fig. 2 and 4, when the mother board of the display panel is cut into a plurality of small-sized panels along the cutting mark line 27, and a conductive foreign object is generated at the cutting mark line 27 to cause a short circuit between the signal lines 25, a potential signal is input to the common gate 23 through the control signal pad 24 to turn off the transistor 22. The source and drain of the transistor 22 are disconnected, so that the circuit between the test signal pad 21 and the corresponding signal line 25 can be effectively disconnected, the test signal during the panel lighting test is not affected, and the display effect of the display panel is improved.

It should be noted that the potential signal may be a high potential signal or a low potential signal, which is determined by the structure of the transistor 22, and reference may be made to the above contents, which are not described herein again.

In some embodiments, the display panel test circuit proposed in the present application may also be disposed in the bonding area 50 as shown in fig. 1. It should be noted that, when the bonding area 50 is provided with the array test circuit, the bonding area 50 needs to be provided with the display panel test circuit.

Referring to fig. 4 and 5, the test area 26 is provided with array test circuits. When performing an array test, a control signal is input to the common gate 23 through the second control signal pad 242 to turn on the transistor 22. The test signal pad 21 receives the test signal and transmits the test signal to the inside of the display panel, thereby completing the array test. The display panel mother board is then cut into a plurality of small-sized display panels along the cutting mark lines 27 by using a laser cutting technique, and the test area 28 and the second control signal pads 242 are removed. At this time, in order to prevent the test signal pad 21 from being short-circuited by the conductive foreign object generated by the laser cutting, another control signal is input to the common gate 23 through the first control signal pad 241, so that the transistor 22 is turned off. The source and the drain of the transistor 22 are disconnected, so that the line between the test signal pad 21 and the short-circuited signal line 25 can be effectively disconnected, and the display effect of the display panel is prevented from being influenced.

Specifically, the second control signal pad 242 provides a low signal to turn on the transistor 22. The first control signal 241 provides a high signal to turn off the transistor 22. Alternatively, the second control signal pad 242 provides a high signal to turn on the transistor 22. The first control signal 241 provides a low signal to turn off the transistor 22. The potential signal is determined by the structure of the transistor 22, and reference is made to the above, which is not described herein again.

In some embodiments, the display panel test circuit proposed in the present application may be disposed in both the panel test area 40 and the bonding area 50 shown in fig. 1. Referring to fig. 2, 4 and 5, after the display panel mother board is cut into a plurality of small-sized panels along the cutting mark line 27, due to the generation of conductive foreign matters, short circuits between the plurality of signal lines 25 may occur in both the panel test area 40 and the bonding area 50, and thus the plurality of test signal pads 21 are shorted. Therefore, the panel test area 40 and the bonding area 50 interfere with each other during the test, causing errors in the test signals.

To solve this problem, when a panel lighting test is performed, a control signal is input to the common gate 23 through the test signal pad 241 in the bonding region 50, and the line between the control signal pad 24 and the signal line 25 in the bonding region 50 is disconnected. Therefore, the problem of short circuit among the test signal pads 21 in the binding area 50 is avoided, and the interference of the binding area 50 on the panel lighting test signal in the panel test area 40 is avoided. Then, a panel lighting test is performed in the panel test area 40, which may be referred to above specifically and will not be described herein again. The embodiment of the application effectively avoids the risk of test signal errors caused by short circuit of the test signal pad 21, and improves the test accuracy.

It should be noted that the potential signal may be a high potential signal or a low potential signal, which is determined by the structure of the transistor 22, and specific reference may be made to the above contents, which is not described herein again.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A display panel test circuit, comprising:

the test signal pads are connected with the display panel;

a control signal pad connected with the common gate.

2. The display panel test circuit according to claim 1, wherein each transistor comprises a source drain region, and a plurality of the source drain regions are arranged at intervals;

wherein the common gate crosses over the plurality of source and drain regions.

3. The display panel test circuit according to claim 2, wherein the common gate includes a plurality of first gate portions and a plurality of second gate portions, the first gate portions being located in the source-drain regions, the second gate portions being disposed between adjacent first gate portions;

4. The display panel test circuit of claim 3, wherein the common gate further comprises a third gate portion for connecting to the control signal pad.

5. The display panel test circuit of claim 4, wherein the first gate portion, the second gate portion, and the third gate portion are formed in the same layer.

6. The display panel test circuit according to claim 1, wherein the number of the control signal pads is two;

7. The display panel test circuit of claim 1, wherein a cutting mark line is further disposed between the plurality of transistors and the plurality of signal lines.

8. The display panel test circuit of claim 7, wherein the control signal pads comprise a first control signal pad and a second control signal pad;

wherein the first control signal pad is disposed at one side of the cutting mark line, and the second control signal pad is disposed at the other side of the cutting mark line.

9. The display panel test circuit of claim 1, wherein the transistor is an N-type transistor or a P-type transistor.

10. A method for testing a display panel test circuit, applied to the display panel test circuit according to any one of claims 1 to 9, wherein a control signal is input to the common gate through the control signal pads to control the transistors to be turned off, so that the circuit between the plurality of test signal pads and the corresponding signal lines is disconnected.