CN114284248A

CN114284248A - Display panel

Info

Publication number: CN114284248A
Application number: CN202111629337.5A
Authority: CN
Inventors: 张向向
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-04-05

Abstract

The embodiment of the invention provides a display panel. The display panel comprises a substrate, a shielding layer and a thin film transistor device layer, wherein a thin film transistor is arranged in the thin film transistor device layer corresponding to the display area, the thin film transistor comprises an active layer, a grid electrode and a source/drain electrode, the display panel further comprises a first through hole and a second through hole, the first through hole is arranged in the bending area, the second through hole is arranged on the shielding layer, the source/drain electrode is electrically connected with the shielding layer through the second through hole, the shielding layer is arranged, and the source/drain electrode is connected with one end of the shielding layer, so that various performances of the display panel are improved.

Description

Display panel

Technical Field

The invention relates to the technical field of manufacturing of display panels, in particular to a display panel.

Background

With the development of flexible display screen technology, people have made higher requirements on the quality and performance of display panels and devices.

Organic light-emitting diode (OLED) devices are used in many fields because they have advantages of light weight, wide viewing angle, high light-emitting efficiency, and the like, compared with conventional Liquid Crystal Displays (LCDs). In order to improve the market competitiveness of liquid crystal display panel products, flexible liquid crystal display panels are added to various liquid crystal display panel manufacturers for development. The organic light emitting diode device comprises an array substrate, wherein a plurality of thin film transistor devices and connecting touch wires are arranged in the array substrate. Therefore, the performance of the thin film transistor device directly affects the performance of the whole light emitting device. Therefore, in the development process, various problems are easily caused, when the thin film transistor in the display panel is in normal operation, static electricity is easily generated inside the device, and the static electricity affects the normal operation of the thin film transistor, thereby causing the problem that the panel driving circuit is abnormal in operation. In the prior art, an electrostatic protection circuit is usually arranged in a panel, and the electrostatic protection circuit can play an electrostatic protection role after the array substrate is manufactured into a display panel in all manufacturing processes, and cannot play an electrostatic protection role on a thin film transistor in the manufacturing process of the panel, so that the electrostatic protection role cannot be effectively played on the panel.

In summary, in the prior art, the display panel is often affected by static electricity during the preparation and formation of the display panel and the prepared display panel, so that the thin film transistor in the panel cannot work normally, and the performance of the display panel is affected.

Disclosure of Invention

Embodiments of the present invention provide a display panel, so as to effectively solve the problems that the display panel is easily affected by static electricity and the performance of the display panel is not ideal.

In order to solve the above technical problem, the technical method provided by the embodiment of the present invention is as follows:

in a first aspect of the embodiments of the present invention, a display panel is provided, which includes a display region, a bending region, and a fan-out routing region, where the display region, the bending region, and the fan-out routing region are sequentially disposed, and the display panel includes:

a substrate;

a shield layer disposed on the substrate, and,

the thin film transistor device layer is arranged on one side, far away from the substrate, of the shielding layer and comprises a thin film transistor and a metal layer, the thin film transistor is correspondingly arranged in the display area and comprises an active layer, a grid electrode and a source/drain electrode, and the projection of the active layer on the substrate is positioned in the orthographic projection of the shielding layer on the substrate;

the display panel further comprises a first via hole and a second via hole, the first via hole and the second via hole are arranged on one side of the thin film transistor, the first via hole is arranged in the bending area, the second via hole is correspondingly arranged on the shielding layer, and the metal layer is electrically connected with the shielding layer through the second via hole.

According to an embodiment of the present invention, the shielding layer is disposed in the display area, the second via hole is disposed in the display area, and the second via hole is correspondingly disposed in an edge area of the shielding layer.

According to an embodiment of the present invention, the second via hole is configured as a stepped hole.

According to an embodiment of the present invention, the step platform corresponding to the step hole and the active layer are located on the same film layer.

According to an embodiment of the present invention, an aperture of a side of the stepped hole close to the substrate is smaller than an aperture of a side of the stepped hole far from the substrate.

According to an embodiment of the invention, a projection of the active layer on the substrate is located in an orthographic projection of the shielding layer on the substrate, one end of the shielding layer is arranged in the display area, and the other end of the shielding layer extends into the fan-out routing area.

According to an embodiment of the invention, the second via hole is arranged in the fan-out routing area, the second via hole is correspondingly arranged in the edge area of the shielding layer, and the first via hole is arranged on the shielding layer.

According to an embodiment of the invention, the shielding layer is arranged patterned on the substrate.

According to an embodiment of the invention, the source/drain electrodes are arranged in the display area and the fan-out routing area, and the source/drain electrodes are electrically connected with the active layer and the shielding layer through corresponding via holes.

According to an embodiment of the present invention, the display panel further includes a connection terminal and a lead, the connection terminal and the lead are disposed in the fan-out wiring region, one end of the lead is connected to the metal layer, and the other end of the lead is connected to the connection terminal.

In summary, the embodiments of the present invention have the following beneficial effects:

the embodiment of the invention provides a display panel. The display panel comprises a substrate, a shielding layer and a thin film transistor device layer, wherein a thin film transistor is arranged on the thin film transistor device layer corresponding to the display area, the thin film transistor comprises an active layer, a grid electrode and a source/drain electrode, the display panel further comprises a first through hole and a second through hole, the first through hole is arranged in the bending area, the second through hole is arranged on the shielding layer, the source/drain electrode is electrically connected with the shielding layer through the second through hole, the shielding layer is arranged, and the source/drain electrode is connected with one end of the shielding layer, so that static electricity in the display panel is reduced, and various performances of the display panel are improved.

Drawings

The technical solution and other advantages of the present invention will become more apparent from the detailed description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a display panel according to an embodiment of the present invention;

fig. 2 is a schematic plan view of a display panel according to an embodiment of the present invention;

fig. 3 is a schematic view of a film structure corresponding to another display panel according to an embodiment of the invention;

fig. 4 is a schematic diagram of a shielding layer structure of a display panel according to an embodiment of the invention;

fig. 5 is a film structure diagram corresponding to a bending region and a vicinity of a fan-out routing region according to an embodiment of the present invention.

Detailed Description

The following disclosure provides different embodiments or examples to implement different structures of the present invention, which are shown in the drawings of the embodiments of the present invention. In order to simplify the present invention, the components and arrangements of specific examples are described below. In addition, the present invention provides examples of various specific processes and materials, and one of ordinary skill in the art will recognize that other processes may be used. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

With the continuous development of display panel preparation technology, people put higher demands on various performances and qualities of display panels. The prepared display panel is expected to have better quality and better comprehensive performance.

When the thin film transistor devices in the display panel prepared by the prior art normally work, certain interference can be formed among the devices in the film layer, for example, the reliability of the thin film transistor driven by current is controlled by the electrical characteristics of the flexible substrate and the electrostatic influence of other charged layers. Further, the reliability of the thin film transistor is obviously reduced, and the performance of the display panel is reduced.

The embodiment of the invention provides a display panel, which is used for effectively improving the reliability and the comprehensive performance of the display panel.

As shown in fig. 1, fig. 1 is a display panel according to an embodiment of the present invention. The display panel includes a substrate, a shielding layer 115, and a thin film transistor device layer 11.

Specifically, the substrate provided in the embodiment of the present invention is a flexible substrate. Wherein the substrate may comprise a multi-layer composite film structure. Such as a first buffer layer 100, a first substrate 101, and a second buffer layer 102. Wherein the first substrate 101 is disposed on the first buffer layer 100, the second buffer layer 102 is disposed on the first substrate 101, and a composite film layer formed by the first buffer layer 100, the first substrate 101 and the second buffer layer 102 constitutes the substrate in the embodiment of the present invention. Specifically, the first buffer layer 100 and the second buffer layer 102 may be both flexible film layers, such as a flexible polyimide film layer. The first base 101 is a supporting film layer with certain rigidity, so that the substrate not only has good bending performance, but also has good supporting effect on various device layers thereon.

Further, a shield layer 115 is provided over the substrate. When the shielding layer 115 is provided, the shielding layer 115 may be provided in a sandwich structure. In the embodiment of the invention, the shielding layer 115 is disposed on the second buffer layer 102, and the second substrate 103 is disposed on the second buffer layer 102, wherein the second substrate 103 completely covers the shielding layer 115. And the film thickness of the shielding layer 115 is smaller than that of the second substrate 103, so that the shielding layer 115 is equivalently clamped in the second substrate 103.

In the embodiment of the invention, when the shielding layer 115 is disposed, the shielding layer 115 may be disposed on the second buffer layer 102 in a patterned manner.

Further, the display panel further includes a thin film transistor device layer 11. Wherein a thin film transistor device layer 11 is disposed over the second substrate 103. In the embodiment of the present invention, the thin film transistor device layer 11 includes a third substrate 104, an active layer 109, a first insulating layer 105, a first gate 112, a second insulating layer 106, and a planarization layer 107.

Specifically, the third substrate 104 is disposed on the second base 103, the active layer 109 is disposed on the third substrate 104, the first insulating layer 105 is disposed on the third substrate 104, and the first insulating layer 105 covers the active layer 109. Meanwhile, the first gate 112 is disposed on the first insulating layer 105, the second insulating layer 106 is disposed on the first insulating layer 105, and the second insulating layer 106 covers the first gate 112.

In the embodiment of the present invention, when the corresponding thin film transistor in the thin film transistor device layer 11 is disposed, the thin film transistor may have a dual gate structure. Specifically, the display panel further includes a second gate 113, the second gate 113 is disposed on the second insulating layer 106, and the second gate 113 is disposed corresponding to the first gate 112, for example, the second gate 113 is disposed on a corresponding film layer at a region above the first gate 112.

Further, a planarization layer 107 is disposed on the second insulating layer 106, and the planarization layer 107 covers the second gate 113. Meanwhile, a metal layer 116 is provided on the planarization layer 107. In an embodiment of the present invention, the metal layer 116 may include a source 110 and a drain 111 of the thin film transistor, wherein the source 110 and the drain 111 of the thin film transistor are electrically connected to the active layer through corresponding vias, and the metal layer 116 is further electrically connected to the shielding layer through corresponding vias.

In the embodiment of the present invention, when forming the thin film transistors 16 in the thin film transistor device layer 11, corresponding via structures are respectively disposed above the active layer 109. The source and drain

electrodes

110 and 111 of the thin film transistor 16 are electrically connected to the active layer 109 through corresponding via structures. In the embodiment of the invention, when the first gate 112 is disposed, a plurality of the first gates 112 may be prepared in the same layer, such as two first gates 112 shown in fig. 1, and another first gate may be disposed on one side of the first gate 112. Thereby finally forming the structure of the thin film transistor device layer 11 and the thin film transistor 16 inside the device layer provided in the embodiment of the present invention.

Specifically, as shown in fig. 2, fig. 2 is a schematic plan view of a display panel provided in an embodiment of the present invention. In conjunction with the film layer structure of figure 1. The display panel 10 in the embodiment of the invention includes a display area 12, a bending area 13 and a fan-out routing area 14. Wherein the bending region 13 is disposed at one side of the display region 12, such as the bending region 13 is disposed at the bottom edge of the display panel 10, meanwhile, the fan-out routing region 14 is disposed at one side of the bending region 13, and the bending region 13 connects the display region 12 and the fan-out routing region 14.

In the embodiment of the present invention, the display area 12 mainly displays a picture, the bending area 13 can be bent to a certain degree, and a plurality of connection lines 141 are disposed in the fan-out routing area 14. The connection lines 141 are connected to the respective signal lines drawn out of the display area 12 of the display panel. Specific connections are not shown directly in embodiments of the present invention. When the bottom of the display panel is bent, such as when the panel is subjected to a bonding process, the bent region 13 is mainly a region where the bending occurs.

Further, in the embodiment of the present invention, a first via 23 and a second via 24 are further disposed on one side of the thin film transistor 16.

Specifically, the first via 23 is disposed in the bending region 13 of the display panel. When the first via hole 23 is provided, the first via hole 23 penetrates through each layer of the thin film transistor device layer 11. For example, the first via 23 sequentially penetrates through the planarization layer 107, the second insulating layer 106, the first insulating layer 105, the third substrate 104, and the second base 103 from top to bottom. And the surface of the second buffer layer 102 is exposed. In the embodiment of the present invention, when the first via hole 23 is disposed, the first via hole 23 may be disposed in the middle of the bending region 13, so that when the display panel is bent in the region, the via hole may effectively reduce the stress inside the film layer.

Specifically, when the plurality of first vias 23 are disposed, the first vias 23 may be disposed in an array in the bending region of the display panel 10. And the distance between two adjacent first vias 23 may be set to be the same. Meanwhile, the sizes of the via holes can be set to be the same or different, and the via holes can be specifically designed according to actual products. In the embodiment of the present invention, the opening area of each via hole on the planarization layer 107 is the same as an example.

In the embodiment of the present invention, when the first via hole 23 is provided, the first via hole 23 is provided as a stepped via hole. If the first via hole 23 includes an upper stepped hole 21 and a lower stepped hole 22, the hole center lines corresponding to the upper stepped hole 21 and the lower stepped hole 22 may coincide with each other, and when the lower stepped hole 22 is provided, the stepped terrace corresponding to the stepped hole 22 and the active layer 109 of the thin film transistor 16 may be provided on the same film layer.

Specifically, the aperture of the upper stepped hole 21 may be larger than that of the lower stepped hole 22, so that when the bending region 13 corresponding to the stepped hole is bent, the film layer at the position with the larger aperture at the upper portion is more easily bent, and the bending performance of the display panel may be effectively improved.

In the embodiment of the present invention, the upper step hole 21 sequentially penetrates through the planarization layer 107, the second insulating layer 106, and the first insulating layer 105. The lower step hole 22 sequentially penetrates through the third substrate 104 and the second base 103, and exposes a surface of the second buffer layer 102.

Further, the display panel provided in the embodiment of the present invention further includes a second via hole 24, and the second via hole 24 is disposed on one side of the thin film transistor 16. When the second via 24 is disposed, it may be correspondingly disposed according to the structure of the disposed shielding layer 115.

Specifically, referring to the film layer structure diagram in fig. 1, when the shielding layer 115 is disposed, and the shielding layer 115 is disposed in the display area 12, one end of the shielding layer is disposed corresponding to the active layer 109 of the thin film transistor 16, and the other end extends to the edge of the display area near the bending area 13. And the projection of the active layer 109 onto the substrate is entirely within the projection of the shield layer 115 onto the substrate. The second via 24 is correspondingly disposed at an edge region of the shield layer 115.

In order to reduce the processes in the display panel preparation process, the second via hole 24 may be formed by an etching process corresponding to the first via hole 23. That is, the second via hole 24 is also provided as a stepped hole, the second via hole 24 includes a first sub-hole 1071 and a second sub-hole 1072, the first sub-hole 1071 has a larger aperture than the second sub-hole 1072, and the second sub-hole 1072 is provided on the first sub-hole 1071. When etching is performed, the first sub-hole 1071 and the lower stepped hole 22 are simultaneously etched and formed, and the second sub-hole 1072 and the upper stepped hole 21 are simultaneously etched and formed, thereby effectively simplifying the number of times of masking the display panel.

Meanwhile, the metal layer 116 disposed on the planarization layer 107 is electrically connected to the shield layer 115 through the second via 24.

As shown in fig. 3, fig. 3 is a schematic view of a film structure corresponding to another display panel according to an embodiment of the present invention. In conjunction with the film layer structure in fig. 1, when the shielding layer 115 is disposed, one end of the shielding layer 115 is correspondingly disposed in the display area 12 below the active layer 109, and the other end of the shielding layer 115 extends into the fan-out routing area 14, so that the shielding layer 115 crosses the bending area 13 between the display area 12 and the fan-out routing area 14.

Correspondingly, the second via 24 is disposed in the fan-out routing area 14, and the second via 24 is correspondingly disposed at one end of the shielding layer 115 and etched to the surface of the shielding layer 115. Meanwhile, the metal layer 116 is electrically connected to the shielding layer 115 through the second via 24. Since the metal layer 116 is simultaneously formed on the same film as the source or drain of the tft 16 and simultaneously formed with the source or drain, the source or drain is electrically connected to the shielding layer 115 through the second via 24. In the embodiment of the present invention, the metal layer connected to the shielding layer 115 is directly connected through the metal layer lead corresponding to the source or the drain without going through the common electrode layer in the display panel.

As shown in fig. 4, fig. 4 is a schematic view of a shielding layer structure of a display panel according to an embodiment of the present invention. In the embodiment of the present invention, since the shielding layer 115 spans a plurality of regions, in order to improve the performance of the display panel, the shielding layer 115 is patterned when the shielding layer structure is prepared. Specifically, the shielding layer 115 may be disposed on the second buffer layer 102 of the display panel 10 in a patterned manner. As shown in the structure of fig. 4, the shielding layer 115 is patterned to have a hollow-out structure, and the hollow-out region can be configured to have various graphic structures, such as a square, a circle, an ellipse, and the like. When the display panel is deformed such as bent in the region, the patterned shielding layer 115 can reduce the bending stress of the layer, thereby improving the performance of the display panel. In the embodiment of the present invention, the shielding layer 115 is patterned in the display region, but the shielding layer in the region is not overlapped by a via hole, after the edges of the display panel are connected, the shielding layer is overlapped by a via hole in the metal layer in the bending region through the corresponding metal layer lead wire bending region, and the lead wire is led to the integrated chip in the fan-out wiring region.

As shown in fig. 5, fig. 5 is a film layer structure diagram corresponding to the vicinity of the bending area and the fan-out routing area in fig. 2 according to an embodiment of the present invention. In the embodiment of the present invention, a fan-out trace 141 is further disposed in the fan-out trace area 14, and a plurality of connection terminals 145 are connected to one end of the fan-out trace, and the connection terminals 145 are electrically connected to the source or the drain through corresponding leads. And then provide various control signals for the display panel and realize the drive of the display panel.

When the display panel is in normal operation, and when the potential of the shielding layer provided in the embodiment of the present invention is fixed, the voltage can be controlled according to the characteristics of the thin film transistor in the display panel, for example, when the voltage of the panel in normal operation is positive 4.6V, the threshold voltage has a negative bias of 0.7V, and according to the actual characteristics of the panel, the negative bias of 0.7V will cause the bias of the thin film transistor to be enhanced, and the reliability will be deteriorated. Therefore, the potential of the shielding layer can be adjusted, for example, the potential of the shielding layer is positive 1V or 0V, so that the normal operation of the thin film transistor is ensured. Meanwhile, when the shielding layer regulates and controls the potential and the output of the control chip IC is synchronous, the source electrode or the drain electrode of the thin film transistor and the shielding layer can keep the same potential, so that the problem of reliability attenuation caused by the bias voltage of the thin film transistor is reduced, and the performance of devices in the display panel is improved.

Further, in order to reduce the influence of the first via holes 23 on the film layer, in the embodiment of the present invention, a flexible material, such as an adhesive layer, may be further filled in each first via hole 23, the film layer in the bending region 13 is still a continuous film layer through the adhesive layer, and meanwhile, when the display panel is bent, the adhesive layer may generate elastic strain under a small acting force, and therefore, the adhesive layer may not affect various performances of the display panel.

Further, an embodiment of the present invention further provides a display device, where the display device includes a display panel, and the display panel is a panel provided in the embodiment of the present invention. The display device has better comprehensive performance.

The display panel provided by the embodiment of the present invention is described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A display panel, comprising a display area, a bending area and a fan-out routing area, wherein the bending area is disposed between the display area and the fan-out routing area, the display panel comprises:

a substrate;

a shield layer disposed on the substrate, and,

the thin film transistor device layer is arranged on one side, far away from the substrate, of the shielding layer and comprises a thin film transistor and a metal layer, the thin film transistor is correspondingly arranged in the display area and comprises an active layer, a grid electrode and a source/drain electrode;

2. The display panel according to claim 1, wherein the shielding layer is disposed in the display area, the second via hole is disposed in the display area, and the second via hole is correspondingly disposed in an edge area of the shielding layer.

3. The display panel according to claim 2, wherein the second via hole is provided as a stepped hole.

4. The display panel of claim 3, wherein the step platform corresponding to the step hole is located on the same film layer as the active layer.

5. The display panel according to claim 3, wherein an aperture of a side of the stepped hole close to the substrate is smaller than an aperture of a side of the stepped hole remote from the substrate.

6. The display panel of claim 1, wherein a projection of the active layer on the substrate is located within an orthographic projection of the shielding layer on the substrate, and one end of the shielding layer is disposed within the display area and the other end of the shielding layer extends into the fan-out routing area.

7. The display panel of claim 6, wherein the second via holes are disposed in the fan-out routing area, the second via holes are correspondingly disposed in an edge area of the shielding layer, and the first via holes are correspondingly disposed on the shielding layer.

8. The display panel of claim 1, wherein the shielding layer is patterned on the substrate.

9. The display panel of claim 1, wherein the metal layer is disposed in the display area and the fan-out routing area, and the metal layer is electrically connected to the active layer and the shielding layer through corresponding vias.

10. The display panel according to claim 1, wherein the display panel further comprises a connection terminal and a lead, the connection terminal and the lead are provided in the fan-out wiring region, one end of the lead is connected to the metal layer, and the other end of the lead is connected to the connection terminal.