CN112436050B

CN112436050B - Display panel and display device

Info

Publication number: CN112436050B
Application number: CN202011574476.8A
Authority: CN
Inventors: 徐涛
Original assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Current assignee: Kunshan New Flat Panel Display Technology Center Co Ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2022-08-19
Anticipated expiration: 2040-12-28
Also published as: CN112436050A

Abstract

The invention provides a display panel and a display device, the display panel comprises: an array substrate provided with a first terminal part including a plurality of first terminals; the flexible circuit board is provided with a second terminal part, the second terminal part comprises a plurality of second terminals, and each second terminal corresponds to one first terminal one by one; each second terminal comprises a first area and a second area which are connected, the width of the second area is smaller than that of the first area, conductive adhesive is arranged on the first area and the first terminal, and the projection of the second area on the array substrate is not overlapped with the projection of the first terminal on the array substrate.

Description

Display panel and display device

Technical Field

The invention belongs to the technical field of display, and particularly relates to a display panel and a display device.

Background

An Organic Light-Emitting Diode (OLED) display device is a device that uses a reversible color change phenomenon generated by an Organic semiconductor material under the driving of a current to realize graphic display. The OLED display device has the advantages of ultra-light weight, ultra-thin thickness, high brightness, large viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple process, few raw materials, high light emitting efficiency, wide temperature range and the like, so the OLED display technology is considered as a new generation display technology with the greatest development prospect.

The basic structure of the OLED display device includes: an anode layer, a cathode layer, and an organic light emitting layer sandwiched between the anode layer and the cathode layer. Generally, the anode layer is formed on the flat layer of the driving backplane, and a patterning process is performed to form a plurality of separate anode electrodes (or pixel electrodes), each corresponding to one pixel unit, exposed from a pixel area of the pixel definition layer on the flat layer to contact the organic light emitting layer.

In the prior art, a COF (tape on film) package (COF) technology places a display driver IC chip into a Flexible Printed Circuit (FPC) cable, and turns over the display driver IC chip to a position below a display panel by using the characteristics of the FPC, and since the space occupied by the IC chip on a driver backplane is released, the frame width of at least 1.5 mm can be generally reduced.

At present, a gold finger is arranged on a Flexible Printed Circuit (FPC), and is pressed to a corresponding position with a COF bonding terminal arranged on a driving backplane in a display panel through an ACF (anisotropic conductive film) to form a binding structure, so that control of an external signal on an OLED display screen is realized; however, in the use of a Flexible Printed Circuit (FPC), the aforementioned bonding structure has a risk of short-circuiting, which affects the use.

Disclosure of Invention

The invention aims to provide a display panel and a display device, which can effectively reduce the probability of short circuit risk of a binding structure by reducing the width of a specific area of a golden finger on a flexible circuit board.

In order to solve the above problems, the present invention provides a display panel, including: an array substrate provided with a first terminal part including a plurality of first terminals; the flexible circuit is provided with a second terminal part, the second terminal part comprises a plurality of second terminals, and each second terminal corresponds to one first terminal one by one; each second terminal comprises a first area and a second area which are connected, the width of the second area is smaller than that of the first area, and after the first area and the first terminal corresponding to the first area are pressed through conductive adhesive, the projection of the second area on the array substrate is not overlapped with the projection of the first terminal on the array substrate.

As an alternative solution, the second region of the second terminal is connected to a central region in the width direction of the first region.

As an optional technical solution, a ratio of a width of the first region to a width of the second region of the second terminal is 1: (0.2-0.6).

As an optional technical solution, the thickness of the film layer in the second area is greater than that of the film layer in the first area.

As an optional technical solution, the array substrate further includes a flat layer, wherein the plurality of first terminals are disposed adjacent to an edge of the flat layer, and the plurality of first terminals have a predetermined distance from the edge of the flat layer.

As an optional technical solution, the second region extends from the first region toward the edge of the flat layer and crosses the edge of the flat layer.

As an optional technical solution, the array substrate further includes an anode layer formed on the planarization layer.

As an optional technical solution, the second terminal further includes a third region, the third region is connected to one end of the second region far from the first region, and a width of the third region is greater than a width of the second region.

As an optional technical solution, an edge of the third area extends and protrudes beyond an edge of the array substrate.

As an optional technical solution, the first region, the second region and the third region of the second terminal are made of the same material and are integrally formed.

The invention also provides a display device which comprises the display panel.

Compared with the prior art, the display panel comprises the array substrate and the flexible circuit board, the width of a second area, which is not in press fit connection with the first terminal, of the second terminal on the flexible circuit board is narrowed, the effective contact area of the second area and the etching residue of the anode layer on the array substrate is reduced, the problem that the second terminal on the flexible circuit board is in transverse conduction and short circuit due to the fact that the second area is in etching residue conduction with the anode layer is avoided, and the probability of poor display of the display panel is reduced.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts,

fig. 1 is a schematic top view of a conventional array substrate and a circuit board before bonding by pressing;

FIG. 2 is a schematic top view of the array substrate and the circuit board of FIG. 1 bonded together by pressing;

FIG. 3 is a schematic top view illustrating an array substrate and a circuit board before being bonded together by pressing according to an embodiment of the invention;

fig. 4 is a schematic top view illustrating the array substrate and the circuit board bonded by pressing in accordance with an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of the circuit board shown in FIG. 3 along view A;

FIG. 6 is a schematic cross-sectional view of the circuit board shown in FIG. 3 taken along a view angle B;

fig. 7 is a schematic top view illustrating a bonded array substrate and a circuit board after being pressed and bonded according to another embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.

As described in the background art, when the Flexible Printed Circuit (FPC) is used, a bonding structure formed by pressing a gold finger provided on the Flexible Printed Circuit (FPC) and a COF bonding terminal provided on a driving backplane of the display panel may have a risk of short circuit, thereby increasing the probability of poor display of the display. In order to reduce the probability of poor display of the display, the applicant of the present application has made a lot of research, and occasionally, etching residues of the anode layer may exist near the outer edge of the COF bonding terminal on the driving backplane in the display panel, and it is the etching residues of the anode layer that contact with the gold fingers arranged on the flexible circuit board (FPC) to cause a binding short circuit.

The display device comprises a driving backboard, wherein the driving backboard comprises a substrate layer, a TFT layer, a planarization layer and an anode layer. Since the planarization layer is usually an organic layer, which is not conducive to cutting the panel, in general, the planarization layer does not extend to the edge of the panel, and thus the edge of the planarization layer is often located between the bonding Pad and the edge of the substrate layer.

In the process of preparing the anode on the planarization layer, an anode film layer is usually manufactured first, and is subjected to photolithography and development, and when a required anode pattern is obtained, because yellow light irradiation is insufficient at the edge position of the planarization layer, a photoresist residue occurs, and an anode layer etching residue occurs. The etching residue has no influence on the function of the driving backboard, but after the bonding Pad close to the etching residue on the driving backboard is pressed with the gold finger of the COF, the gold finger of the COF is easy to have a transverse conduction short circuit under the action of the conductive layer, so that the abnormal display problem is caused.

Specifically, as shown in fig. 1 and fig. 2, the driving backplane 10 is provided with a COF bonding terminal 12, which is pressed to a corresponding position with a gold finger 21 or the like on the flexible circuit board 20 by an ACF (anisotropic conductive film), so as to control the OLED display screen by an external signal.

Since the planarization layer 11 on the driving backplane 10 is an organic film layer, which is not conducive to cutting the driving backplane 10, the edge 111 of the planarization layer 11 often does not extend to the edge 101 of the display substrate 10, and the edge 111 of the planarization layer 11 is located approximately between the COF bonding terminal 12 of the display substrate 10 and the edge 101 of the display substrate 10. In addition, the anode layer is laminated on the surface of the planarization layer 11 away from the display substrate 10, and the anode layer has insufficient yellow light irradiation and residual photoresist in the patterning process corresponding to the edge 111 of the planarization layer 11, resulting in the existence of etching residue 13 in the anode layer.

After the COF bonding terminal 12 on the driving backplane 10 and the gold finger 21 on the flexible circuit board 20 are bonded by pressing, the etching residue 13 of the anode film layer easily causes the gold finger 21 to be in a transverse conduction short circuit, and an external signal cannot be transmitted to the driving backplane 10 through the gold finger 21 and the COF bonding terminal 12, thereby causing display abnormality of the display panel.

Accordingly, the present invention is directed to a display panel to solve the above problems. As shown in fig. 3 and 4, the present invention provides a display panel, preferably an organic light emitting display panel, including an array substrate 1000 and a flexible circuit board 2000, wherein the array substrate 1000 is provided with a first terminal portion, and the first terminal portion includes a plurality of first terminals 1200; a second terminal portion is arranged on the flexible circuit board 2000, the second terminal portion includes a plurality of second terminals 2100, and each second terminal 2100 corresponds to one first terminal 1200; each of the second terminals 2100 includes a first region 2101 and a second region 2102 connected to each other, a width W1 of the first region 2101 is greater than a width W2 of the second region 2102, a conductive adhesive is disposed between the first region 2101 and the first terminal 1200, and a projection of the second region 2101 on the array substrate 1000 does not overlap a projection of the first terminal 1200 on the array substrate 1000.

In the present embodiment, the width W1 of the first region 2101 and the width W2 of the second region 2102 refer to the lateral widths of the second terminal 2100, respectively. Preferably, the ratio of the width W1 of the first region 2101 to the width W2 of the second region 2102 is 1: (0.2-0.6), for example, 1:0.2, 1:0.3, 1:0.4, 1:0.5 or 1:0.6, or may be selected from the interval consisting of any two of the above.

In a preferred embodiment, the second region 2102 of the second terminal 2100 is connected to the central region in the width direction of the first region 2101. In other words, the first region 2101 controls the both long sides of the second region 2102 to narrow toward the central region, respectively, from the edge distant from the first terminal 1200 to form the second region 2102.

In other embodiments of the present invention, the second region of the second terminal is connected to one side of the first region in the width direction, that is, the first region is controlled to narrow the long edge of one side in the second region toward the long edge of the other side from the edge far away from the first terminal.

In the present invention, the width of the second region 2102 in which the second terminal 2100 is not press-bonded to the first terminal 1200 is narrowed, so that the probability that the second region 2102 of the second terminal 2100 is laterally conducted to the etching residue 1300 of the anode layer on the array substrate 1000 is reduced. Specifically, anisotropic conductive adhesive is generally used for press bonding the flexible circuit board 2000 and the array substrate 1000, since the width W2 of the second region 2102 is smaller, the overlapped region between the second region 2102 and the etching residue 1300 of the anode layer is smaller, that is, the effective contact area is small, the conduction probability between the etching residue 1300 of the anode layer and the second region 2102 of the second terminal 2100 of the flexible circuit board 2000 is reduced, and further the conduction probability between the two second regions 2102 of the adjacent second terminals 2100 and the etching residue 1300 of the pole layer is exponentially reduced, thereby effectively reducing or overcoming the problem that after the existing flexible circuit board is press bonded, the gold finger thereon is easily contacted with the etching residue of the anode layer to generate a lateral short circuit.

Note that the etching residue 1300 of the anode layer tends to be formed between the edge 1101 of the planarization layer 1100 and the first terminal 1200.

In this embodiment, the plurality of first terminals 1200 are respectively formed on the planarization layer 1100. The plurality of first terminals 1200 are respectively disposed adjacent to the edge 1101 of the planarization layer 1100, and the plurality of first terminals 1200 have a predetermined distance from the edge 1101 of the planarization layer 1100. The edge 1101 of the planarization layer 1100 is close to the edge 1001 of the array substrate 1000, and preferably, the edge 1101 of the planarization layer 1100 is located inside the edge 1001 of the array substrate 1000 to avoid cutting the planarization layer 1100 when cutting the array substrate 1000.

The first terminals 1200 are spaced apart from the edge 1101 of the planarization layer 1100 by a predetermined distance, so that the first terminals 1200 are not electrically connected to the etching residues 1300 of the anode layer, thereby avoiding an abnormal condition. In a preferred embodiment, the predetermined distance between the plurality of first terminals 1200 and the edge 1101 of the planarization layer 1100 is in the range of 0-70 μm.

In addition, an anode layer (not shown) is formed on the planarization layer 1100, and the anode layer includes a plurality of electrode patterns, each of which corresponds to a pixel unit (not shown). In which a plurality of electrode patterns are formed by etching an anode film layer formed on a planarization layer, an etching residue 1300 forming an anode layer among the plurality of electrode patterns tends to cover an edge of the planarization layer 1100.

In a preferred embodiment, a region from the edge of the planarization layer to the edge of the array substrate has a slope structure or a groove structure inclined with respect to the planarization layer.

As shown in fig. 3 and 4, the second region 2102 extends from the first region 2101 to the edge 1101 of the flat layer 1100, and the second region crosses the far distance 1101 of the flat layer 1100, so that the narrowed second region 2102 covers the edge 1101 of the flat layer 1100 and the etching residue 1300 of the anode layer, thereby ensuring that the etching residue 1300 of the anode layer on the edge 1101 of the flat layer 1100 is not easy to conduct any two of the second regions 2102 and the etching residue 1300 of the anode layer through the conductive particles of the anisotropic conductive paste, and avoiding the problem of poor display.

The planarization layer 1100 often further includes a plurality of non-insulating layers and a semiconductor layer disposed between the plurality of non-insulating layers; the multilayer inorganic insulating layer includes, for example, a buffer layer, a gate insulating layer, and an interlayer insulating layer; the multilayer metal layers comprise a grid metal layer, a source drain metal layer and a data line metal layer; the multiple metal layers and the semiconductor layer jointly form a plurality of TFT devices and metal routing wires.

The planarization layer 1100 includes an anode layer, a pixel defining layer and a supporting layer, which are organic film layers, respectively, wherein the pixel defining layer is formed on the planarization layer 1100 and the anode layer and encloses a plurality of pixel openings on the anode layer, and electrode patterns of the anode layer are exposed from the pixel openings; the support layer is formed on the pixel defining region outside the pixel opening of the pixel defining layer for supporting the mask for steaming the light emitting device layer.

The light emitting device layer is located in the pixel opening, and includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and a cathode layer.

As shown in fig. 5 and 6, the film thickness T1 of the first region 2101 of the second terminal 2100 is smaller than the film thickness T of the second region 2102, and the ratio of the cross-sectional area of the second region 2102 in the thickness direction to the cross-sectional area of the first region 2101 in the thickness direction is 1: (0.95-1.05). The purpose of this setting is: the width W2 of the second region 2102 is narrowed without increasing the resistance of the second region 2102.

The resistance R of the second region 2102 is inversely proportional to the cross-sectional area S, and is calculated as: r = ρ L/S; where R represents resistance, L represents wire length, S represents wire cross-sectional area, and ρ represents wire resistivity. As shown in fig. 6, the cross-sectional area S is calculated by the formula: s = H (W2+ W3)/2; the second region 2102 has a trapezoidal cross-section, S is a cross-sectional area, W2 is a width at the top of the trapezoid, W3 is a width at the bottom of the trapezoid, and T is a vertical height of the trapezoid (i.e., a film thickness of the second region 2102). According to the above calculation formula, the values of W2 and W3 of the second region 2102 become smaller, that is, the cross-sectional area S becomes smaller, and the resistance R of the corresponding second region 2102 becomes larger.

Due to the driving process of the display panel, the driving IC (packaged on the flexible circuit board 2000) has a requirement on the resistance of the traces on the flexible circuit board 2000 and the connection terminal (the second terminal 2100), and when the widths W2 and W3 of the second region 2102 of the second terminal 2100 are reduced, the resistance may be increased correspondingly, which may exceed the requirement of the driving IC. At this time, the cross-sectional area S is secured constant by increasing the film thickness T of the second region 2102 of the second terminal 2100 of the flexible circuit board 2000, thereby making it possible not to increase even the resistance of the second region 2102.

Note that, when the second region 2102 has a trapezoidal cross section, the upper width W2 and the lower width W3 of the trapezoid are both smaller than the width W1 of the first region 2101.

As shown in fig. 3 to 5, the second terminal 2100 on the flexible circuit board 2000 further includes a third region 2103, and the third region 2103 is connected to the second region 2102 and protrudes toward the edge 1001 of the array substrate 1000, which passes over the edge 1001 of the array substrate 1000.

The width of the third region 2103 is greater than the width W2 of the second region 2102, and preferably, the width of the third region 2103 is equal to, less than or greater than the width W1 of the first region 2101.

In a preferred embodiment, the film thickness T2 of the third region 2103 is less than the film thickness T of the second region 2102, and preferably, the film thickness T2 of the third region 2103 is equal to, greater than or less than the film thickness T1 of the first region 2101.

In order to explain the structure of the second terminal 2100 in the present invention, the second terminal 2100 is divided into different regions, and in actual manufacturing, the first region 2101, the second region 2102, and/or the third region 2103 of the second terminal 2100 are made of the same material and are integrally molded.

As shown in fig. 7, in another embodiment of the present invention, the flexible circuit board 3000 bonded to the array substrate 1000 by pressing includes a second terminal portion, the second terminal portion includes a plurality of second terminals 3100, the second terminals 3100 includes a first region 3101 and a second region 3102 connected to each other, wherein the first region 3101 and the corresponding first terminal 1200 on the array substrate 1000 are electrically connected to each other after being pressed by a conductive adhesive, and a projection of the second region 3102 on the array substrate 1000 does not overlap with a projection of the first terminal 1200 on the array substrate 1000.

In this embodiment, the second region 3102 extends from the first region 3101 toward the edge 1101 of the flat layer 1100 and across the edge 1101 of the flat layer 1100. Preferably, the second region 3102 extends beyond the edge 1001 of the array substrate 1000.

In a preferred embodiment, the thickness of the second region 3102 is greater than that of the first region 3101, so that the resistance of the second terminal 3100 meets the resistance requirement of the driver IC.

As shown in fig. 7, a conductive adhesive, such as an anisotropic conductive adhesive, is disposed between the first terminal 1200 and the first region 3101, and the conductive adhesive includes a base material and conductive particles, wherein the base material is attached to the first terminal 1200, the first region 3101 of the second terminal 3100 of the flexible circuit board 2000 is pressed onto the first terminal 1200, and the conductive particles electrically connect the first region 3101 of the first terminal 1200 and the first region 3101 of the second terminal 3100.

Alternatively, a conductive adhesive, such as an anisotropic conductive adhesive, is disposed between the first terminal 1200 and the first region 3101, and includes a base material and conductive particles, the base material is attached to the first region 3101 of the second terminal 3100, the flexible circuit board 2000 and the anisotropic conductive adhesive are pressed onto the first terminal 1200, and the conductive particles electrically connect the first region 3101 of the first terminal 1200 and the second terminal 3100.

The invention also provides a display device which comprises the display panel.

In summary, the present invention provides a display panel and a display device, where the display panel includes an array substrate and a flexible circuit board, a width of a second region where a second terminal on the flexible circuit board is not press-bonded to a first terminal is narrowed, an effective contact area of the second region and an etching residue of an anode layer on the array substrate is reduced, a problem of a short circuit caused by a lateral conduction of the second terminal on the flexible circuit board due to a conduction of the etching residue of the second region and the anode layer is avoided, and a probability of a display failure of the display panel is reduced.

The present invention has been described in relation to the above embodiments, which are only exemplary of the implementation of the present invention. Furthermore, the technical features mentioned in the different embodiments of the present invention described above can be combined with each other as long as they do not conflict with each other. It is to be noted that the present invention may take various other embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display panel, comprising:

an array substrate provided with a first terminal part including a plurality of first terminals; and

the flexible circuit board is provided with a second terminal part, the second terminal part comprises a plurality of second terminals, and each second terminal corresponds to one first terminal;

each second terminal comprises a first area and a second area which are connected, the width of the second area is smaller than that of the first area, and conductive adhesive is arranged between the first area and the corresponding first terminal;

the array substrate further comprises a flat layer, wherein the first terminals are arranged adjacent to the edge of the flat layer, and the first terminals and the edge of the flat layer have a preset distance; the second region extends from the first region toward and beyond an edge of the planar layer.

2. The display panel according to claim 1, wherein the second region of the second terminal is connected to a central region in a width direction of the first region.

3. The display panel according to claim 1 or 2, wherein a ratio of the width of the first region to the width of the second region of the second terminal is 1: (0.2-0.6).

4. The display panel according to claim 1, wherein the film thickness of the second region is greater than the film thickness of the first region.

5. The display panel according to claim 1, wherein the second terminal further comprises a third region connected to an end of the second region remote from the first region, and wherein a width of the third region is larger than a width of the second region.

6. The display panel according to claim 5, wherein the third region extends away from one side edge of the first region and protrudes beyond the edge of the array substrate.

7. The display panel according to claim 5, wherein the first region, the second region and the third region of the second terminal are made of the same material and are integrally formed.

8. A display device characterized in that it comprises a display panel as claimed in any one of claims 1-7.