CN115019656B - Display panel motherboard, display panel and display device - Google Patents
Display panel motherboard, display panel and display device Download PDFInfo
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- CN115019656B CN115019656B CN202210720305.4A CN202210720305A CN115019656B CN 115019656 B CN115019656 B CN 115019656B CN 202210720305 A CN202210720305 A CN 202210720305A CN 115019656 B CN115019656 B CN 115019656B
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- 238000012360 testing method Methods 0.000 claims abstract description 137
- 238000005520 cutting process Methods 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 abstract description 16
- 238000010586 diagram Methods 0.000 description 20
- 239000000758 substrate Substances 0.000 description 15
- 230000008901 benefit Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000002360 preparation method Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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Abstract
The application provides a display panel motherboard, a display panel and a display device, which solve the problem that a conductive material area on a cutting surface of the display panel causes a short circuit of a bonding pad of a circuit board for testing in the prior art. Wherein, the display panel motherboard includes: aligning marks; the test pad is positioned at one side of a cutting line formed by the alignment marks; the anti-bonding pad is positioned on the side of the test bonding pad of the cutting line, and the orthographic projection of the anti-bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the cutting line in the direction vertical to the display surface; and a load circuit connected with the anti-bonding pad for consuming the current flowing in the anti-bonding pad.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel motherboard, a display panel and a display device.
Background
In the manufacturing process of the display panel, it is generally necessary to cut a large-sized mother panel of the display panel to obtain a small-sized display panel. The cutting line location generally includes an organic material which is easily carbonized during the cutting process, thereby forming a material region having a conductive function (hereinafter referred to as a conductive material region) on a cut surface of the display panel obtained after the cutting. In this case, when the test circuit board and the cut display panel are connected to perform the lighting test, the pads of the test circuit board are likely to contact the conductive material areas on the cut surface of the display panel, so that a short circuit occurs between adjacent pads of the test circuit board, the short circuit current may cause burn of the test circuit board, and serious abnormality may also occur in the signal generator used for the lighting test.
Disclosure of Invention
In view of this, the embodiments of the present application provide a display panel motherboard, a display panel and a display device, so as to solve the problem that the conductive material area on the cut surface of the display panel in the prior art causes the short circuit of the bonding pad of the circuit board for testing.
A first aspect of the present application provides a display panel motherboard, comprising: aligning marks; the test pad is positioned at one side of a cutting line formed by the alignment mark; the anti-pad is positioned on the side of the test pad of the cutting line, and orthographic projection of the anti-pad in the direction vertical to the display surface is intersected with orthographic projection of the test pad in the direction vertical to the display surface; and a load circuit connected with the anti-bonding pad for consuming the current flowing in the anti-bonding pad. According to the display panel provided by the embodiment, through the arrangement of the anti-bonding pad and the load circuit connected with the anti-bonding pad, the orthographic projection of the anti-bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the test bonding pad in the direction vertical to the display surface, even if a conductive material area is formed on the cutting surface of the display panel obtained after cutting along the cutting line, when the bonding pad of the test circuit board is lapped on the test bonding pad of the display panel, the short-circuit current generated by the short-circuit of the bonding pad on the test circuit board due to the conductive material area can be led into the load circuit through the anti-bonding pad and is consumed by the load circuit, so that the short-circuit current is prevented from damaging the test circuit board, and even a signal generator for lighting test is used.
In one embodiment, the test pad and the anti-pad are provided in the same layer. This has the advantage that the test pad and the anti-pad can be realized by a one-time patterning process, and the preparation process is simpler.
In one embodiment, the anti-pad and the test pad are spaced apart in a direction parallel to the cut line. This may attenuate electromagnetic interference between currents flowing in different pads.
In one embodiment, the display panel motherboard further comprises a ground pad connected with the anti-pad as a load circuit; or the display panel motherboard also comprises a pixel unit, and the pixel unit is connected with the anti-bonding pad to serve as a load circuit. The grounding pad is used as a load circuit, so that the structure is simple and the implementation is easy. With the pixel unit as a load circuit, the position of the signal line where the short-circuit problem occurs can be determined based on the display condition of the pixel unit.
In one embodiment, the display panel motherboard further includes a thermistor disposed on a test line connected to the test pad. The resistance of the thermistor increases with the increase of the current, so that the current is limited in an effective current range, and the large current is prevented from flowing back into the test circuit board and the signal generator along the test pad, so that further protection is provided for the test circuit board and the signal generator.
In one embodiment, the display panel motherboard further comprises a frame region in contact with the dicing line and a display region located on a side of the frame region away from the dicing line, and the test pad and the anti-pad are located in the frame region.
A second aspect of the present application provides another display panel, including: the test pad comprises a first end and a second end which are oppositely arranged, the first end is connected with the test line, and the second end points to one side surface of the display panel; an anti-pad, the orthographic projection of the anti-pad in the direction vertical to the display surface intersects with the orthographic projection of the side surface in the direction vertical to the display surface; and a load circuit connected with the anti-bonding pad for consuming the current flowing in the anti-bonding pad.
In one embodiment, the test pad and the anti-pad are co-layer; preferably, the anti-pad and the test pad are spaced apart in a direction parallel to the dicing line.
In one embodiment, the display panel further includes a ground pad connected to the anti-pad as a load circuit; alternatively, the display panel further includes a pixel unit connected to the anti-pad as a load circuit.
A third aspect of the present application provides a display device, including the display panel provided in the second aspect.
According to the display panel motherboard, the display panel and the display device provided by the embodiment of the application, through the arrangement of the anti-bonding pad and the load circuit connected with the anti-bonding pad, the orthographic projection of the anti-bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the test bonding pad in the direction vertical to the display surface, even if a conductive material area is formed on the cutting surface of the display panel obtained after cutting along the cutting line, when the bonding pad of the test circuit board is lapped on the test bonding pad of the display panel, the short-circuit current generated by the short-circuit of the bonding pad on the test circuit board due to the conductive material area can be led into the load circuit through the anti-bonding pad and is consumed by the load circuit, so that the short-circuit current is prevented from damaging the test circuit board, and even a signal generator used for lighting test is damaged.
Drawings
Fig. 1 is a top view of a conventional display panel motherboard.
Fig. 2 is a schematic structural diagram of a display panel obtained after cutting a mother board of the display panel according to an embodiment of the present disclosure.
Fig. 3 is a schematic cross-sectional structure diagram of the display panel shown in fig. 2 according to an embodiment of the present application when performing a lighting test.
Fig. 4 is a top view of the display panel shown in fig. 2 according to an embodiment of the present application. Fig. 5 is a schematic structural diagram of a motherboard of a display panel according to a first embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of the motherboard of the display panel shown in fig. 5 along line A1 A2.
Fig. 7 is a schematic structural diagram of a motherboard of a display panel according to a second embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of the motherboard of the display panel shown in fig. 7 along line B1B 2.
Fig. 9 is a schematic structural diagram of a motherboard of a display panel according to a third embodiment of the present application.
Fig. 10 is a schematic structural diagram of a motherboard of a display panel according to a fourth embodiment of the present application.
Fig. 11 is a schematic structural diagram of a motherboard of a display panel according to a fifth embodiment of the present application.
Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of a display panel according to two embodiments of the present application.
Fig. 14 is a schematic structural diagram of a display panel according to a third embodiment of the present disclosure.
Detailed Description
Fig. 1 is a top view of a conventional display panel motherboard. As shown in fig. 1, the display panel motherboard includes a plurality of display panels 10 and alignment marks N disposed between the plurality of display panels 10, as shown by black solid dots in fig. 1. The alignment mark N on the display panel motherboard is used for aligning with the alignment mark on the cutting device to determine a cutting line L on the display panel motherboard, and the cutting device cuts the display panel motherboard along the cutting line L, so that the large-size display panel motherboard can be divided into a plurality of small-size display panels 10. The display panel 10 includes a display area AA and a bezel area at least partially surrounding the display area AA. The frame area includes a pad area BB, and pads with various functions, such as a test pad for lighting test, a driving pad connected with a driving chip, etc., are disposed in the pad area BB, and the pads are used for transmitting external signals into the display area AA so as to realize corresponding functions.
Fig. 2 is a schematic structural diagram of a display panel obtained after cutting a mother board of the display panel according to an embodiment of the present disclosure. As shown in fig. 1 and 2, the display panel 10 includes at least one side surface due to cutting, which is denoted as a cut surface S, which is easily carbonized due to cutting, thereby forming the conductive material region Q. The pad region BB of the display panel 10 is closer to the cut surface S than the display region AA. The pad region BB is provided with at least one test pad 11, the test pad 11 including oppositely disposed first and second ends, the first end being connected to the test line, the second end being directed toward the cutting plane S.
Fig. 3 is a schematic cross-sectional structure diagram of the display panel shown in fig. 2 according to an embodiment of the present application when performing a lighting test. Fig. 4 is a top view of the display panel shown in fig. 2 according to an embodiment of the present application. As shown in fig. 3 and 4, when the lighting test is performed on the display panel 10 shown in fig. 2, the pads 21 on the test board 20 need to be overlapped with the test pads 11 of the display panel 10. In this case, the test circuit board 20 may be bent at the edge of the display panel 10 for various reasons, for example, to cause the pads 21 on the test circuit board 20 to contact the conductive material region Q on the cut surface S of the display panel 10, thereby causing the adjacent pads 20 to be shorted, the short-circuit current may cause the test circuit board 20 to burn, and serious abnormality may also occur in the signal generator used for the lighting test.
In view of this, the embodiment of the present application provides a display panel motherboard, a display panel, and a display device, by providing an anti-pad and a load circuit connected to the anti-pad in a pad area BB, an orthographic projection of the anti-pad in a direction perpendicular to a display surface intersects with an orthographic projection of a cutting line L in a direction perpendicular to the display surface, and the anti-pad is exposed on a cut surface S of the resulting display panel after cutting the display panel motherboard along the cutting line L. In this case, even if the conductive material region Q is formed on the cut surface S, when the pads 21 of the test circuit board 20 overlap the test pads 11 of the display panel 10, a short-circuit current generated by the short-circuit of the pads 21 on the test circuit board 20 due to the conductive material region Q can be introduced into the load circuit through the anti-pad and consumed by the load circuit, thereby preventing the short-circuit current from damaging the test circuit board 20 and even damaging the signal generator used for the lighting test.
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Fig. 5 is a schematic structural diagram of a motherboard of a display panel according to a first embodiment of the present application. Fig. 6 is a schematic cross-sectional view of the motherboard of the display panel shown in fig. 4 along line A1 A2. In this embodiment, the display panel motherboard includes two display panels 10 as an example, and it should be understood that the number of display panels 10 may be reasonably set according to actual needs. As can be seen from a review of fig. 5 and 6, the display panel motherboard differs from the display panel shown in fig. 1 in that the display panel motherboard further includes an anti-pad 12 and a load circuit connected to the anti-pad 12. The anti-pad 12 is located on the side of the dicing line L where the test pad 11 is located, i.e., the anti-pad 12 and the test pad 11 are located on the same side of the dicing line L. The orthographic projection of the anti-pad 12 in the direction perpendicular to the display surface intersects the orthographic projection of the cutting line L in the direction perpendicular to the display surface. The intersection referred to herein may be the intersection of the orthographic projection of the anti-pad 12 and the orthographic projection of the cut line L, i.e., the anti-pad 12 passes through the cut line L to extend from one display panel to the other display panel; or it may be that the orthographic projection of the anti-pad 12 extends just above the dicing line L. By providing the intersection of the orthographic projection of the anti-pad 12 in the direction perpendicular to the display surface and the orthographic projection of the cutting line L in the direction perpendicular to the display surface, it is ensured that after cutting along the cutting line L, one end of the anti-pad 12 is exposed on the cutting surface S to be in contact with the conductive material region Q on the cutting surface S, and the short-circuit current generated by the short-circuit of the pad 21 of the test circuit board 20 due to the conductive material region Q is led into the load circuit to be consumed by the load circuit.
As shown in fig. 6, from the perspective of the film structure, the display panel motherboard includes an array substrate 110 and a light emitting device layer 120 stacked on the array substrate 110. The light emitting device layer 120 includes a first light emitting device region 121 and a second light emitting device region 122 disposed at a spacing. The alignment mark N is disposed on the array substrate 110 between the first light emitting device region 121 and the second light emitting device region 122. The cut surface S may divide the array substrate 11 into a first array substrate 111 and a second array substrate 112. The first light emitting device region 121 is located on the first array substrate 111, and the second light emitting device region 122 is located on the second array substrate 112. After being cut along the cutting plane S, the first array substrate 111 and the first light emitting device region 121 form a first display panel, the first light emitting device region 121 forms a display area AA of the first display panel, and an area of the first array substrate 111 not covered by the first light emitting device region 121 forms a frame area of the first display panel. The second array substrate 112 and the second light emitting device region 122 form a second display panel, the second light emitting device region 122 forms a display area AA of the second display panel, and an area of the second array substrate 112 not covered by the second light emitting device region 122 forms a bezel area of the second display panel.
The anti-pad 12 may be provided in the same layer as the test pad 11 or may be provided in a different layer from the test pad 11. In this embodiment, as shown in fig. 6, the test pad 11 and the anti-pad 12 are provided in the same layer. This has the advantage that the test pad 11 and the anti-pad 12 can be realized by a one-time patterning process, and the manufacturing process is simpler. In the case where the test pad 11 and the anti-pad 12 are arranged in the same layer, as shown in fig. 5, the test pad 11 and the anti-pad 12 are arranged at intervals in the direction parallel to the cutting line L; alternatively, the test pads 11 and the anti-pads 12 are disposed opposite to each other, i.e., the test pads 11 and the anti-pads 12 are collinear, and the straight lines in which the test pads 11 and the anti-pads 12 are located are perpendicular to the cutting line L. In comparison, the arrangement of the guard pads 11 and the test pads 12 spaced apart is advantageous for achieving a narrow frame. The interval between the test pad 11 and the guard pad 12 can be set reasonably according to actual needs. In an example, the number of the test pads 11 and the anti-pads 12 is plural, the test pads 11 and the anti-pads 12 are arranged at intervals in a direction parallel to the cutting line L, and the width of the anti-pads 12 is greater than or equal to 1/3 of the interval between the adjacent test pads 11 and less than or equal to 2/3 of the interval between the adjacent test pads 11. For example, the spacing between adjacent test pads 11 is 60 microns and the width of the anti-pad 12 is 20 microns. The greater the width of the anti-pad 12, the greater the reliability and the greater the electromagnetic interference between adjacent test pads 11, and the provision of the anti-pad 12 having a width between 1/3 and 2/3 of the spacing between adjacent test pads 11 can achieve a compromise between improving the reliability of the anti-pad 12 and reducing the electromagnetic interference between the anti-pad 12 and the test pads 11. The plurality of anti-bonding pads 12 may be arranged linearly along the direction of the cutting line L, may be arranged in a fan shape, and the like, and the plurality of test bonding pads 11 may be arranged linearly along the direction of the cutting line L, may be arranged in a fan shape, and the like.
In this embodiment, the load circuit is implemented as a ground circuit. Specifically, as shown in fig. 5, the array substrate 110 is further provided with a ground pad 13, the ground pad 13 and the test pad 11 are arranged on the same layer, the ground pad 13 is connected with the anti-pad 12, and the ground pad 13 and the ground wire connected therewith are used together as a load circuit. In this case, during the lighting test, the short-circuit current generated in the pad 21 of the test board 20 can be led to the ground pad 13 through the anti-pad 12 and further led away from the ground wire, thereby avoiding damage to the test board 20 and even the signal generator.
Fig. 7 is a schematic structural diagram of a motherboard of a display panel according to a second embodiment of the present application. Fig. 8 is a schematic cross-sectional view of the motherboard of the display panel shown in fig. 7 along line B1B 2. As shown in fig. 7 and 8, in the present embodiment, the test pad 11 and the anti-pad 12 are located in different layers, respectively, the test pad 11 and the ground pad 13 are located in the same layer, and the anti-pad 12 is connected to the ground pad 13 through a via hole.
Specifically, the orthographic projections of the anti-pad 12 in the direction perpendicular to the display surface and the orthographic projections of the test pad 11 in the direction perpendicular to the display surface are arranged at intervals or in pairs. In this embodiment, the number of the test pads 11 and the anti-pads 12 is plural, and orthographic projections of the plurality of anti-pads 12 in a direction perpendicular to the display surface and orthographic projections of the plurality of test pads 11 in a direction perpendicular to the display surface are alternately arranged, and a partial area of orthographic projection of each anti-pad 12 is located between orthographic projections of two adjacent test pads 11.
According to the display panel provided in the present embodiment, by disposing the test pad 11 and the anti-pad 12 in different layers, there is an advantage in that the size of the frame area can be reduced while electromagnetic interference between the test pad 11 and the anti-pad 12 can be reduced, compared to the case where the test pad 11 and the anti-pad 12 are disposed in the same layer.
Fig. 9 is a schematic structural diagram of a motherboard of a display panel according to a third embodiment of the present application. As shown in fig. 9, the display panel motherboard is different from the display panel motherboard provided in any of the above embodiments in that the display panel motherboard further includes a plurality of thermistors 14, and the plurality of thermistors 14 are in one-to-one correspondence with the plurality of test pads 11. Each test pad 11 is disposed on the test line to which its corresponding test pad 11 is connected, i.e., the thermistor 14 is located at the end of the test pad 11 remote from the anti-pad 12. The thermistor 14 may be made of Fe, for example 2 O 3 、Al 2 O 3 Etc. In this case, as shown in fig. 3, when the display panel obtained by cutting the display panel motherboard along the cutting line L and the test circuit board 20 are subjected to the lighting test, the pads 21 of the test circuit board 20 are short-circuitedPart of the current is conducted away through the anti-pad 12 and the grounding pad 13, the other part flows through the test pad 11 and the thermistor 14, and the impedance of the thermistor 14 increases along with the increase of the current, so that the current is limited in an effective current range, and large current is prevented from flowing back into the test circuit board 20 and the signal generator along the test pad 11, so that further protection is provided for the test circuit board 20 and the signal generator. It should be appreciated that the thermistor 14 may be provided separately from the load circuit, and thus may also provide protection for the test board 20 and the signal generator from damage caused by short-circuit currents.
Fig. 10 is a schematic structural diagram of a motherboard of a display panel according to a fourth embodiment of the present application. As shown in fig. 10, the display panel motherboard differs from the display panel motherboard shown in fig. 5 and 6 in that in the present embodiment, the load circuit is implemented as at least one pixel unit. Specifically, taking the example in which the load circuit is implemented as one pixel column, a plurality of pixel circuits 15 are further provided in the first array substrate 111, and a plurality of light emitting devices 16 are provided in the first light emitting device region 121. At least one light emitting device 16 is connected to one pixel circuit 15 to constitute one pixel unit 130. The first array substrate 111 is further provided therein with driving signal lines 17, and the driving signal lines 17 connect a row of pixel units 130 and the anti-pads 12, or connect a column of pixel units 130 and the anti-pads 12. The row or column of pixel cells may be, for example, a plurality of green pixel cells arranged linearly.
In this embodiment, the anti-pad 12 and the test pad 11 are provided in the same layer, the anti-pad 12 and the drive signal line 17 are located in different layers, and the drive signal line 17 and the anti-pad 12 are connected by a via hole.
When the display panel obtained after cutting the motherboard of the display panel and the test circuit board 20 according to the present embodiment are subjected to the lighting test, if the bonding pad 21 of the test circuit board 20 is shorted, the shorted current is provided to one row or one column of pixel units 130 along the anti-bonding pad 12 and the driving signal line 17. In this case, the row or column of pixel units 130 displays a bright line, thereby determining an abnormal product and detecting the abnormal product.
Fig. 11 is a schematic structural diagram of a motherboard of a display panel according to a fifth embodiment of the present application. As shown in fig. 11, the display panel motherboard differs from the display panel motherboard shown in fig. 5 and 6 in that, in the present embodiment, the anti-pad 12 and the test pad 11 are located in different layers, and the anti-pad 12 and the driving signal line 17 are located in the same layer.
The application also provides a display panel. Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application. The display panel may be a display panel obtained by cutting the display panel motherboard provided in any of the above embodiments along the cutting line L. As shown in fig. 12, the display panel includes a test pad 11, an anti-pad 12, and a load circuit. The test pad 11 includes a first end and a second end disposed opposite to each other, the first end is connected to the test line, and the second end points to a side surface of the display panel, which is the cutting surface S. The orthographic projection of the anti-pad 12 in the direction perpendicular to the display surface intersects the orthographic projection of the cut surface S in the direction perpendicular to the display surface. For example, the frame region includes a first pad region N1 and a second pad region N2, the first pad region N1 being located between the display region AA and the second pad region N2, and an orthographic projection of the side surface S in a direction perpendicular to the display surface forms a partial edge of the orthographic projection of the second pad region N2 in the direction perpendicular to the display surface. The test pad 11 is located in the first pad area N1, and the anti-pad 12 is located in the second pad area N2. The anti-pad 12 extends to and is exposed at the side S. The load circuit is implemented as a ground circuit comprising a ground pad 13 and a ground line, the anti-pad 12 being connected to the ground pad 13. The test pad 11 and the anti-pad 12 are arranged in the same layer. In this case, the anti-pad 12 and the test pad 11 are disposed at a spacing in a direction parallel to the dicing line; alternatively, the anti-pad 12 and the test pad 11 are disposed opposite to each other.
Referring to fig. 3, when the bonding pad 21 on the test circuit board 20 is overlapped on the test bonding pad 11, the test circuit board 20 bends at the edge of the display panel, so that the bonding pad 21 on the test circuit board 20 contacts the conductive material region Q on the cutting surface S, and thus, the adjacent bonding pad 21 is shorted, the short-circuit current sequentially passes through the bonding pad 21, the conductive material region Q, the anti-bonding pad 12, the grounding bonding pad 13, and is finally conducted away by the grounding wire, thereby avoiding burning of the test circuit board 20.
Fig. 13 is a schematic structural diagram of a display panel according to two embodiments of the present application. The display panel differs from the display panel shown in fig. 12 in that in the present embodiment, the load circuit is implemented as at least one pixel unit 130. Specifically, the display panel further includes a plurality of pixel units 130, wherein a portion of the pixel units 130 of the plurality of pixel units 130 are connected to the anti-pad 12, and a portion of the pixel units 130 connected to the anti-pad 12 serves as a load circuit. The partial pixel unit 130 as the load circuit may be, for example, a plurality of green pixel units arranged linearly.
Fig. 14 is a schematic structural diagram of a display panel according to a third embodiment of the present disclosure. As shown in fig. 14, the display panel is different from the display panel shown in fig. 12 in that the display panel further includes a thermistor 14, and the thermistor 14 is disposed on a test line to which the test pad 11 is connected, i.e., the thermistor 14 is located at an end of the test pad 11 remote from the anti-pad 12. The thermistor 14 may be made of Fe, for example 2 O 3 、Al 2 O 3 Etc.
The application also provides a display device, which comprises the display panel provided by any embodiment of the application. The specific structure of the display panel is referred to the above display panel embodiment, and will not be described herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the application to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.
Claims (11)
1. A display panel motherboard, comprising:
aligning marks;
the test pad is positioned at one side of the cutting line formed by the alignment mark;
an anti-bonding pad positioned on the side of the cutting line where the test bonding pad is positioned, wherein the orthographic projection of the anti-bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the cutting line in the direction vertical to the display surface; and
and the load circuit is connected with the anti-bonding pad and used for consuming the current flowing in the anti-bonding pad.
2. The display panel motherboard of claim 1 wherein said test pad and said anti-pad are co-layer.
3. The display panel motherboard of claim 2, wherein said anti-pad and said test pad are spaced apart in a direction parallel to said cut line.
4. The display panel motherboard of any one of claims 1-3, further comprising a ground pad connected with said anti-pad as said load circuit; or,
the display panel motherboard further comprises a pixel unit, and the pixel unit is connected with the anti-pad to serve as the load circuit.
5. A display panel motherboard according to any one of claims 1-3, further comprising a thermistor disposed on a test line to which the test pad is connected.
6. A display panel motherboard according to any one of claims 1 to 3, comprising a border region in contact with a cut line and a display region located on a side of the border region remote from the cut line, the test pads and the anti-pads being located in the border region.
7. A display panel, comprising:
the test pad comprises a first end and a second end which are oppositely arranged, the first end is connected with a test line, and the second end points to one side surface of the display panel;
an anti-pad, an orthographic projection of the anti-pad in a direction perpendicular to a display surface intersects an orthographic projection of the side surface in a direction perpendicular to the display surface; and
and the load circuit is connected with the anti-bonding pad and used for consuming the current flowing in the anti-bonding pad.
8. The display panel of claim 7, wherein the test pad and the anti-pad are disposed in a same layer.
9. The display panel of claim 8, wherein the anti-pad and the test pad are spaced apart in a direction parallel to the cut line.
10. The display panel according to any one of claims 7 to 9, further comprising a ground pad connected to the anti-pad as the load circuit; or,
the display panel further comprises a pixel unit, and the pixel unit is connected with the anti-pad to serve as the load circuit.
11. A display device comprising the display panel of claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210720305.4A CN115019656B (en) | 2022-06-23 | 2022-06-23 | Display panel motherboard, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210720305.4A CN115019656B (en) | 2022-06-23 | 2022-06-23 | Display panel motherboard, display panel and display device |
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| Publication Number | Publication Date |
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| CN115019656A CN115019656A (en) | 2022-09-06 |
| CN115019656B true CN115019656B (en) | 2023-12-22 |
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| CN202210720305.4A Active CN115019656B (en) | 2022-06-23 | 2022-06-23 | Display panel motherboard, display panel and display device |
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