CN115019656A - Display panel mother board, display panel and display device - Google Patents
Display panel mother board, display panel and display device Download PDFInfo
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- CN115019656A CN115019656A CN202210720305.4A CN202210720305A CN115019656A CN 115019656 A CN115019656 A CN 115019656A CN 202210720305 A CN202210720305 A CN 202210720305A CN 115019656 A CN115019656 A CN 115019656A
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- 238000012360 testing method Methods 0.000 claims abstract description 139
- 238000005520 cutting process Methods 0.000 claims abstract description 69
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- 238000010586 diagram Methods 0.000 description 20
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Abstract
The application provides a display panel mother board, a display panel and a display device, and solves the problem that a conducting material area on a cutting surface of the display panel in the prior art causes a pad of a circuit board for testing to be short-circuited. Wherein, the display panel motherboard includes: carrying out alignment identification; the test pad is positioned on one side of the cutting line formed by the alignment mark; the protective bonding pad is positioned on the side of the test bonding pad of the cutting line, and the orthographic projection of the protective bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the cutting line in the direction vertical to the display surface; and a load circuit connected to the shield pad for consuming a current flowing in the shield pad.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel mother board, a display panel and a display device.
Background
In the manufacturing process of the display panel, a large-sized display panel mother board is generally required to be cut to obtain a small-sized display panel. The position of the cutting line generally includes an organic material, and the organic material is easily carbonized during the cutting process, so that a material region having a conductive function (hereinafter referred to as a conductive material region) is formed on the cut surface of the display panel obtained after the cutting. In this case, when the test circuit board and the cut display panel are connected to perform the lighting test, the pads of the test circuit board are likely to contact the conductive material region on the cut surface of the display panel, so that a short circuit occurs between adjacent pads of the test circuit board, and the short circuit current may cause burning of the test circuit board and may seriously cause abnormality of the signal generator used for the lighting test.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a display panel motherboard, a display panel and a display device to solve the problem of a short circuit of a pad of a circuit board for testing caused by a conductive material region on a cutting surface of the display panel in the prior art.
The present application provides in a first aspect a display panel motherboard comprising: carrying out alignment identification; the test pad is positioned on one side of the cutting line formed by the alignment mark; the protective bonding pad is positioned on the side of the test bonding pad of the cutting line, and the orthographic projection of the protective bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the test bonding pad in the direction vertical to the display surface; and a load circuit connected to the shield pad for consuming a current flowing in the shield pad. According to the display panel provided by the embodiment, by arranging the protection pad and the load circuit connected with the protection pad, the orthographic projection of the protection pad in the direction perpendicular to the display surface is intersected with the orthographic projection of the test pad in the direction perpendicular to the display surface, even if the conductive material area is formed on the cutting surface of the display panel obtained after cutting along the cutting line, when the pad of the circuit board for test is lapped on the test pad of the display panel, the short-circuit current generated by the pad short circuit on the circuit board for test due to the conductive material area can be led into the load circuit through the protection pad and consumed by the load circuit, so that the circuit board for test is prevented from being damaged by the short-circuit current, and even a signal generator used for lighting test is prevented.
In one embodiment, the test pads and the guard pads are disposed in the same layer. This has the advantage that the test pad and the protection pad can be realized by one-time patterning process, and the preparation process is simpler.
In one embodiment, the guard pad and the test pad are spaced apart in a direction parallel to the cutting line. This can attenuate electromagnetic interference between currents flowing in different pads.
In one embodiment, the display panel motherboard further comprises a ground pad connected with the protection pad as a load circuit; or the display panel mother board also comprises a pixel unit, and the pixel unit is connected with the protective bonding pad to be used as a load circuit. And the grounding bonding pad is used as a load circuit, so that the structure is simple and the realization is easy. With the pixel unit as a load circuit, the position of the signal line where the short-circuit problem occurs can be determined based on the display condition of the pixel unit.
In one embodiment, the display panel mother substrate further includes a thermistor disposed on the test line connected to the test pad. The impedance of the thermistor is increased along with the increase of the current, so that the current is limited in an effective current range, and the large current is prevented from flowing back along the test pad to enter the circuit board for testing and the signal generator, so that further protection is provided for the circuit board for testing and the signal generator.
In one embodiment, the display panel mother board further comprises a frame area contacting with the cutting line and a display area located on one side of the frame area away from the cutting line, and the test pad and the protection pad are located in the frame area.
A second aspect of the present application provides another display panel, including: the testing pad comprises a first end and a second end which are oppositely arranged, the first end is connected with the testing line, and the second end points to one side face of the display panel; the orthographic projection of the protection bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the side surface in the direction vertical to the display surface; and a load circuit connected to the shield pad for consuming a current flowing in the shield pad.
In one embodiment, the test pad and the guard pad are arranged on the same layer; preferably, the guard pad and the test pad are spaced apart in a direction parallel to the cutting line.
In one embodiment, the display panel further includes a ground pad connected with the shielding pad as a load circuit; or, the display panel further comprises a pixel unit, and the pixel unit is connected with the protective bonding pad to be used as a load circuit.
A third aspect of the present application provides a display device comprising the display panel provided in the second aspect.
According to the display panel mother board, the display panel and the display device provided by the embodiment of the application, through the arrangement of the protective bonding pad and the load circuit connected with the protective bonding pad, the orthographic projection of the protective bonding pad in the direction perpendicular to the display surface is intersected with the orthographic projection of the test bonding pad in the direction perpendicular to the display surface, even if a conductive material area is formed on the cutting surface of the display panel obtained after cutting along the cutting line, when the bonding pad of the test circuit board is lapped on the test bonding pad of the display panel, short-circuit current generated by the short circuit of the bonding pad on the test circuit board due to the conductive material area can be led into the load circuit through the protective bonding pad and consumed by the load circuit, and therefore the situation that the short-circuit current damages the test circuit board and even damages a signal generator used for lighting test is avoided.
Drawings
Fig. 1 is a top view of a conventional display panel motherboard.
Fig. 2 is a schematic structural diagram of a display panel obtained by cutting a mother board of the display panel according to an embodiment of the present disclosure.
Fig. 3 is a schematic cross-sectional structure diagram of the display panel shown in fig. 2 when performing a lighting test according to an embodiment of the present application.
Fig. 4 is a top view of the display panel shown in fig. 2 according to an embodiment of the present disclosure during a lighting test. Fig. 5 is a schematic structural diagram of a display panel motherboard according to a first embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of the display panel mother board shown in fig. 5 along line A1a 2.
Fig. 7 is a schematic structural diagram of a display panel motherboard according to a second embodiment of the present application.
Fig. 8 is a schematic cross-sectional view of the display panel mother board shown in fig. 7 along line B1B 2.
Fig. 9 is a schematic structural diagram of a display panel motherboard according to a third embodiment of the present application.
Fig. 10 is a schematic structural diagram of a display panel motherboard according to a fourth embodiment of the present application.
Fig. 11 is a schematic structural diagram of a display panel motherboard according to a fifth embodiment of the present application.
Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of a display panel according to the second embodiment of the present application.
Fig. 14 is a schematic structural diagram of a display panel according to a third embodiment of the present application.
Detailed Description
Fig. 1 is a top view of a conventional display panel motherboard. As shown in fig. 1, the display panel mother substrate includes a plurality of display panels 10 and a registration mark N disposed between the plurality of display panels 10, as indicated by black solid dots in fig. 1. The alignment mark N on the display panel motherboard is used for aligning with the alignment mark on the cutting device to determine a cutting line L on the display panel motherboard, and the cutting device cuts the display panel motherboard along the cutting line L, so that the large-size display panel motherboard can be divided into a plurality of small-size display panels 10. The display panel 10 includes a display area AA and a bezel area at least partially surrounding the display area AA. The frame area includes a pad area BB, in which pads with various functions, such as a test pad for lighting test, a driving pad connected to a driving chip, etc., are disposed, and the pads are used to transmit external signals to the display area AA to implement corresponding functions.
Fig. 2 is a schematic structural diagram of a display panel obtained by cutting a mother board of the display panel according to an embodiment of the present disclosure. As shown in fig. 1 and 2, the display panel 10 includes at least one side surface resulting from cutting, which is referred to as a cut surface S, and the cut surface S is easily carbonized due to cutting, thereby forming a conductive material region Q. The pad area BB of the display panel 10 is closer to the cutting plane S than the display area AA. The pad area BB is provided with at least one test pad 11, the test pad 11 includes a first end and a second end which are oppositely arranged, the first end is connected with the test line, and the second end points to the cutting surface S.
Fig. 3 is a schematic cross-sectional structure diagram of the display panel shown in fig. 2 when performing a lighting test according to an embodiment of the present application. Fig. 4 is a top view of the display panel shown in fig. 2 according to an embodiment of the present disclosure during a lighting test. As shown in fig. 3 and 4, when the lighting test is performed on the display panel 10 shown in fig. 2, it is necessary to attach the pads 21 on the test circuit board 20 to the test pads 11 of the display panel 10. In this case, for example, the test circuit board 20 may be bent at the edge of the display panel 10, so that the pads 21 on the test circuit board 20 are in contact with the conductive material regions Q on the cutting surface S of the display panel 10, and the adjacent pads 20 are short-circuited, and the short-circuited current may burn the test circuit board 20, and may seriously cause an abnormality in the signal generator used for the lighting test.
In view of this, the present disclosure provides a display panel motherboard, a display panel and a display device, in which a protection pad and a load circuit connected to the protection pad are disposed in a pad area BB, an orthogonal projection of the protection pad in a direction perpendicular to a display surface intersects an orthogonal projection of a cutting line L in the direction perpendicular to the display surface, and after the display panel motherboard is cut along the cutting line L, the protection pad is exposed on a cutting surface S of the obtained display panel. In this case, even if the conductive material region Q is formed on the cut surface S, when the pad 21 of the test circuit board 20 is lapped on the test pad 11 of the display panel 10, a short-circuit current generated by a short-circuit of the pad 21 on the test circuit board 20 due to the conductive material region Q may be introduced into the load circuit through the protection pad and consumed by the load circuit, thereby preventing the short-circuit current from damaging the test circuit board 20 and even damaging a signal generator used for a lighting test.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 5 is a schematic structural diagram of a display panel motherboard according to a first embodiment of the present application. Fig. 6 is a schematic cross-sectional view of the display panel motherboard shown in fig. 4 along line A1a 2. In this embodiment, taking an example that the display panel motherboard includes two display panels 10, it should be understood that the number of the display panels 10 may be set reasonably according to actual needs. As can be seen from fig. 5 and 6, the difference between the display panel mother board and the display panel shown in fig. 1 is that the display panel mother board further includes an anti-pad 12 and a load circuit connected to the anti-pad 12. The anti-pad 12 is located on the side of the cutting line L where the test pad 11 is located, i.e. the anti-pad 12 and the test pad 11 are located on the same side of the cutting line L. An orthogonal projection of the protection pad 12 in a direction perpendicular to the display surface intersects an orthogonal projection of the cutting line L in a direction perpendicular to the display surface. The intersection referred to herein may be an orthographic projection of the anti-pad 12 and an orthographic projection of the cutting line L intersecting, i.e., the anti-pad 12 passes through the cutting line L to extend from one display panel to another; or the orthographic projection of the protection pad 12 may extend just above the cutting line L. By arranging that the orthographic projection of the protective bonding pad 12 in the direction perpendicular to the display surface is intersected with the orthographic projection of the cutting line L in the direction perpendicular to the display surface, after cutting along the cutting line L, one end of the protective bonding pad 12 is exposed on the cutting surface S and is contacted with the conductive material area Q on the cutting surface S, and then short-circuit current generated by short-circuit of the bonding pad 21 of the test circuit board 20 caused by the conductive material area Q is led into a load circuit to be consumed by the load circuit.
As shown in fig. 6, the display panel mother substrate includes an array substrate 110 and a light emitting device layer 120 stacked on the array substrate 110 from the viewpoint of a film structure. The light emitting device layer 120 includes a first light emitting device region 121 and a second light emitting device region 122 disposed at an interval. The alignment marks N are disposed on the array substrate 110 between the first and second light emitting device regions 121 and 122. The cutting surface S may divide the array substrate 11 into the first array substrate 111 and the second array substrate 112. The first light emitting device region 121 is positioned on the first array substrate 111, and the second light emitting device region 122 is positioned on the second array substrate 112. After cutting along the cutting surface S, the first array substrate 111 and the first light emitting device region 121 form a first display panel, the first light emitting device region 121 forms a display area AA of the first display panel, and an area of the first array substrate 111 not covered by the first light emitting device region 121 forms a frame area of the first display panel. The second array substrate 112 and the second light emitting device region 122 form a second display panel, the second light emitting device region 122 forms a display region AA of the second display panel, and a region of the second array substrate 112 not covered by the second light emitting device region 122 forms a bezel region of the second display panel.
The anti-pad 12 may be disposed on the same layer as the test pad 11, or may be disposed on a different layer from the test pad 11. In the present embodiment, as shown in fig. 6, the test pad 11 and the shield pad 12 are disposed in the same layer. This has an advantage in that the test pad 11 and the shield pad 12 can be realized by a one-time patterning process, and the manufacturing process is simpler. Under the condition that the test pad 11 and the protection pad 12 are arranged on the same layer, as shown in fig. 5, the test pad 11 and the protection pad 12 are arranged at intervals in a direction parallel to the cutting line L; or, the test pad 11 and the protection pad 12 are arranged opposite to each other, that is, the test pad 11 and the protection pad 12 are collinear, and a straight line where the test pad 11 and the protection pad 12 are located is perpendicular to the cutting line L. In comparison, the protection pad 11 and the test pad 12 are spaced apart to facilitate a narrow bezel. The interval between the test pad 11 and the protection pad 12 can be set reasonably according to actual needs. In one example, the number of the test pads 11 and the guard pads 12 is plural, the test pads 11 and the guard pads 12 are arranged at intervals in a direction parallel to the cutting line L, and the width of the guard pads 12 is greater than or equal to 1/3 of the interval between the adjacent test pads 11 and less than or equal to 2/3 of the interval between the adjacent test pads 11. For example, the interval between the adjacent test pads 11 is 60 micrometers, and the width of the guard pad 12 is 20 micrometers. The larger the width of the protective pad 12 is, the higher the reliability is, and the more the electromagnetic interference between the protective pad 12 and the adjacent test pad 11 is, the width of the protective pad 12 is set between 1/3-2/3 of the interval between the adjacent test pads 11, and the compromise can be achieved between the improvement of the reliability of the protective pad 12 and the reduction of the electromagnetic interference between the protective pad 12 and the test pad 11. A plurality of protection pads 12 can be arranged along cutting line L direction is linear, also can fan-shaped arrange etc. and on the same way, a plurality of test pads 11 can be arranged along cutting line L direction is linear, also can fan-shaped arrange etc..
In the present embodiment, the load circuit is implemented as a ground circuit. Specifically, as shown in fig. 5, the array substrate 110 is further provided with a ground pad 13, the ground pad 13 and the test pad 11 are disposed on the same layer, the ground pad 13 is connected to the guard pad 12, and the ground pad 13 and a ground line connected thereto serve as a load circuit. In this case, during the lighting test, the short-circuit current generated in the pad 21 of the test circuit board 20 can be led to the ground pad 13 through the protection pad 12 and further led away by the ground line, thereby preventing damage to the test circuit board 20 and even the signal generator.
Fig. 7 is a schematic structural diagram of a display panel motherboard according to a second embodiment of the present application. Fig. 8 is a schematic cross-sectional view of the display panel mother board shown in fig. 7 along line B1B 2. As shown in fig. 7 and 8, in this embodiment, the test pad 11 and the anti-pad 12 are located in different layers, the test pad 11 and the ground pad 13 are located in the same layer, and the anti-pad 12 is connected to the ground pad 13 through a via.
Specifically, the orthographic projection of the protection pad 12 in the direction perpendicular to the display surface and the orthographic projection of the test pad 11 in the direction perpendicular to the display surface are arranged at intervals or in pair. In this embodiment, the number of the test pads 11 and the number of the anti-pads 12 are both multiple, the orthographic projections of the plurality of anti-pads 12 in the direction perpendicular to the display surface and the orthographic projections of the plurality of test pads 11 in the direction perpendicular to the display surface are alternately arranged, and a partial area of the orthographic projection of each anti-pad 12 is located between the orthographic projections of two adjacent test pads 11.
According to the display panel provided by the present embodiment, by disposing the test pad 11 and the anti-pad 12 in different layers, there is an advantage in that the size of the bezel area can be reduced and the electromagnetic interference between the test pad 11 and the anti-pad 12 can be reduced, compared to disposing the test pad 11 and the anti-pad 12 in the same layer.
FIG. 9 is a diagram of a display panel mother board according to a third embodiment of the present applicationThe structure is schematic. As shown in fig. 9, the display panel mother board differs from the display panel mother board provided in any of the above embodiments in that the display panel mother board further includes a plurality of thermistors 14, and the plurality of thermistors 14 correspond to the plurality of test pads 11 one to one. Each test pad 11 is disposed on the test line to which the test pad 11 corresponding thereto is connected, i.e., the thermistor 14 is located at an end of the test pad 11 remote from the shielding pad 12. The material of the thermistor 14 may be Fe, for example 2 O 3 、Al 2 O 3 And the like. In this case, as shown in fig. 3, when the display panel obtained by cutting the mother board of the display panel along the cutting line L is subjected to a lighting test with the test circuit board 20, if a short circuit occurs in the pad 21 of the test circuit board 20, a part of the short-circuit current is conducted away through the shielding pad 12 and the ground pad 13, and the other part of the short-circuit current flows through the test pad 11 and the thermistor 14, and the impedance of the thermistor 14 increases with the increase of the current, so that the current is limited within the effective current range, and a large current is prevented from flowing back along the test pad 11 to the test circuit board 20 and the signal generator, thereby providing further protection for the test circuit board 20 and the signal generator. It should be understood that the thermistor 14 may be provided separately from the load circuit, and thus may also provide protection for the test circuit board 20 and the signal generator from short circuit currents that could damage them.
Fig. 10 is a schematic structural diagram of a display panel motherboard according to a fourth embodiment of the present application. As shown in fig. 10, the display panel mother board is different from the display panel mother boards shown in fig. 5 and 6 in that, in the present embodiment, the load circuit is implemented as at least one pixel unit. Specifically, taking an example in which the load circuit is implemented as one pixel column, a plurality of pixel circuits 15 are further provided in the first array substrate 111, and a plurality of light emitting devices 16 are provided in the first light emitting device region 121. At least one light emitting device 16 is connected to one pixel circuit 15 to constitute one pixel unit 130. A driving signal line 17 is further disposed in the first array substrate 111, and the driving signal line 17 connects a row of pixel units 130 and the anti-pad 12, or connects a column of pixel units 130 and the anti-pad 12. The one row or column of pixel units may be, for example, a plurality of green pixel units arranged linearly.
In this embodiment, the anti-pad 12 and the test pad 11 are disposed on the same layer, the anti-pad 12 and the driving signal line 17 are located on different layers, and the driving signal line 17 and the anti-pad 12 are connected by a via.
When the lighting test is performed on the display panel obtained by cutting the display panel motherboard and the test circuit board 20 according to the embodiment, if the pad 21 of the test circuit board 20 is short-circuited, the short-circuit current is supplied to the pixel units 130 in one row or one column along the protection pad 12 and the driving signal line 17. In this case, the pixel units 130 in the row or the column display bright lines to determine an abnormal product, thereby detecting the abnormal product.
Fig. 11 is a schematic structural diagram of a display panel motherboard according to a fifth embodiment of the present application. As shown in fig. 11, the display panel mother board differs from the display panel mother boards shown in fig. 5 and 6 in that in the present embodiment, the anti-pad 12 and the test pad 11 are located in different layers, and the anti-pad 12 and the driving signal line 17 are located in the same layer.
The application also provides a display panel. Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application. The display panel may be a display panel obtained by cutting the display panel mother board provided in any of the above embodiments along the cutting line L. As shown in fig. 12, the display panel includes a test pad 11, a protection pad 12, and a load circuit. The test pad 11 includes a first end and a second end, which are oppositely disposed, the first end is connected to the test line, and the second end is directed to a side surface of the display panel, which is the cutting surface S. An orthogonal projection of the protection pad 12 in a direction perpendicular to the display surface intersects an orthogonal projection of the cutting surface S in a direction perpendicular to the display surface. For example, the bezel region includes a first pad region N1 and a second pad region N2, the first pad region N1 is located between the display region AA and the second pad region N2, and an orthogonal projection of the side surface S in a direction perpendicular to the display surface forms a partial edge of an orthogonal projection of the second pad region N2 in a direction perpendicular to the display surface. The test pad 11 is located at the first pad region N1, and the shield pad 12 is located at the second pad region N2. The protective pad 12 extends to the side surface S and is exposed at the side surface S. The load circuit is implemented as a ground circuit including a ground pad 13 and a ground line, and the guard pad 12 is connected to the ground pad 13. The test pad 11 and the shield pad 12 are disposed in the same layer. In this case, the shield pad 12 and the test pad 11 are disposed at an interval in a direction parallel to the cutting line; alternatively, the shield pad 12 and the test pad 11 are arranged facing each other two by two.
As shown in fig. 3, when the pad 21 on the test circuit board 20 is overlapped on the test pad 11, and the test circuit board 20 is bent at the edge of the display panel, so that the pad 21 on the test circuit board 20 is contacted with the conductive material region Q on the cutting surface S, and thus the adjacent pads 21 are short-circuited, the short-circuit current passes through the pad 21, the conductive material region Q, the guard pad 12, and the ground pad 13 in sequence, and is finally guided away by the ground wire, so as to avoid burning of the test circuit board 20.
Fig. 13 is a schematic structural diagram of a display panel according to the second embodiment of the present application. The display panel differs from the display panel shown in fig. 12 in that, in the present embodiment, the load circuit is implemented as at least one pixel unit 130. Specifically, the display panel further includes a plurality of pixel units 130, a part of the pixel units 130 in the plurality of pixel units 130 is connected to the protection pad 12, and a part of the pixel units 130 connected to the protection pad 12 is used as a load circuit. The partial pixel unit 130 as the load circuit may be, for example, a plurality of green pixel units linearly arranged.
Fig. 14 is a schematic structural diagram of a display panel according to a third embodiment of the present application. As shown in fig. 14, the display panel is different from the display panel shown in fig. 12 in that the display panel further includes a thermistor 14, and the thermistor 14 is disposed on a test line to which the test pad 11 is connected, i.e., the thermistor 14 is located at an end of the test pad 11 away from the shield pad 12. The material of the thermistor 14 may be Fe, for example 2 O 3 、Al 2 O 3 And the like.
The application also provides a display device comprising the display panel provided by any embodiment of the application. For the specific structure of the display panel, reference is made to the above embodiments of the display panel, and details are not repeated here.
The foregoing description has been presented for purposes of illustration and description. Furthermore, the description is not intended to limit embodiments of the application to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (10)
1. A display panel motherboard, comprising:
carrying out alignment identification;
the test pad is positioned on one side of the cutting line formed by the alignment mark;
the protective bonding pad is positioned on the side of the test bonding pad of the cutting line, and the orthographic projection of the protective bonding pad in the direction vertical to the display surface is intersected with the orthographic projection of the cutting line in the direction vertical to the display surface; and
and the load circuit is connected with the protective bonding pad and used for consuming the current flowing in the protective bonding pad.
2. The display panel motherboard according to claim 1, wherein the test pad and the shield pad are provided in the same layer.
3. The display panel motherboard according to claim 2, wherein the shield pad and the test pad are disposed at a distance in a direction parallel to the cutting line.
4. The display panel motherboard according to any of claims 1 to 3, further comprising a ground pad connected to the shield pad as the load circuit; or,
the display panel motherboard further comprises a pixel unit, and the pixel unit is connected with the protective bonding pad to serve as the load circuit.
5. The display panel motherboard according to any one of claims 1 to 3, further comprising a thermistor provided on a test line to which the test pad is connected.
6. The display panel mother board according to any one of claims 1 to 3, comprising a bezel region in contact with a cutting line and a display region located on a side of the bezel region away from the cutting line, the test pad and the shield pad being located in the bezel region.
7. A display panel, comprising:
the testing pad comprises a first end and a second end which are oppositely arranged, the first end is connected with the testing line, and the second end points to one side face of the display panel;
an orthographic projection of the protection pad in a direction perpendicular to a display surface is intersected with an orthographic projection of the side face in the direction perpendicular to the display surface; and
and the load circuit is connected with the protective bonding pad and used for consuming the current flowing in the protective bonding pad.
8. The display panel according to claim 6, wherein the test pad and the protective pad are disposed on the same layer;
preferably, the guard pad and the test pad are spaced apart in a direction parallel to the cutting line.
9. The display panel according to claim 6 or 7, further comprising a ground pad connected to the shield pad as the load circuit; or,
the display panel further comprises a pixel unit, and the pixel unit is connected with the protective bonding pad to serve as the load circuit.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210720305.4A CN115019656B (en) | 2022-06-23 | 2022-06-23 | Display panel motherboard, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210720305.4A CN115019656B (en) | 2022-06-23 | 2022-06-23 | Display panel motherboard, display panel and display device |
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| CN115019656A true CN115019656A (en) | 2022-09-06 |
| CN115019656B CN115019656B (en) | 2023-12-22 |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005340557A (en) * | 2004-05-28 | 2005-12-08 | Kyocera Corp | Manufacturing method of semiconductor wafer and semiconductor chip |
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| CN115019656B (en) | 2023-12-22 |
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