CN110911561A - 形成用于电子装置的电介质 - Google Patents
形成用于电子装置的电介质 Download PDFInfo
- Publication number
- CN110911561A CN110911561A CN201910863120.7A CN201910863120A CN110911561A CN 110911561 A CN110911561 A CN 110911561A CN 201910863120 A CN201910863120 A CN 201910863120A CN 110911561 A CN110911561 A CN 110911561A
- Authority
- CN
- China
- Prior art keywords
- workpiece
- dielectric
- over
- region
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003989 dielectric material Substances 0.000 title claims description 16
- 239000000463 material Substances 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000000151 deposition Methods 0.000 claims abstract description 27
- 239000002243 precursor Substances 0.000 claims abstract description 20
- 238000000059 patterning Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 28
- 238000004381 surface treatment Methods 0.000 claims description 15
- 230000005855 radiation Effects 0.000 claims description 14
- 238000004132 cross linking Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 73
- 239000004020 conductor Substances 0.000 description 27
- 238000001723 curing Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007567 mass-production technique Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 239000002094 self assembled monolayer Substances 0.000 description 1
- 239000013545 self-assembled monolayer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
一种形成限定一个或多个电子装置的层的堆叠的方法,所述方法包括:在工件的区域上方沉积第一厚度的可固化、电介质或电介质前驱体材料;随后至少在所述工件的所述区域上方使所述工件暴露于固化条件;以及在无任何中间图案化操作的情况下,随后在所述工件的所述区域上方沉积第二厚度的所述可固化材料;以及随后至少在所述工件的所述区域上方使所述工件再次暴露于固化条件。
Description
技术领域
产生一起限定一个或多个电子装置的层的堆叠涉及在所述堆叠内包含用于所述一个或多个电子装置的电介质。
背景技术
本申请的发明人已经对形成用于电子装置的电介质进行了广泛研究,且已经发现能够改进良率的技术。
发明内容
在此提供一种形成限定一个或多个电子装置的层的堆叠的方法,所述方法包括:在工件的区域上方沉积第一厚度的可固化、电介质或电介质前驱体材料;随后至少在所述工件的所述区域上方使所述工件暴露于固化条件;以及在无任何中间图案化操作的情况下,随后在所述工件的所述区域上方沉积第二厚度的所述可固化材料;以及随后至少在所述工件的所述区域上方使所述工件再次暴露于固化条件。
根据一个实施例,所述一个或多个电子装置包含一个或多个晶体管,且所述电介质或电介质前驱体材料是栅极电介质或栅极电介质前驱体材料。
根据一个实施例,使工件暴露于固化条件包括至少在所述工件的所述区域上方使工件暴露于固化辐射。
根据一个实施例,所述第一和第二厚度大体上相等。
根据一个实施例,可固化材料为可交联材料,且固化辐射处于引起可交联材料的交联的一个或多个波长处。
根据一个实施例,所述方法包括:在所述第一固化之后且在沉积所述第二厚度的所述可固化材料之前,使工件至少在所述工件的所述区域上方经历表面处理。
根据一个实施例,所述方法包括:沉积所述第二厚度的可固化材料包括形成所述可固化材料的溶液的膜;以及所述表面处理在所述工件的所述区域上方针对所述可固化材料的所述溶液增加工件的表面的润湿性。
根据一个实施例,所述表面处理包括至少在所述工件的所述区域上方使工件暴露于等离子体或来自紫外灯的紫外辐射。
根据一个实施例:在沉积所述第一厚度的可固化材料之前,所述工件包含提供用于所述一个或多个晶体管的半导体沟道的半导体沟道材料层。
根据一个实施例:所述半导体沟道材料层是图案化层:形成所述图案化半导体沟道材料层包括经由电介质层使一层半导体沟道材料图案化;以及所述方法包括在所述电介质层上沉积所述第一厚度的所述可固化材料。
在此还提供一种形成限定一个或多个电子装置的层的堆叠的方法,所述方法包括:在工件上在所述工件的区域上方沉积电介质材料或电介质前驱体材料的受控量的溶液,以及随后在工件上在所述工件的所述区域上方沉积电介质材料或电介质前驱体材料的第二受控量的所述溶液;其中在沉积电介质材料或电介质前驱体材料的所述第二受控量的所述溶液之前,使工件经历表面处理以便在工件的所述区域上方针对栅极电介质材料或栅极电介质前驱体材料的所述溶液增加工件的表面的润湿性。
根据一个实施例,所述一个或多个电子装置包含一个或多个晶体管,且所述电介质或电介质前驱体材料是栅极电介质或栅极电介质前驱体材料。
根据一个实施例,所述表面处理包括使所述工件暴露于等离子体或来自紫外灯的紫外辐射。
附图说明
在下文中仅以示例的方式并参考附图详细地描述本发明的实施例,附图中:
图1和2示出在根据本发明的第一实施例的实例工艺之前的半导体图案化步骤;
图3示出在根据本发明的第一实施例的实例工艺中的固化栅极电介质层的形成;
图4示出在根据本发明的第一实施例的实例工艺中的固化栅极电介质层的表面处理步骤;
图5示出在根据本发明的第一实施例的实例工艺中的固化第二栅极电介质层的形成;
图6示出来自根据本发明的第一实施例的实例工艺的第二栅极电介质层上方的栅极导体的形成;以及
图7和8示出根据第一实施例的实例工艺在批量生产技术中的使用。
具体实施方式
在下文中针对形成用于顶栅晶体管装置的电介质的实例详细描述本发明的第一实施例,但所述技术同等地适用于形成用于底栅晶体管装置的电介质,且适用于形成用于依赖于经由电介质的电容耦合的例如电容器装置等其它类型的电子装置的电介质。
在下文中针对形成用于控制像素电极阵列的晶体管阵列的实例详细描述本发明的第一实施例,但所述技术同等地适用于形成例如用于逻辑电路的晶体管和/或电容器等用于其它功能的一个或多个电子装置。
在下文中针对在经由额外栅极电介质层图案化的半导体沟道材料层上方形成栅极电介质的实例详细描述本发明的第一实施例,但所述技术同等地适用于在以除经由额外栅极电介质层以外的方式图案化的半导体沟道材料层上方形成栅极电介质,且适用于在未图案化半导体沟道材料层上方形成栅极电介质。
针对形成包含有机半导体沟道的一个或多个晶体管(被称作有机薄膜晶体管(OTFT))的栅极电介质的实例描述本发明的第一实施例,但所述技术同等地适用于形成用于包含其它类型的半导体沟道的一个或多个晶体管的栅极电介质。
第一实施例涉及在(例如塑料)支撑膜上原位形成一起限定一个或多个晶体管(例如,晶体管阵列)的导体、半导体和电介质层的堆叠。
图1和2示出用于在限定一个或多个晶体管的源极电极和漏极电极4、6的源极-漏极导体图案上方形成有机聚合物半导体沟道材料的图案化层8b的实例技术,所述图案化层8b是原位形成在支撑元件2上。支撑元件2可例如包括在上面原位形成例如平坦化层和/或湿气阻挡层等一个或多个层的塑料支撑膜。图1和2仅展示单一对源极电极/漏极电极,但源极-漏极导体图案可同等地限定:(i)源极导体阵列,每一源极导体提供用于晶体管的有源矩阵阵列的晶体管的相应行的源极电极,且每一源极导体延伸超出所述晶体管阵列;以及(ii)漏极导体阵列,每一漏极导体提供用于晶体管阵列的相应晶体管的漏极电极。
有机聚合物半导体沟道材料的溶液通过例如旋涂技术大体上均匀地沉积在包含上文所描述的源极-漏极导体图案的工件上方,以形成连续/未图案化层8a。半导体沟道材料的此连续层8a的形成之前可以是例如在源极-漏极导体图案上形成自组装有机材料单层,这促进电荷载流子在源极-漏极导体图案和半导体沟道材料之间的转移。
电介质材料(或电介质材料的前驱体)的溶液通过例如旋涂技术大体上均匀地沉积在所得工件(包含有机半导体沟道材料的连续层8a)上方,以形成连续/未图案化层。在此实例中,如下文所论述,使用介电常数比稍后沉积的电介质材料低的可固化电介质材料。
通过连续层10a的选择性区的固化和连续层10a中因此形成的潜在溶解度图像的显影使可固化电介质材料的连续层10a图案化,以通过例如反应性离子蚀刻技术形成用于使半导体沟道材料8a的连续层图案化的掩模10b。连续层10a的选择性固化包括使连续层10a穿过图案化光掩模暴露于引起可固化材料中的交联的波长处的辐射,所述交联减小从其沉积可固化材料的溶剂中的溶解度。
可交联材料的受控量的溶液通过例如旋涂技术大体上均匀地沉积在包含图案化半导体和电介质层8b、10b的所得工件的上部工作表面的区域上方,以形成连续层12a。如下文相对于图7和8所提到,上面沉积可交联材料的受控量的所述溶液的区域可以是从其同时产生多个晶体管阵列装置的大面积工件40一侧的整个区域。
所得工件经受烘焙工艺以移除溶剂,且接着至少在连续层12a的区域上方(以及从工件的上面形成连续层12a的一侧)暴露于引起可交联材料的交联的一个或多个波长处的固化辐射(例如紫外(UV)辐射)。所得工件接着至少在固化后的连续栅极电介质层12b的区域上方经受表面处理,所述表面处理针对可交联材料的相同溶液增强固化后电介质层12b的表面的润湿性。此表面处理可例如涉及至少在固化后电介质层12b的区域上方使工件暴露于等离子体(例如氩等离子体),或至少在固化后电介质层的区域上方使工件暴露于来自UV灯的紫外(UV)辐射(例如约254nm处的UV或约185nm处的UV臭氧)。在此实例中,工件经受额外烘焙以完成固化工艺。
在经过固化和表面处理的电介质层12c不进行任何中间图案化的情况下(即,在上面沉积可固化材料的溶液的整个区域上方保持第一栅极电介质层的情况下),在不沉积任何介入层的情况下,在上面沉积可交联材料的第一受控量的溶液的工件的相同区域上方大体上均匀地沉积第二受控量的完全相同的可交联材料溶液,以在经过固化和表面处理的电介质层12c上直接形成连续层14a。所述沉积条件和沉积技术对于沉积第一受控量的可交联材料溶液是相同的;例如可使用相同旋涂技术。
所得工件经受烘焙工艺以移除溶剂,且接着至少在连续层14a的区域上方(以及从工件的上面形成连续层14a的一侧)暴露于引起可交联材料的交联的一个或多个波长处的固化辐射(例如紫外(UV)辐射)。在此实例中,工件再次经受额外烘焙以完成固化工艺。
紧接在固化之后,所得固化后的电介质层14b占据由下层的经过固化和表面处理的电介质层12c占据的大体上所有区;大体上不存在工件的由两个栅极电介质层12c、14b中的仅一个占据的区。所述技术不排除在第二固化操作之后使所述两个栅极电介质层12c、14b中的一个或两个图案化,但在形成上部栅极电介质层之前不进行下部栅极电介质层的图案化。
在此实例中,导体材料通过例如比如溅镀等气相沉积技术大体上均匀地沉积在包含上部固化后栅极电介质层14b的所得工件的上部工作表面上方,以形成连续层。使导体材料的连续层图案化(通过例如使用临时抗蚀剂的光刻技术)以限定提供用于所述一个或多个晶体管的栅极电极的一个或多个栅极导体16。根据另一实例,通过印刷技术形成栅极导体图案。
在上文所提及的产生晶体管的有源矩阵阵列的实例中,图案化导体层限定栅极导体阵列,每一栅极导体提供用于晶体管阵列的晶体管的相应列的栅极电极,且每一栅极导体延伸超出晶体管阵列。每一漏极导体(其可例如在堆叠内的较高层级处形成像素电极或以导电方式连接到相应像素电极)与栅极导体和源极导体的相应唯一组合相关联,且可经由栅极导体和源极导体的在晶体管阵列外部的部分独立地寻址。如上文所提及,此技术同等地适用于形成例如用于逻辑电路的晶体管等具有其它功能的晶体管,其中电接触件可(或可不)在包含晶体管的电路区域内。
参考图7和8:在一个批量生产实例中,上面形成两个上部栅极电介质层12c、14b的工件包含大面积单元40(包括大面积塑料支撑片),其稍后被切割(连同单元40上原位形成的层一起)以产生具有小于大面积单元40的对应尺寸(例如宽度)的尺寸(例如宽度)D1、D2的多个装置。大面积单元40包含限定用于所述多个装置中的每一个的上文提及的源极-漏极导体图案的导体图案,且上文提及的半导体沟道材料8a的连续层在如上文所描述的图案化之前在大面积单元的大体上整个区域上方连续地延伸。此批量生产技术涉及在大面积单元40的整个区域上方大体上均匀地两次沉积(在相同条件下且通过相同沉积技术)上文提及的可交联材料的受控量的溶液,且在所述两次沉积之间进行中间固化和表面处理;且在第二固化操作之后,所得两个栅极电介质层12b、14b各自占据大面积单元40的大体上整个区域。如上文所提及,所述技术并不排除两个栅极电介质层12c、14b中的一个或两个的后续图案化;且可采用此稍后图案化来例如向下形成到漏极导体6的通孔以促进漏极导体6和稍后阶段处形成的相应像素电极之间的导电连接。
本申请的发明人已发现,与其它方面相同的技术相比,上文所描述的技术实现具有较好良率的生产工艺,在所述其它方面相同的技术中,具有相同组成的两个栅极电介质层12c、14b被单个上部栅极电介质层代替,所述单个上部栅极电介质层具有与两个上部栅极电介质层10b、12c相同的组成且具有与两个上部栅极电介质层12c、14b的组合厚度大体上相同的厚度。本申请的发明人将此良率改进归于两个因素:(i)可交联材料的较好交联;以及(ii)栅极电介质中的针孔对半导体和栅极电极之间的漏电流的影响减小。对于后者,本申请的发明人认为,两个栅极电介质层的下部栅极电介质层的上部表面的上文所描述的表面处理具有以下效果:较好地防止两个栅极电介质层的下部栅极电介质层中的针孔(由溶液沉积工艺产生)传播到两个栅极电介质层的上部栅极电介质层中并穿过所述上部栅极电介质层。
还可在经由除照射技术以外的技术(例如涉及通过热传导加热工件的热固化技术)执行固化时,在某一程度上实现上文提及的交联的改进。
通过上文描述的技术产生的电子装置(例如,晶体管、晶体管阵列和/或电容器)可在例如显示装置、传感器装置和逻辑电路等多种多样的装置中使用。
除了上文明确提及的任何修改之外,所属领域的技术人员还将清楚,可以在本发明的范围内对所描述的实施例进行各种其它修改。
申请人在此单独公开本文描述的每一个个别特征及两个或更多个此类特征的任意组合,以所属领域的技术人员的普通知识,能够总体上基于本说明书实行此类特征或组合,而不考虑此类特征或特征的组合是否能解决本文所公开的任何问题;且不对权利要求书的范围造成限制。申请人指示本发明的各方面可由任何此类个别特征或特征的组合构成。
Claims (13)
1.一种形成限定一个或多个电子装置的层的堆叠的方法,其特征在于:所述方法包括:在工件的区域上方沉积第一厚度的可固化、电介质或电介质前驱体材料;随后至少在所述工件的所述区域上方使所述工件暴露于固化条件;以及在无任何中间图案化操作的情况下,随后在所述工件的所述区域上方沉积第二厚度的所述可固化材料;以及随后至少在所述工件的所述区域上方使所述工件再次暴露于固化条件。
2.根据权利要求1所述的方法,其特征在于:所述一个或多个电子装置包含一个或多个晶体管,且所述电介质或电介质前驱体材料是栅极电介质或栅极电介质前驱体材料。
3.根据权利要求1或权利要求2所述的方法,其特征在于:使所述工件暴露于固化条件包括至少在所述工件的所述区域上方使所述工件暴露于固化辐射。
4.根据任一前述权利要求所述的方法,其特征在于:所述第一和第二厚度大体上相等。
5.根据权利要求3所述的方法,其特征在于:所述可固化材料为可交联材料,且所述固化辐射处于引起所述可交联材料的交联的一个或多个波长处。
6.根据任一前述权利要求所述的方法,其特征在于:包括:在所述第一固化之后且在沉积所述第二厚度的所述可固化材料之前,至少在所述工件的所述区域上方使所述工件经历表面处理。
7.根据权利要求6所述的方法,其特征在于:沉积所述第二厚度的可固化材料包括形成所述可固化材料的溶液的膜;且所述表面处理在所述工件的所述区域上方针对所述可固化材料的所述溶液增加所述工件的表面的润湿性。
8.根据权利要求7所述的方法,其特征在于:所述表面处理包括至少在所述工件的所述区域上方使所述工件暴露于等离子体或来自紫外灯的紫外辐射。
9.根据任一前述权利要求所述的方法,其特征在于:在沉积所述第一厚度的可固化材料之前,所述工件包含提供用于所述一个或多个晶体管的半导体沟道的半导体沟道材料层。
10.根据权利要求9所述的方法,其特征在于:所述半导体沟道材料层为图案化层,且其中形成所述图案化半导体沟道材料层包括经由电介质层使一层半导体沟道材料图案化;且其中所述方法包括在所述电介质层上沉积所述第一厚度的所述可固化材料。
11.一种形成限定一个或多个电子装置的层的堆叠的方法,其特征在于:所述方法包括:在工件上在所述工件的区域上方沉积电介质材料或电介质前驱体材料的受控量的溶液,以及随后在所述工件上在所述工件的所述区域上方沉积电介质材料或电介质前驱体材料的第二受控量的所述溶液;其中在沉积电介质材料或电介质前驱体材料的所述第二受控量的所述溶液之前,使所述工件经历表面处理以便在所述工件的所述区域上方针对栅极电介质材料或栅极电介质前驱体材料的所述溶液增加所述工件的表面的润湿性。
12.根据权利要求1所述的方法,其特征在于:所述一个或多个电子装置包含一个或多个晶体管,且所述电介质或电介质前驱体材料是栅极电介质或栅极电介质前驱体材料。
13.根据权利要求11或权利要求12所述的方法,其特征在于:所述表面处理包括使所述工件暴露于等离子体或来自紫外灯的紫外辐射。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1815017.7 | 2018-09-14 | ||
GB1815017.7A GB2577112A (en) | 2018-09-14 | 2018-09-14 | Forming dielectric for electronic devices |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110911561A true CN110911561A (zh) | 2020-03-24 |
Family
ID=64013248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910863120.7A Pending CN110911561A (zh) | 2018-09-14 | 2019-09-12 | 形成用于电子装置的电介质 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20200091449A1 (zh) |
CN (1) | CN110911561A (zh) |
GB (1) | GB2577112A (zh) |
TW (1) | TW202030898A (zh) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6383913B1 (en) * | 2001-04-06 | 2002-05-07 | United Microelectronics Corp. | Method for improving surface wettability of low k material |
US20050239295A1 (en) * | 2004-04-27 | 2005-10-27 | Wang Pei-L | Chemical treatment of material surfaces |
US7265063B2 (en) * | 2004-10-22 | 2007-09-04 | Hewlett-Packard Development Company, L.P. | Method of forming a component having dielectric sub-layers |
US7884030B1 (en) * | 2006-04-21 | 2011-02-08 | Advanced Micro Devices, Inc. and Spansion LLC | Gap-filling with uniform properties |
US20080138983A1 (en) * | 2006-12-06 | 2008-06-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming tensile stress films for NFET performance enhancement |
WO2014037076A1 (en) * | 2012-09-04 | 2014-03-13 | Merck Patent Gmbh | Process of surface modification of dielectric structures in organic electronic devices |
JP2016162848A (ja) * | 2015-02-27 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
2018
- 2018-09-14 GB GB1815017.7A patent/GB2577112A/en not_active Withdrawn
-
2019
- 2019-09-12 CN CN201910863120.7A patent/CN110911561A/zh active Pending
- 2019-09-12 TW TW108133022A patent/TW202030898A/zh unknown
- 2019-09-13 US US16/569,778 patent/US20200091449A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW202030898A (zh) | 2020-08-16 |
GB2577112A (en) | 2020-03-18 |
GB201815017D0 (en) | 2018-10-31 |
US20200091449A1 (en) | 2020-03-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7271098B2 (en) | Method of fabricating a desired pattern of electronically functional material | |
US6927108B2 (en) | Solution-processed thin film transistor formation method | |
EP1629546B8 (en) | A field effect transistor arrangement and method of manufacturing a field effect transistor arrangement | |
TWI232543B (en) | Method of forming contact holes and electronic device formed thereby | |
US10096788B2 (en) | Reducing undesirable capacitive coupling in transistor devices | |
JP5051968B2 (ja) | 凹凸パターン化を伴う半導体層 | |
US7632705B2 (en) | Method of high precision printing for manufacturing organic thin film transistor | |
CN110911561A (zh) | 形成用于电子装置的电介质 | |
CN108493197B (zh) | 顶栅型阵列基板制备工艺 | |
KR100817215B1 (ko) | 자기 정렬된 유기물 전계 효과 트랜지스터 및 그 제조 방법 | |
CN112310148A (zh) | 堆叠的图案化 | |
US20170110516A1 (en) | Production of transistor arrays | |
TW202034402A (zh) | 用於生產薄膜電晶體裝置的導體蝕刻 | |
CN112201663A (zh) | 半导体装置 | |
US20200343464A1 (en) | Source-drain conductors for organic tfts | |
US20200313103A1 (en) | Patterning semiconductor for tft device | |
US10541258B2 (en) | Patterning layers stacks for electronic devices | |
WO2019229256A1 (en) | Transistor arrays | |
GB2574266A (en) | Transistor Arrays | |
CN112649913A (zh) | 液晶装置 | |
GB2568516A (en) | Organic semiconductor devices | |
GB2583126A (en) | LCD device production |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200324 |